2 * Marvell camera core structures.
4 * Copyright 2011 Jonathan Corbet corbet@lwn.net
9 #include <linux/list.h>
10 #include <media/v4l2-common.h>
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-dev.h>
13 #include <media/videobuf2-core.h>
16 * Create our own symbols for the supported buffer modes, but, for now,
17 * base them entirely on which videobuf2 options have been selected.
19 #if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
20 #define MCAM_MODE_VMALLOC 1
23 #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
24 #define MCAM_MODE_DMA_CONTIG 1
27 #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
28 #define MCAM_MODE_DMA_SG 1
31 #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
32 !defined(MCAM_MODE_DMA_SG)
33 #error One of the videobuf buffer modes must be selected in the config
38 S_NOTREADY
, /* Not yet initialized */
39 S_IDLE
, /* Just hanging around */
40 S_FLAKED
, /* Some sort of problem */
41 S_STREAMING
, /* Streaming data */
42 S_BUFWAIT
/* streaming requested but no buffers yet */
44 #define MAX_DMA_BUFS 3
47 * Different platforms work best with different buffer modes, so we
48 * let the platform pick.
50 enum mcam_buffer_mode
{
57 * Is a given buffer mode supported by the current kernel configuration?
59 static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode
)
62 #ifdef MCAM_MODE_VMALLOC
65 #ifdef MCAM_MODE_DMA_CONTIG
68 #ifdef MCAM_MODE_DMA_SG
80 struct mcam_frame_state
{
83 unsigned int delivered
;
87 * A description of one of our devices.
88 * Locking: controlled by s_mutex. Certain fields, however, require
89 * the dev_lock spinlock; they are marked as such by comments.
90 * dev_lock is also required for access to device registers.
94 * These fields should be set by the platform code prior to
95 * calling mcam_register().
97 struct i2c_adapter
*i2c_adapter
;
98 unsigned char __iomem
*regs
;
100 struct device
*dev
; /* For messages, dma alloc */
101 unsigned int chip_id
;
102 short int clock_speed
; /* Sensor clock speed, default 30 */
103 short int use_smbus
; /* SMBUS or straight I2c? */
104 enum mcam_buffer_mode buffer_mode
;
106 * Callbacks from the core to the platform code.
108 void (*plat_power_up
) (struct mcam_camera
*cam
);
109 void (*plat_power_down
) (struct mcam_camera
*cam
);
112 * Everything below here is private to the mcam core and
113 * should not be touched by the platform code.
115 struct v4l2_device v4l2_dev
;
116 struct v4l2_ctrl_handler ctrl_handler
;
117 enum mcam_state state
;
118 unsigned long flags
; /* Buffer status, mainly (dev_lock) */
119 int users
; /* How many open FDs */
121 struct mcam_frame_state frame_state
; /* Frame state counter */
123 * Subsystem structures.
125 struct video_device vdev
;
126 struct v4l2_subdev
*sensor
;
127 unsigned short sensor_addr
;
129 /* Videobuf2 stuff */
130 struct vb2_queue vb_queue
;
131 struct list_head buffers
; /* Available frames */
133 unsigned int nbufs
; /* How many are alloc'd */
134 int next_buf
; /* Next to consume (dev_lock) */
136 /* DMA buffers - vmalloc mode */
137 #ifdef MCAM_MODE_VMALLOC
138 unsigned int dma_buf_size
; /* allocated size */
139 void *dma_bufs
[MAX_DMA_BUFS
]; /* Internal buffer addresses */
140 dma_addr_t dma_handles
[MAX_DMA_BUFS
]; /* Buffer bus addresses */
141 struct tasklet_struct s_tasklet
;
143 unsigned int sequence
; /* Frame sequence number */
144 unsigned int buf_seq
[MAX_DMA_BUFS
]; /* Sequence for individual bufs */
146 /* DMA buffers - DMA modes */
147 struct mcam_vb_buffer
*vb_bufs
[MAX_DMA_BUFS
];
148 struct vb2_alloc_ctx
*vb_alloc_ctx
;
150 /* Mode-specific ops, set at open time */
151 void (*dma_setup
)(struct mcam_camera
*cam
);
152 void (*frame_complete
)(struct mcam_camera
*cam
, int frame
);
154 /* Current operating parameters */
155 u32 sensor_type
; /* Currently ov7670 only */
156 struct v4l2_pix_format pix_format
;
157 enum v4l2_mbus_pixelcode mbus_code
;
160 struct mutex s_mutex
; /* Access to this structure */
165 * Register I/O functions. These are here because the platform code
166 * may legitimately need to mess with the register space.
169 * Device register I/O
171 static inline void mcam_reg_write(struct mcam_camera
*cam
, unsigned int reg
,
174 iowrite32(val
, cam
->regs
+ reg
);
177 static inline unsigned int mcam_reg_read(struct mcam_camera
*cam
,
180 return ioread32(cam
->regs
+ reg
);
184 static inline void mcam_reg_write_mask(struct mcam_camera
*cam
, unsigned int reg
,
185 unsigned int val
, unsigned int mask
)
187 unsigned int v
= mcam_reg_read(cam
, reg
);
189 v
= (v
& ~mask
) | (val
& mask
);
190 mcam_reg_write(cam
, reg
, v
);
193 static inline void mcam_reg_clear_bit(struct mcam_camera
*cam
,
194 unsigned int reg
, unsigned int val
)
196 mcam_reg_write_mask(cam
, reg
, 0, val
);
199 static inline void mcam_reg_set_bit(struct mcam_camera
*cam
,
200 unsigned int reg
, unsigned int val
)
202 mcam_reg_write_mask(cam
, reg
, val
, val
);
206 * Functions for use by platform code.
208 int mccic_register(struct mcam_camera
*cam
);
209 int mccic_irq(struct mcam_camera
*cam
, unsigned int irqs
);
210 void mccic_shutdown(struct mcam_camera
*cam
);
212 void mccic_suspend(struct mcam_camera
*cam
);
213 int mccic_resume(struct mcam_camera
*cam
);
217 * Register definitions for the m88alp01 camera interface. Offsets in bytes
218 * as given in the spec.
220 #define REG_Y0BAR 0x00
221 #define REG_Y1BAR 0x04
222 #define REG_Y2BAR 0x08
225 #define REG_IMGPITCH 0x24 /* Image pitch register */
226 #define IMGP_YP_SHFT 2 /* Y pitch params */
227 #define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
228 #define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
229 #define IMGP_UVP_MASK 0x3ffc0000
230 #define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
231 #define IRQ_EOF0 0x00000001 /* End of frame 0 */
232 #define IRQ_EOF1 0x00000002 /* End of frame 1 */
233 #define IRQ_EOF2 0x00000004 /* End of frame 2 */
234 #define IRQ_SOF0 0x00000008 /* Start of frame 0 */
235 #define IRQ_SOF1 0x00000010 /* Start of frame 1 */
236 #define IRQ_SOF2 0x00000020 /* Start of frame 2 */
237 #define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
238 #define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
239 #define IRQ_TWSIR 0x00020000 /* TWSI read */
240 #define IRQ_TWSIE 0x00040000 /* TWSI error */
241 #define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
242 #define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
243 #define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
244 #define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
245 #define REG_IRQSTAT 0x30 /* IRQ status / clear */
247 #define REG_IMGSIZE 0x34 /* Image size */
248 #define IMGSZ_V_MASK 0x1fff0000
249 #define IMGSZ_V_SHIFT 16
250 #define IMGSZ_H_MASK 0x00003fff
251 #define REG_IMGOFFSET 0x38 /* IMage offset */
253 #define REG_CTRL0 0x3c /* Control 0 */
254 #define C0_ENABLE 0x00000001 /* Makes the whole thing go */
256 /* Mask for all the format bits */
257 #define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
260 #define C0_RGB4_RGBX 0x00000000
261 #define C0_RGB4_XRGB 0x00000004
262 #define C0_RGB4_BGRX 0x00000008
263 #define C0_RGB4_XBGR 0x0000000c
264 #define C0_RGB5_RGGB 0x00000000
265 #define C0_RGB5_GRBG 0x00000004
266 #define C0_RGB5_GBRG 0x00000008
267 #define C0_RGB5_BGGR 0x0000000c
269 /* Spec has two fields for DIN and DOUT, but they must match, so
270 combine them here. */
271 #define C0_DF_YUV 0x00000000 /* Data is YUV */
272 #define C0_DF_RGB 0x000000a0 /* ... RGB */
273 #define C0_DF_BAYER 0x00000140 /* ... Bayer */
274 /* 8-8-8 must be missing from the below - ask */
275 #define C0_RGBF_565 0x00000000
276 #define C0_RGBF_444 0x00000800
277 #define C0_RGB_BGR 0x00001000 /* Blue comes first */
278 #define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
279 #define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
280 #define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
281 /* Think that 420 packed must be 111 - ask */
282 #define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
283 #define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
284 #define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
285 #define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
286 #define C0_YUVE_XYUV 0x00000000 /* 420: .YUV */
287 #define C0_YUVE_XYVU 0x00010000 /* 420: .YVU */
288 #define C0_YUVE_XUVY 0x00020000 /* 420: .UVY */
289 #define C0_YUVE_XVUY 0x00030000 /* 420: .VUY */
290 /* Bayer bits 18,19 if needed */
291 #define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
292 #define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
293 #define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
294 #define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
295 #define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
296 #define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
297 #define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
299 /* Bits below C1_444ALPHA are not present in Cafe */
300 #define REG_CTRL1 0x40 /* Control 1 */
301 #define C1_CLKGATE 0x00000001 /* Sensor clock gate */
302 #define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */
303 #define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */
304 #define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
305 #define C1_ALPHA_SHFT 20
306 #define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
307 #define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
308 #define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
309 #define C1_DMAB_MASK 0x06000000
310 #define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
311 #define C1_PWRDWN 0x10000000 /* Power down */
313 #define REG_CLKCTRL 0x88 /* Clock control */
314 #define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
316 /* This appears to be a Cafe-only register */
317 #define REG_UBAR 0xc4 /* Upper base address register */
319 /* Armada 610 DMA descriptor registers */
320 #define REG_DMA_DESC_Y 0x200
321 #define REG_DMA_DESC_U 0x204
322 #define REG_DMA_DESC_V 0x208
323 #define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */
324 #define REG_DESC_LEN_U 0x210
325 #define REG_DESC_LEN_V 0x214
328 * Useful stuff that probably belongs somewhere global.
330 #define VGA_WIDTH 640
331 #define VGA_HEIGHT 480
333 #endif /* _MCAM_CORE_H */