drivers/media/platform/marvell-ccic/mcam-core.h

   1 /*
   2  * Marvell camera core structures.
   3  *
   4  * Copyright 2011 Jonathan Corbet corbet@lwn.net
   5  */
   6 #ifndef _MCAM_CORE_H
   7 #define _MCAM_CORE_H
   8
   9 #include <linux/list.h>
  10 #include <media/v4l2-common.h>
  11 #include <media/v4l2-dev.h>
  12 #include <media/videobuf2-core.h>
  13
  14 /*
  15  * Create our own symbols for the supported buffer modes, but, for now,
  16  * base them entirely on which videobuf2 options have been selected.
  17  */
  18 #if defined(CONFIG_VIDEOBUF2_VMALLOC) || defined(CONFIG_VIDEOBUF2_VMALLOC_MODULE)
  19 #define MCAM_MODE_VMALLOC 1
  20 #endif
  21
  22 #if defined(CONFIG_VIDEOBUF2_DMA_CONTIG) || defined(CONFIG_VIDEOBUF2_DMA_CONTIG_MODULE)
  23 #define MCAM_MODE_DMA_CONTIG 1
  24 #endif
  25
  26 #if defined(CONFIG_VIDEOBUF2_DMA_SG) || defined(CONFIG_VIDEOBUF2_DMA_SG_MODULE)
  27 #define MCAM_MODE_DMA_SG 1
  28 #endif
  29
  30 #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
  31         !defined(MCAM_MODE_DMA_SG)
  32 #error One of the videobuf buffer modes must be selected in the config
  33 #endif
  34
  35
  36 enum mcam_state {
  37         S_NOTREADY,     /* Not yet initialized */
  38         S_IDLE,         /* Just hanging around */
  39         S_FLAKED,       /* Some sort of problem */
  40         S_STREAMING,    /* Streaming data */
  41         S_BUFWAIT       /* streaming requested but no buffers yet */
  42 };
  43 #define MAX_DMA_BUFS 3
  44
  45 /*
  46  * Different platforms work best with different buffer modes, so we
  47  * let the platform pick.
  48  */
  49 enum mcam_buffer_mode {
  50         B_vmalloc = 0,
  51         B_DMA_contig = 1,
  52         B_DMA_sg = 2
  53 };
  54
  55 /*
  56  * Is a given buffer mode supported by the current kernel configuration?
  57  */
  58 static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
  59 {
  60         switch (mode) {
  61 #ifdef MCAM_MODE_VMALLOC
  62         case B_vmalloc:
  63 #endif
  64 #ifdef MCAM_MODE_DMA_CONTIG
  65         case B_DMA_contig:
  66 #endif
  67 #ifdef MCAM_MODE_DMA_SG
  68         case B_DMA_sg:
  69 #endif
  70                 return 1;
  71         default:
  72                 return 0;
  73         }
  74 }
  75
  76
  77 /*
  78  * A description of one of our devices.
  79  * Locking: controlled by s_mutex.  Certain fields, however, require
  80  *          the dev_lock spinlock; they are marked as such by comments.
  81  *          dev_lock is also required for access to device registers.
  82  */
  83 struct mcam_camera {
  84         /*
  85          * These fields should be set by the platform code prior to
  86          * calling mcam_register().
  87          */
  88         struct i2c_adapter *i2c_adapter;
  89         unsigned char __iomem *regs;
  90         spinlock_t dev_lock;
  91         struct device *dev; /* For messages, dma alloc */
  92         unsigned int chip_id;
  93         short int clock_speed;  /* Sensor clock speed, default 30 */
  94         short int use_smbus;    /* SMBUS or straight I2c? */
  95         enum mcam_buffer_mode buffer_mode;
  96         /*
  97          * Callbacks from the core to the platform code.
  98          */
  99         void (*plat_power_up) (struct mcam_camera *cam);
 100         void (*plat_power_down) (struct mcam_camera *cam);
 101
 102         /*
 103          * Everything below here is private to the mcam core and
 104          * should not be touched by the platform code.
 105          */
 106         struct v4l2_device v4l2_dev;
 107         enum mcam_state state;
 108         unsigned long flags;            /* Buffer status, mainly (dev_lock) */
 109         int users;                      /* How many open FDs */
 110
 111         /*
 112          * Subsystem structures.
 113          */
 114         struct video_device vdev;
 115         struct v4l2_subdev *sensor;
 116         unsigned short sensor_addr;
 117
 118         /* Videobuf2 stuff */
 119         struct vb2_queue vb_queue;
 120         struct list_head buffers;       /* Available frames */
 121
 122         unsigned int nbufs;             /* How many are alloc'd */
 123         int next_buf;                   /* Next to consume (dev_lock) */
 124
 125         /* DMA buffers - vmalloc mode */
 126 #ifdef MCAM_MODE_VMALLOC
 127         unsigned int dma_buf_size;      /* allocated size */
 128         void *dma_bufs[MAX_DMA_BUFS];   /* Internal buffer addresses */
 129         dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
 130         struct tasklet_struct s_tasklet;
 131 #endif
 132         unsigned int sequence;          /* Frame sequence number */
 133         unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */
 134
 135         /* DMA buffers - DMA modes */
 136         struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];
 137         struct vb2_alloc_ctx *vb_alloc_ctx;
 138
 139         /* Mode-specific ops, set at open time */
 140         void (*dma_setup)(struct mcam_camera *cam);
 141         void (*frame_complete)(struct mcam_camera *cam, int frame);
 142
 143         /* Current operating parameters */
 144         u32 sensor_type;                /* Currently ov7670 only */
 145         struct v4l2_pix_format pix_format;
 146         enum v4l2_mbus_pixelcode mbus_code;
 147
 148         /* Locks */
 149         struct mutex s_mutex; /* Access to this structure */
 150 };
 151
 152
 153 /*
 154  * Register I/O functions.  These are here because the platform code
 155  * may legitimately need to mess with the register space.
 156  */
 157 /*
 158  * Device register I/O
 159  */
 160 static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
 161                 unsigned int val)
 162 {
 163         iowrite32(val, cam->regs + reg);
 164 }
 165
 166 static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
 167                 unsigned int reg)
 168 {
 169         return ioread32(cam->regs + reg);
 170 }
 171
 172
 173 static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
 174                 unsigned int val, unsigned int mask)
 175 {
 176         unsigned int v = mcam_reg_read(cam, reg);
 177
 178         v = (v & ~mask) | (val & mask);
 179         mcam_reg_write(cam, reg, v);
 180 }
 181
 182 static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
 183                 unsigned int reg, unsigned int val)
 184 {
 185         mcam_reg_write_mask(cam, reg, 0, val);
 186 }
 187
 188 static inline void mcam_reg_set_bit(struct mcam_camera *cam,
 189                 unsigned int reg, unsigned int val)
 190 {
 191         mcam_reg_write_mask(cam, reg, val, val);
 192 }
 193
 194 /*
 195  * Functions for use by platform code.
 196  */
 197 int mccic_register(struct mcam_camera *cam);
 198 int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
 199 void mccic_shutdown(struct mcam_camera *cam);
 200 #ifdef CONFIG_PM
 201 void mccic_suspend(struct mcam_camera *cam);
 202 int mccic_resume(struct mcam_camera *cam);
 203 #endif
 204
 205 /*
 206  * Register definitions for the m88alp01 camera interface.  Offsets in bytes
 207  * as given in the spec.
 208  */
 209 #define REG_Y0BAR       0x00
 210 #define REG_Y1BAR       0x04
 211 #define REG_Y2BAR       0x08
 212 /* ... */
 213
 214 #define REG_IMGPITCH    0x24    /* Image pitch register */
 215 #define   IMGP_YP_SHFT    2             /* Y pitch params */
 216 #define   IMGP_YP_MASK    0x00003ffc    /* Y pitch field */
 217 #define   IMGP_UVP_SHFT   18            /* UV pitch (planar) */
 218 #define   IMGP_UVP_MASK   0x3ffc0000
 219 #define REG_IRQSTATRAW  0x28    /* RAW IRQ Status */
 220 #define   IRQ_EOF0        0x00000001    /* End of frame 0 */
 221 #define   IRQ_EOF1        0x00000002    /* End of frame 1 */
 222 #define   IRQ_EOF2        0x00000004    /* End of frame 2 */
 223 #define   IRQ_SOF0        0x00000008    /* Start of frame 0 */
 224 #define   IRQ_SOF1        0x00000010    /* Start of frame 1 */
 225 #define   IRQ_SOF2        0x00000020    /* Start of frame 2 */
 226 #define   IRQ_OVERFLOW    0x00000040    /* FIFO overflow */
 227 #define   IRQ_TWSIW       0x00010000    /* TWSI (smbus) write */
 228 #define   IRQ_TWSIR       0x00020000    /* TWSI read */
 229 #define   IRQ_TWSIE       0x00040000    /* TWSI error */
 230 #define   TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
 231 #define   FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
 232 #define   ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
 233 #define REG_IRQMASK     0x2c    /* IRQ mask - same bits as IRQSTAT */
 234 #define REG_IRQSTAT     0x30    /* IRQ status / clear */
 235
 236 #define REG_IMGSIZE     0x34    /* Image size */
 237 #define  IMGSZ_V_MASK     0x1fff0000
 238 #define  IMGSZ_V_SHIFT    16
 239 #define  IMGSZ_H_MASK     0x00003fff
 240 #define REG_IMGOFFSET   0x38    /* IMage offset */
 241
 242 #define REG_CTRL0       0x3c    /* Control 0 */
 243 #define   C0_ENABLE       0x00000001    /* Makes the whole thing go */
 244
 245 /* Mask for all the format bits */
 246 #define   C0_DF_MASK      0x00fffffc    /* Bits 2-23 */
 247
 248 /* RGB ordering */
 249 #define   C0_RGB4_RGBX    0x00000000
 250 #define   C0_RGB4_XRGB    0x00000004
 251 #define   C0_RGB4_BGRX    0x00000008
 252 #define   C0_RGB4_XBGR    0x0000000c
 253 #define   C0_RGB5_RGGB    0x00000000
 254 #define   C0_RGB5_GRBG    0x00000004
 255 #define   C0_RGB5_GBRG    0x00000008
 256 #define   C0_RGB5_BGGR    0x0000000c
 257
 258 /* Spec has two fields for DIN and DOUT, but they must match, so
 259    combine them here. */
 260 #define   C0_DF_YUV       0x00000000    /* Data is YUV      */
 261 #define   C0_DF_RGB       0x000000a0    /* ... RGB                  */
 262 #define   C0_DF_BAYER     0x00000140    /* ... Bayer                */
 263 /* 8-8-8 must be missing from the below - ask */
 264 #define   C0_RGBF_565     0x00000000
 265 #define   C0_RGBF_444     0x00000800
 266 #define   C0_RGB_BGR      0x00001000    /* Blue comes first */
 267 #define   C0_YUV_PLANAR   0x00000000    /* YUV 422 planar format */
 268 #define   C0_YUV_PACKED   0x00008000    /* YUV 422 packed       */
 269 #define   C0_YUV_420PL    0x0000a000    /* YUV 420 planar       */
 270 /* Think that 420 packed must be 111 - ask */
 271 #define   C0_YUVE_YUYV    0x00000000    /* Y1CbY0Cr             */
 272 #define   C0_YUVE_YVYU    0x00010000    /* Y1CrY0Cb             */
 273 #define   C0_YUVE_VYUY    0x00020000    /* CrY1CbY0             */
 274 #define   C0_YUVE_UYVY    0x00030000    /* CbY1CrY0             */
 275 #define   C0_YUVE_XYUV    0x00000000    /* 420: .YUV            */
 276 #define   C0_YUVE_XYVU    0x00010000    /* 420: .YVU            */
 277 #define   C0_YUVE_XUVY    0x00020000    /* 420: .UVY            */
 278 #define   C0_YUVE_XVUY    0x00030000    /* 420: .VUY            */
 279 /* Bayer bits 18,19 if needed */
 280 #define   C0_HPOL_LOW     0x01000000    /* HSYNC polarity active low */
 281 #define   C0_VPOL_LOW     0x02000000    /* VSYNC polarity active low */
 282 #define   C0_VCLK_LOW     0x04000000    /* VCLK on falling edge */
 283 #define   C0_DOWNSCALE    0x08000000    /* Enable downscaler */
 284 #define   C0_SIFM_MASK    0xc0000000    /* SIF mode bits */
 285 #define   C0_SIF_HVSYNC   0x00000000    /* Use H/VSYNC */
 286 #define   CO_SOF_NOSYNC   0x40000000    /* Use inband active signaling */
 287
 288 /* Bits below C1_444ALPHA are not present in Cafe */
 289 #define REG_CTRL1       0x40    /* Control 1 */
 290 #define   C1_CLKGATE      0x00000001    /* Sensor clock gate */
 291 #define   C1_DESC_ENA     0x00000100    /* DMA descriptor enable */
 292 #define   C1_DESC_3WORD   0x00000200    /* Three-word descriptors used */
 293 #define   C1_444ALPHA     0x00f00000    /* Alpha field in RGB444 */
 294 #define   C1_ALPHA_SHFT   20
 295 #define   C1_DMAB32       0x00000000    /* 32-byte DMA burst */
 296 #define   C1_DMAB16       0x02000000    /* 16-byte DMA burst */
 297 #define   C1_DMAB64       0x04000000    /* 64-byte DMA burst */
 298 #define   C1_DMAB_MASK    0x06000000
 299 #define   C1_TWOBUFS      0x08000000    /* Use only two DMA buffers */
 300 #define   C1_PWRDWN       0x10000000    /* Power down */
 301
 302 #define REG_CLKCTRL     0x88    /* Clock control */
 303 #define   CLK_DIV_MASK    0x0000ffff    /* Upper bits RW "reserved" */
 304
 305 /* This appears to be a Cafe-only register */
 306 #define REG_UBAR        0xc4    /* Upper base address register */
 307
 308 /* Armada 610 DMA descriptor registers */
 309 #define REG_DMA_DESC_Y  0x200
 310 #define REG_DMA_DESC_U  0x204
 311 #define REG_DMA_DESC_V  0x208
 312 #define REG_DESC_LEN_Y  0x20c   /* Lengths are in bytes */
 313 #define REG_DESC_LEN_U  0x210
 314 #define REG_DESC_LEN_V  0x214
 315
 316 /*
 317  * Useful stuff that probably belongs somewhere global.
 318  */
 319 #define VGA_WIDTH       640
 320 #define VGA_HEIGHT      480
 321
 322 #endif /* _MCAM_CORE_H */