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[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / media / platform / exynos4-is / fimc-is.c
1 /*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * Younghwan Joo <yhwan.joo@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
14
15 #include <linux/device.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/dma-contiguous.h>
19 #include <linux/errno.h>
20 #include <linux/firmware.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/of_i2c.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31 #include <linux/types.h>
32 #include <linux/videodev2.h>
33 #include <media/v4l2-of.h>
34 #include <media/videobuf2-dma-contig.h>
35
36 #include "media-dev.h"
37 #include "fimc-is.h"
38 #include "fimc-is-command.h"
39 #include "fimc-is-errno.h"
40 #include "fimc-is-i2c.h"
41 #include "fimc-is-param.h"
42 #include "fimc-is-regs.h"
43
44
45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
46 [ISS_CLK_PPMUISPX] = "ppmuispx",
47 [ISS_CLK_PPMUISPMX] = "ppmuispmx",
48 [ISS_CLK_LITE0] = "lite0",
49 [ISS_CLK_LITE1] = "lite1",
50 [ISS_CLK_MPLL] = "mpll",
51 [ISS_CLK_SYSREG] = "sysreg",
52 [ISS_CLK_ISP] = "isp",
53 [ISS_CLK_DRC] = "drc",
54 [ISS_CLK_FD] = "fd",
55 [ISS_CLK_MCUISP] = "mcuisp",
56 [ISS_CLK_UART] = "uart",
57 [ISS_CLK_ISP_DIV0] = "ispdiv0",
58 [ISS_CLK_ISP_DIV1] = "ispdiv1",
59 [ISS_CLK_MCUISP_DIV0] = "mcuispdiv0",
60 [ISS_CLK_MCUISP_DIV1] = "mcuispdiv1",
61 [ISS_CLK_ACLK200] = "aclk200",
62 [ISS_CLK_ACLK200_DIV] = "div_aclk200",
63 [ISS_CLK_ACLK400MCUISP] = "aclk400mcuisp",
64 [ISS_CLK_ACLK400MCUISP_DIV] = "div_aclk400mcuisp",
65 };
66
67 static void fimc_is_put_clocks(struct fimc_is *is)
68 {
69 int i;
70
71 for (i = 0; i < ISS_CLKS_MAX; i++) {
72 if (IS_ERR(is->clocks[i]))
73 continue;
74 clk_put(is->clocks[i]);
75 is->clocks[i] = ERR_PTR(-EINVAL);
76 }
77 }
78
79 static int fimc_is_get_clocks(struct fimc_is *is)
80 {
81 int i, ret;
82
83 for (i = 0; i < ISS_CLKS_MAX; i++)
84 is->clocks[i] = ERR_PTR(-EINVAL);
85
86 for (i = 0; i < ISS_CLKS_MAX; i++) {
87 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
88 if (IS_ERR(is->clocks[i])) {
89 ret = PTR_ERR(is->clocks[i]);
90 goto err;
91 }
92 }
93
94 return 0;
95 err:
96 fimc_is_put_clocks(is);
97 dev_err(&is->pdev->dev, "failed to get clock: %s\n",
98 fimc_is_clocks[i]);
99 return ret;
100 }
101
102 static int fimc_is_setup_clocks(struct fimc_is *is)
103 {
104 int ret;
105
106 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
107 is->clocks[ISS_CLK_ACLK200_DIV]);
108 if (ret < 0)
109 return ret;
110
111 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
112 is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
113 if (ret < 0)
114 return ret;
115
116 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
117 if (ret < 0)
118 return ret;
119
120 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
121 if (ret < 0)
122 return ret;
123
124 ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
125 ATCLK_MCUISP_FREQUENCY);
126 if (ret < 0)
127 return ret;
128
129 return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
130 ATCLK_MCUISP_FREQUENCY);
131 }
132
133 int fimc_is_enable_clocks(struct fimc_is *is)
134 {
135 int i, ret;
136
137 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
138 if (IS_ERR(is->clocks[i]))
139 continue;
140 ret = clk_prepare_enable(is->clocks[i]);
141 if (ret < 0) {
142 dev_err(&is->pdev->dev, "clock %s enable failed\n",
143 fimc_is_clocks[i]);
144 for (--i; i >= 0; i--)
145 clk_disable(is->clocks[i]);
146 return ret;
147 }
148 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
149 }
150 return 0;
151 }
152
153 void fimc_is_disable_clocks(struct fimc_is *is)
154 {
155 int i;
156
157 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
158 if (!IS_ERR(is->clocks[i])) {
159 clk_disable_unprepare(is->clocks[i]);
160 pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
161 }
162 }
163 }
164
165 static int fimc_is_parse_sensor_config(struct fimc_is_sensor *sensor,
166 struct device_node *np)
167 {
168 u32 tmp = 0;
169 int ret;
170
171 np = v4l2_of_get_next_endpoint(np, NULL);
172 if (!np)
173 return -ENXIO;
174 np = v4l2_of_get_remote_port(np);
175 if (!np)
176 return -ENXIO;
177
178 /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
179 ret = of_property_read_u32(np, "reg", &tmp);
180 sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
181
182 return ret;
183 }
184
185 static int fimc_is_register_subdevs(struct fimc_is *is)
186 {
187 struct device_node *adapter, *child;
188 int ret;
189
190 ret = fimc_isp_subdev_create(&is->isp);
191 if (ret < 0)
192 return ret;
193
194 for_each_compatible_node(adapter, NULL, FIMC_IS_I2C_COMPATIBLE) {
195 if (!of_find_device_by_node(adapter)) {
196 of_node_put(adapter);
197 return -EPROBE_DEFER;
198 }
199
200 for_each_available_child_of_node(adapter, child) {
201 struct i2c_client *client;
202 struct v4l2_subdev *sd;
203
204 client = of_find_i2c_device_by_node(child);
205 if (!client)
206 goto e_retry;
207
208 sd = i2c_get_clientdata(client);
209 if (!sd)
210 goto e_retry;
211
212 /* FIXME: Add support for multiple sensors. */
213 if (WARN_ON(is->sensor))
214 continue;
215
216 is->sensor = sd_to_fimc_is_sensor(sd);
217
218 if (fimc_is_parse_sensor_config(is->sensor, child)) {
219 dev_warn(&is->pdev->dev, "DT parse error: %s\n",
220 child->full_name);
221 }
222 pr_debug("%s(): registered subdev: %p\n",
223 __func__, sd->name);
224 }
225 }
226 return 0;
227
228 e_retry:
229 of_node_put(child);
230 return -EPROBE_DEFER;
231 }
232
233 static int fimc_is_unregister_subdevs(struct fimc_is *is)
234 {
235 fimc_isp_subdev_destroy(&is->isp);
236 is->sensor = NULL;
237 return 0;
238 }
239
240 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
241 {
242 const struct firmware *fw;
243 void *buf;
244 int ret;
245
246 ret = request_firmware(&fw, file_name, &is->pdev->dev);
247 if (ret < 0) {
248 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
249 return ret;
250 }
251 buf = is->memory.vaddr + is->setfile.base;
252 memcpy(buf, fw->data, fw->size);
253 fimc_is_mem_barrier();
254 is->setfile.size = fw->size;
255
256 pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
257
258 memcpy(is->fw.setfile_info,
259 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
260 FIMC_IS_SETFILE_INFO_LEN - 1);
261
262 is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
263 is->setfile.state = 1;
264
265 pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
266 is->setfile.base, fw->size);
267
268 release_firmware(fw);
269 return ret;
270 }
271
272 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
273 {
274 unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
275
276 if (on) {
277 /* Disable watchdog */
278 mcuctl_write(0, is, REG_WDT_ISP);
279
280 /* Cortex-A5 start address setting */
281 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
282
283 /* Enable and start Cortex-A5 */
284 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
285 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
286 } else {
287 /* A5 power off */
288 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
289 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
290
291 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
292 if (timeout == 0)
293 return -ETIME;
294 timeout--;
295 udelay(1);
296 }
297 }
298
299 return 0;
300 }
301
302 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
303 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
304 unsigned int state, unsigned int timeout)
305 {
306
307 int ret = wait_event_timeout(is->irq_queue,
308 !state ^ test_bit(bit, &is->state),
309 timeout);
310 if (ret == 0) {
311 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
312 return -ETIME;
313 }
314 return 0;
315 }
316
317 int fimc_is_start_firmware(struct fimc_is *is)
318 {
319 struct device *dev = &is->pdev->dev;
320 int ret;
321
322 if (is->fw.f_w == NULL) {
323 dev_err(dev, "firmware is not loaded\n");
324 return -EINVAL;
325 }
326
327 memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
328 wmb();
329
330 ret = fimc_is_cpu_set_power(is, 1);
331 if (ret < 0)
332 return ret;
333
334 ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
335 msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
336 if (ret < 0)
337 dev_err(dev, "FIMC-IS CPU power on failed\n");
338
339 return ret;
340 }
341
342 /* Allocate working memory for the FIMC-IS CPU. */
343 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
344 {
345 struct device *dev = &is->pdev->dev;
346
347 is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
348 &is->memory.paddr, GFP_KERNEL);
349 if (is->memory.vaddr == NULL)
350 return -ENOMEM;
351
352 is->memory.size = FIMC_IS_CPU_MEM_SIZE;
353 memset(is->memory.vaddr, 0, is->memory.size);
354
355 dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
356
357 if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
358 dev_err(dev, "invalid firmware memory alignment: %#x\n",
359 (u32)is->memory.paddr);
360 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
361 is->memory.paddr);
362 return -EIO;
363 }
364
365 is->is_p_region = (struct is_region *)(is->memory.vaddr +
366 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
367
368 is->is_dma_p_region = is->memory.paddr +
369 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
370
371 is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
372 FIMC_IS_SHARED_REGION_OFFSET);
373 return 0;
374 }
375
376 static void fimc_is_free_cpu_memory(struct fimc_is *is)
377 {
378 struct device *dev = &is->pdev->dev;
379
380 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
381 is->memory.paddr);
382 }
383
384 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
385 {
386 struct fimc_is *is = context;
387 struct device *dev = &is->pdev->dev;
388 void *buf;
389 int ret;
390
391 if (fw == NULL) {
392 dev_err(dev, "firmware request failed\n");
393 return;
394 }
395 mutex_lock(&is->lock);
396
397 if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
398 dev_err(dev, "wrong firmware size: %d\n", fw->size);
399 goto done;
400 }
401
402 is->fw.size = fw->size;
403
404 ret = fimc_is_alloc_cpu_memory(is);
405 if (ret < 0) {
406 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
407 goto done;
408 }
409
410 memcpy(is->memory.vaddr, fw->data, fw->size);
411 wmb();
412
413 /* Read firmware description. */
414 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
415 memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
416 is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
417
418 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
419 memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
420 is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
421
422 is->fw.state = 1;
423
424 dev_info(dev, "loaded firmware: %s, rev. %s\n",
425 is->fw.info, is->fw.version);
426 dev_dbg(dev, "FW size: %d, paddr: %#x\n", fw->size, is->memory.paddr);
427
428 is->is_shared_region->chip_id = 0xe4412;
429 is->is_shared_region->chip_rev_no = 1;
430
431 fimc_is_mem_barrier();
432
433 /*
434 * FIXME: The firmware is not being released for now, as it is
435 * needed around for copying to the IS working memory every
436 * time before the Cortex-A5 is restarted.
437 */
438 if (is->fw.f_w)
439 release_firmware(is->fw.f_w);
440 is->fw.f_w = fw;
441 done:
442 mutex_unlock(&is->lock);
443 }
444
445 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
446 {
447 return request_firmware_nowait(THIS_MODULE,
448 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
449 GFP_KERNEL, is, fimc_is_load_firmware);
450 }
451
452 /* General IS interrupt handler */
453 static void fimc_is_general_irq_handler(struct fimc_is *is)
454 {
455 is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
456
457 switch (is->i2h_cmd.cmd) {
458 case IHC_GET_SENSOR_NUM:
459 fimc_is_hw_get_params(is, 1);
460 fimc_is_hw_wait_intmsr0_intmsd0(is);
461 fimc_is_hw_set_sensor_num(is);
462 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
463 break;
464 case IHC_SET_FACE_MARK:
465 case IHC_FRAME_DONE:
466 fimc_is_hw_get_params(is, 2);
467 break;
468 case IHC_SET_SHOT_MARK:
469 case IHC_AA_DONE:
470 case IH_REPLY_DONE:
471 fimc_is_hw_get_params(is, 3);
472 break;
473 case IH_REPLY_NOT_DONE:
474 fimc_is_hw_get_params(is, 4);
475 break;
476 case IHC_NOT_READY:
477 break;
478 default:
479 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
480 }
481
482 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
483
484 switch (is->i2h_cmd.cmd) {
485 case IHC_GET_SENSOR_NUM:
486 fimc_is_hw_set_intgr0_gd0(is);
487 set_bit(IS_ST_A5_PWR_ON, &is->state);
488 break;
489
490 case IHC_SET_SHOT_MARK:
491 break;
492
493 case IHC_SET_FACE_MARK:
494 is->fd_header.count = is->i2h_cmd.args[0];
495 is->fd_header.index = is->i2h_cmd.args[1];
496 is->fd_header.offset = 0;
497 break;
498
499 case IHC_FRAME_DONE:
500 break;
501
502 case IHC_AA_DONE:
503 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
504 is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
505 break;
506
507 case IH_REPLY_DONE:
508 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
509
510 switch (is->i2h_cmd.args[0]) {
511 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
512 /* Get CAC margin */
513 set_bit(IS_ST_CHANGE_MODE, &is->state);
514 is->isp.cac_margin_x = is->i2h_cmd.args[1];
515 is->isp.cac_margin_y = is->i2h_cmd.args[2];
516 pr_debug("CAC margin (x,y): (%d,%d)\n",
517 is->isp.cac_margin_x, is->isp.cac_margin_y);
518 break;
519
520 case HIC_STREAM_ON:
521 clear_bit(IS_ST_STREAM_OFF, &is->state);
522 set_bit(IS_ST_STREAM_ON, &is->state);
523 break;
524
525 case HIC_STREAM_OFF:
526 clear_bit(IS_ST_STREAM_ON, &is->state);
527 set_bit(IS_ST_STREAM_OFF, &is->state);
528 break;
529
530 case HIC_SET_PARAMETER:
531 is->config[is->config_index].p_region_index1 = 0;
532 is->config[is->config_index].p_region_index2 = 0;
533 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
534 pr_debug("HIC_SET_PARAMETER\n");
535 break;
536
537 case HIC_GET_PARAMETER:
538 break;
539
540 case HIC_SET_TUNE:
541 break;
542
543 case HIC_GET_STATUS:
544 break;
545
546 case HIC_OPEN_SENSOR:
547 set_bit(IS_ST_OPEN_SENSOR, &is->state);
548 pr_debug("data lanes: %d, settle line: %d\n",
549 is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
550 break;
551
552 case HIC_CLOSE_SENSOR:
553 clear_bit(IS_ST_OPEN_SENSOR, &is->state);
554 is->sensor_index = 0;
555 break;
556
557 case HIC_MSG_TEST:
558 pr_debug("config MSG level completed\n");
559 break;
560
561 case HIC_POWER_DOWN:
562 clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
563 break;
564
565 case HIC_GET_SET_FILE_ADDR:
566 is->setfile.base = is->i2h_cmd.args[1];
567 set_bit(IS_ST_SETFILE_LOADED, &is->state);
568 break;
569
570 case HIC_LOAD_SET_FILE:
571 set_bit(IS_ST_SETFILE_LOADED, &is->state);
572 break;
573 }
574 break;
575
576 case IH_REPLY_NOT_DONE:
577 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
578 is->i2h_cmd.args[1],
579 fimc_is_strerr(is->i2h_cmd.args[1]));
580
581 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
582 pr_err("IS_ERROR_TIME_OUT\n");
583
584 switch (is->i2h_cmd.args[1]) {
585 case IS_ERROR_SET_PARAMETER:
586 fimc_is_mem_barrier();
587 }
588
589 switch (is->i2h_cmd.args[0]) {
590 case HIC_SET_PARAMETER:
591 is->config[is->config_index].p_region_index1 = 0;
592 is->config[is->config_index].p_region_index2 = 0;
593 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
594 break;
595 }
596 break;
597
598 case IHC_NOT_READY:
599 pr_err("IS control sequence error: Not Ready\n");
600 break;
601 }
602
603 wake_up(&is->irq_queue);
604 }
605
606 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
607 {
608 struct fimc_is *is = priv;
609 unsigned long flags;
610 u32 status;
611
612 spin_lock_irqsave(&is->slock, flags);
613 status = mcuctl_read(is, MCUCTL_REG_INTSR1);
614
615 if (status & (1UL << FIMC_IS_INT_GENERAL))
616 fimc_is_general_irq_handler(is);
617
618 if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
619 fimc_isp_irq_handler(is);
620
621 spin_unlock_irqrestore(&is->slock, flags);
622 return IRQ_HANDLED;
623 }
624
625 static int fimc_is_hw_open_sensor(struct fimc_is *is,
626 struct fimc_is_sensor *sensor)
627 {
628 struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
629
630 fimc_is_hw_wait_intmsr0_intmsd0(is);
631
632 soe->self_calibration_mode = 1;
633 soe->actuator_type = 0;
634 soe->mipi_lane_num = 0;
635 soe->mclk = 0;
636 soe->mipi_speed = 0;
637 soe->fast_open_sensor = 0;
638 soe->i2c_sclk = 88000000;
639
640 fimc_is_mem_barrier();
641
642 mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
643 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
644 mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
645 mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
646 mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
647
648 fimc_is_hw_set_intgr0_gd0(is);
649
650 return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
651 FIMC_IS_SENSOR_OPEN_TIMEOUT);
652 }
653
654
655 int fimc_is_hw_initialize(struct fimc_is *is)
656 {
657 const int config_ids[] = {
658 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
659 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
660 };
661 struct device *dev = &is->pdev->dev;
662 u32 prev_id;
663 int i, ret;
664
665 /* Sensor initialization. */
666 ret = fimc_is_hw_open_sensor(is, is->sensor);
667 if (ret < 0)
668 return ret;
669
670 /* Get the setfile address. */
671 fimc_is_hw_get_setfile_addr(is);
672
673 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
674 FIMC_IS_CONFIG_TIMEOUT);
675 if (ret < 0) {
676 dev_err(dev, "get setfile address timed out\n");
677 return ret;
678 }
679 pr_debug("setfile.base: %#x\n", is->setfile.base);
680
681 /* Load the setfile. */
682 fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
683 clear_bit(IS_ST_SETFILE_LOADED, &is->state);
684 fimc_is_hw_load_setfile(is);
685 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
686 FIMC_IS_CONFIG_TIMEOUT);
687 if (ret < 0) {
688 dev_err(dev, "loading setfile timed out\n");
689 return ret;
690 }
691
692 pr_debug("setfile: base: %#x, size: %d\n",
693 is->setfile.base, is->setfile.size);
694 pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
695
696 /* Check magic number. */
697 if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
698 FIMC_IS_MAGIC_NUMBER) {
699 dev_err(dev, "magic number error!\n");
700 return -EIO;
701 }
702
703 pr_debug("shared region: %#x, parameter region: %#x\n",
704 is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
705 is->is_dma_p_region);
706
707 is->setfile.sub_index = 0;
708
709 /* Stream off. */
710 fimc_is_hw_stream_off(is);
711 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
712 FIMC_IS_CONFIG_TIMEOUT);
713 if (ret < 0) {
714 dev_err(dev, "stream off timeout\n");
715 return ret;
716 }
717
718 /* Preserve previous mode. */
719 prev_id = is->config_index;
720
721 /* Set initial parameter values. */
722 for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
723 is->config_index = config_ids[i];
724 fimc_is_set_initial_params(is);
725 ret = fimc_is_itf_s_param(is, true);
726 if (ret < 0) {
727 is->config_index = prev_id;
728 return ret;
729 }
730 }
731 is->config_index = prev_id;
732
733 set_bit(IS_ST_INIT_DONE, &is->state);
734 dev_info(dev, "initialization sequence completed (%d)\n",
735 is->config_index);
736 return 0;
737 }
738
739 static int fimc_is_log_show(struct seq_file *s, void *data)
740 {
741 struct fimc_is *is = s->private;
742 const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
743
744 if (is->memory.vaddr == NULL) {
745 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
746 return -EIO;
747 }
748
749 seq_printf(s, "%s\n", buf);
750 return 0;
751 }
752
753 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
754 {
755 return single_open(file, fimc_is_log_show, inode->i_private);
756 }
757
758 static const struct file_operations fimc_is_debugfs_fops = {
759 .open = fimc_is_debugfs_open,
760 .read = seq_read,
761 .llseek = seq_lseek,
762 .release = single_release,
763 };
764
765 static void fimc_is_debugfs_remove(struct fimc_is *is)
766 {
767 debugfs_remove_recursive(is->debugfs_entry);
768 is->debugfs_entry = NULL;
769 }
770
771 static int fimc_is_debugfs_create(struct fimc_is *is)
772 {
773 struct dentry *dentry;
774
775 is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
776
777 dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
778 is, &fimc_is_debugfs_fops);
779 if (!dentry)
780 fimc_is_debugfs_remove(is);
781
782 return is->debugfs_entry == NULL ? -EIO : 0;
783 }
784
785 static int fimc_is_probe(struct platform_device *pdev)
786 {
787 struct device *dev = &pdev->dev;
788 struct fimc_is *is;
789 struct resource res;
790 struct device_node *node;
791 int ret;
792
793 is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
794 if (!is)
795 return -ENOMEM;
796
797 is->pdev = pdev;
798 is->isp.pdev = pdev;
799
800 init_waitqueue_head(&is->irq_queue);
801 spin_lock_init(&is->slock);
802 mutex_init(&is->lock);
803
804 ret = of_address_to_resource(dev->of_node, 0, &res);
805 if (ret < 0)
806 return ret;
807
808 is->regs = devm_ioremap_resource(dev, &res);
809 if (IS_ERR(is->regs))
810 return PTR_ERR(is->regs);
811
812 node = of_get_child_by_name(dev->of_node, "pmu");
813 if (!node)
814 return -ENODEV;
815
816 is->pmu_regs = of_iomap(node, 0);
817 if (!is->pmu_regs)
818 return -ENOMEM;
819
820 is->irq = irq_of_parse_and_map(dev->of_node, 0);
821 if (is->irq < 0) {
822 dev_err(dev, "no irq found\n");
823 return is->irq;
824 }
825
826 ret = fimc_is_get_clocks(is);
827 if (ret < 0)
828 return ret;
829
830 platform_set_drvdata(pdev, is);
831
832 ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
833 if (ret < 0) {
834 dev_err(dev, "irq request failed\n");
835 goto err_clk;
836 }
837 pm_runtime_enable(dev);
838 /*
839 * Enable only the ISP power domain, keep FIMC-IS clocks off until
840 * the whole clock tree is configured. The ISP power domain needs
841 * be active in order to acces any CMU_ISP clock registers.
842 */
843 ret = pm_runtime_get_sync(dev);
844 if (ret < 0)
845 goto err_irq;
846
847 ret = fimc_is_setup_clocks(is);
848 pm_runtime_put_sync(dev);
849
850 if (ret < 0)
851 goto err_irq;
852
853 is->clk_init = true;
854
855 is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
856 if (IS_ERR(is->alloc_ctx)) {
857 ret = PTR_ERR(is->alloc_ctx);
858 goto err_irq;
859 }
860 /*
861 * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
862 * will be created within the subdev's registered() callback.
863 */
864 ret = fimc_is_register_subdevs(is);
865 if (ret < 0)
866 goto err_vb;
867
868 ret = fimc_is_debugfs_create(is);
869 if (ret < 0)
870 goto err_sd;
871
872 ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
873 if (ret < 0)
874 goto err_dfs;
875
876 dev_dbg(dev, "FIMC-IS registered successfully\n");
877 return 0;
878
879 err_dfs:
880 fimc_is_debugfs_remove(is);
881 err_vb:
882 vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
883 err_sd:
884 fimc_is_unregister_subdevs(is);
885 err_irq:
886 free_irq(is->irq, is);
887 err_clk:
888 fimc_is_put_clocks(is);
889 return ret;
890 }
891
892 static int fimc_is_runtime_resume(struct device *dev)
893 {
894 struct fimc_is *is = dev_get_drvdata(dev);
895
896 if (!is->clk_init)
897 return 0;
898
899 return fimc_is_enable_clocks(is);
900 }
901
902 static int fimc_is_runtime_suspend(struct device *dev)
903 {
904 struct fimc_is *is = dev_get_drvdata(dev);
905
906 if (is->clk_init)
907 fimc_is_disable_clocks(is);
908
909 return 0;
910 }
911
912 #ifdef CONFIG_PM_SLEEP
913 static int fimc_is_resume(struct device *dev)
914 {
915 /* TODO: */
916 return 0;
917 }
918
919 static int fimc_is_suspend(struct device *dev)
920 {
921 struct fimc_is *is = dev_get_drvdata(dev);
922
923 /* TODO: */
924 if (test_bit(IS_ST_A5_PWR_ON, &is->state))
925 return -EBUSY;
926
927 return 0;
928 }
929 #endif /* CONFIG_PM_SLEEP */
930
931 static int fimc_is_remove(struct platform_device *pdev)
932 {
933 struct fimc_is *is = platform_get_drvdata(pdev);
934
935 pm_runtime_disable(&pdev->dev);
936 pm_runtime_set_suspended(&pdev->dev);
937 free_irq(is->irq, is);
938 fimc_is_unregister_subdevs(is);
939 vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
940 fimc_is_put_clocks(is);
941 fimc_is_debugfs_remove(is);
942 if (is->fw.f_w)
943 release_firmware(is->fw.f_w);
944 fimc_is_free_cpu_memory(is);
945
946 return 0;
947 }
948
949 static const struct of_device_id fimc_is_of_match[] = {
950 { .compatible = "samsung,exynos4212-fimc-is" },
951 { /* sentinel */ },
952 };
953 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
954
955 static const struct dev_pm_ops fimc_is_pm_ops = {
956 SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
957 SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
958 NULL)
959 };
960
961 static struct platform_driver fimc_is_driver = {
962 .probe = fimc_is_probe,
963 .remove = fimc_is_remove,
964 .driver = {
965 .of_match_table = fimc_is_of_match,
966 .name = FIMC_IS_DRV_NAME,
967 .owner = THIS_MODULE,
968 .pm = &fimc_is_pm_ops,
969 }
970 };
971
972 static int fimc_is_module_init(void)
973 {
974 int ret;
975
976 ret = fimc_is_register_sensor_driver();
977 if (ret < 0)
978 return ret;
979
980 ret = fimc_is_register_i2c_driver();
981 if (ret < 0)
982 goto err_sens;
983
984 ret = platform_driver_register(&fimc_is_driver);
985 if (!ret)
986 return ret;
987
988 fimc_is_unregister_i2c_driver();
989 err_sens:
990 fimc_is_unregister_sensor_driver();
991 return ret;
992 }
993
994 static void fimc_is_module_exit(void)
995 {
996 fimc_is_unregister_sensor_driver();
997 fimc_is_unregister_i2c_driver();
998 platform_driver_unregister(&fimc_is_driver);
999 }
1000
1001 module_init(fimc_is_module_init);
1002 module_exit(fimc_is_module_exit);
1003
1004 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
1005 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
1006 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");