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Merge branch 'broonie/spi-next' of git://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / platform / coda.c
1 /*
2 * Coda multi-standard codec IP
3 *
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/firmware.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/videodev2.h>
25 #include <linux/of.h>
26 #include <linux/platform_data/imx-iram.h>
27
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-ioctl.h>
31 #include <media/v4l2-mem2mem.h>
32 #include <media/videobuf2-core.h>
33 #include <media/videobuf2-dma-contig.h>
34
35 #include "coda.h"
36
37 #define CODA_NAME "coda"
38
39 #define CODA_MAX_INSTANCES 4
40
41 #define CODA_FMO_BUF_SIZE 32
42 #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
43 #define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
44 #define CODA_PARA_BUF_SIZE (10 * 1024)
45 #define CODA_ISRAM_SIZE (2048 * 2)
46 #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
47
48 #define CODA_MAX_FRAMEBUFFERS 2
49
50 #define MAX_W 720
51 #define MAX_H 576
52 #define CODA_MAX_FRAME_SIZE 0x90000
53 #define FMO_SLICE_SAVE_BUF_SIZE (32)
54 #define CODA_DEFAULT_GAMMA 4096
55
56 #define MIN_W 176
57 #define MIN_H 144
58 #define MAX_W 720
59 #define MAX_H 576
60
61 #define S_ALIGN 1 /* multiple of 2 */
62 #define W_ALIGN 1 /* multiple of 2 */
63 #define H_ALIGN 1 /* multiple of 2 */
64
65 #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
66
67 static int coda_debug;
68 module_param(coda_debug, int, 0);
69 MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
70
71 enum {
72 V4L2_M2M_SRC = 0,
73 V4L2_M2M_DST = 1,
74 };
75
76 enum coda_fmt_type {
77 CODA_FMT_ENC,
78 CODA_FMT_RAW,
79 };
80
81 enum coda_inst_type {
82 CODA_INST_ENCODER,
83 CODA_INST_DECODER,
84 };
85
86 enum coda_product {
87 CODA_DX6 = 0xf001,
88 CODA_7541 = 0xf012,
89 };
90
91 struct coda_fmt {
92 char *name;
93 u32 fourcc;
94 enum coda_fmt_type type;
95 };
96
97 struct coda_devtype {
98 char *firmware;
99 enum coda_product product;
100 struct coda_fmt *formats;
101 unsigned int num_formats;
102 size_t workbuf_size;
103 };
104
105 /* Per-queue, driver-specific private data */
106 struct coda_q_data {
107 unsigned int width;
108 unsigned int height;
109 unsigned int sizeimage;
110 struct coda_fmt *fmt;
111 };
112
113 struct coda_aux_buf {
114 void *vaddr;
115 dma_addr_t paddr;
116 u32 size;
117 };
118
119 struct coda_dev {
120 struct v4l2_device v4l2_dev;
121 struct video_device vfd;
122 struct platform_device *plat_dev;
123 const struct coda_devtype *devtype;
124
125 void __iomem *regs_base;
126 struct clk *clk_per;
127 struct clk *clk_ahb;
128
129 struct coda_aux_buf codebuf;
130 struct coda_aux_buf workbuf;
131 long unsigned int iram_paddr;
132
133 spinlock_t irqlock;
134 struct mutex dev_mutex;
135 struct v4l2_m2m_dev *m2m_dev;
136 struct vb2_alloc_ctx *alloc_ctx;
137 struct list_head instances;
138 unsigned long instance_mask;
139 struct delayed_work timeout;
140 struct completion done;
141 };
142
143 struct coda_params {
144 u8 rot_mode;
145 u8 h264_intra_qp;
146 u8 h264_inter_qp;
147 u8 mpeg4_intra_qp;
148 u8 mpeg4_inter_qp;
149 u8 gop_size;
150 int codec_mode;
151 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
152 u32 framerate;
153 u16 bitrate;
154 u32 slice_max_bits;
155 u32 slice_max_mb;
156 };
157
158 struct coda_ctx {
159 struct coda_dev *dev;
160 struct list_head list;
161 int aborting;
162 int rawstreamon;
163 int compstreamon;
164 u32 isequence;
165 struct coda_q_data q_data[2];
166 enum coda_inst_type inst_type;
167 enum v4l2_colorspace colorspace;
168 struct coda_params params;
169 struct v4l2_m2m_ctx *m2m_ctx;
170 struct v4l2_ctrl_handler ctrls;
171 struct v4l2_fh fh;
172 int gopcounter;
173 char vpu_header[3][64];
174 int vpu_header_size[3];
175 struct coda_aux_buf parabuf;
176 struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
177 int num_internal_frames;
178 int idx;
179 };
180
181 static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
182 {
183 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
184 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
185 writel(data, dev->regs_base + reg);
186 }
187
188 static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
189 {
190 u32 data;
191 data = readl(dev->regs_base + reg);
192 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
193 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
194 return data;
195 }
196
197 static inline unsigned long coda_isbusy(struct coda_dev *dev)
198 {
199 return coda_read(dev, CODA_REG_BIT_BUSY);
200 }
201
202 static inline int coda_is_initialized(struct coda_dev *dev)
203 {
204 return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
205 }
206
207 static int coda_wait_timeout(struct coda_dev *dev)
208 {
209 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
210
211 while (coda_isbusy(dev)) {
212 if (time_after(jiffies, timeout))
213 return -ETIMEDOUT;
214 }
215 return 0;
216 }
217
218 static void coda_command_async(struct coda_ctx *ctx, int cmd)
219 {
220 struct coda_dev *dev = ctx->dev;
221 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
222
223 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
224 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
225 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
226 }
227
228 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
229 {
230 struct coda_dev *dev = ctx->dev;
231
232 coda_command_async(ctx, cmd);
233 return coda_wait_timeout(dev);
234 }
235
236 static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
237 enum v4l2_buf_type type)
238 {
239 switch (type) {
240 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
241 return &(ctx->q_data[V4L2_M2M_SRC]);
242 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
243 return &(ctx->q_data[V4L2_M2M_DST]);
244 default:
245 BUG();
246 }
247 return NULL;
248 }
249
250 /*
251 * Add one array of supported formats for each version of Coda:
252 * i.MX27 -> codadx6
253 * i.MX51 -> coda7
254 * i.MX6 -> coda960
255 */
256 static struct coda_fmt codadx6_formats[] = {
257 {
258 .name = "YUV 4:2:0 Planar",
259 .fourcc = V4L2_PIX_FMT_YUV420,
260 .type = CODA_FMT_RAW,
261 },
262 {
263 .name = "H264 Encoded Stream",
264 .fourcc = V4L2_PIX_FMT_H264,
265 .type = CODA_FMT_ENC,
266 },
267 {
268 .name = "MPEG4 Encoded Stream",
269 .fourcc = V4L2_PIX_FMT_MPEG4,
270 .type = CODA_FMT_ENC,
271 },
272 };
273
274 static struct coda_fmt coda7_formats[] = {
275 {
276 .name = "YUV 4:2:0 Planar",
277 .fourcc = V4L2_PIX_FMT_YUV420,
278 .type = CODA_FMT_RAW,
279 },
280 {
281 .name = "H264 Encoded Stream",
282 .fourcc = V4L2_PIX_FMT_H264,
283 .type = CODA_FMT_ENC,
284 },
285 {
286 .name = "MPEG4 Encoded Stream",
287 .fourcc = V4L2_PIX_FMT_MPEG4,
288 .type = CODA_FMT_ENC,
289 },
290 };
291
292 static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
293 {
294 struct coda_fmt *formats = dev->devtype->formats;
295 int num_formats = dev->devtype->num_formats;
296 unsigned int k;
297
298 for (k = 0; k < num_formats; k++) {
299 if (formats[k].fourcc == f->fmt.pix.pixelformat)
300 break;
301 }
302
303 if (k == num_formats)
304 return NULL;
305
306 return &formats[k];
307 }
308
309 /*
310 * V4L2 ioctl() operations.
311 */
312 static int vidioc_querycap(struct file *file, void *priv,
313 struct v4l2_capability *cap)
314 {
315 strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
316 strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
317 strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
318 /*
319 * This is only a mem-to-mem video device. The capture and output
320 * device capability flags are left only for backward compatibility
321 * and are scheduled for removal.
322 */
323 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
324 V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
325 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
326
327 return 0;
328 }
329
330 static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
331 enum coda_fmt_type type)
332 {
333 struct coda_ctx *ctx = fh_to_ctx(priv);
334 struct coda_dev *dev = ctx->dev;
335 struct coda_fmt *formats = dev->devtype->formats;
336 struct coda_fmt *fmt;
337 int num_formats = dev->devtype->num_formats;
338 int i, num = 0;
339
340 for (i = 0; i < num_formats; i++) {
341 if (formats[i].type == type) {
342 if (num == f->index)
343 break;
344 ++num;
345 }
346 }
347
348 if (i < num_formats) {
349 fmt = &formats[i];
350 strlcpy(f->description, fmt->name, sizeof(f->description));
351 f->pixelformat = fmt->fourcc;
352 return 0;
353 }
354
355 /* Format not found */
356 return -EINVAL;
357 }
358
359 static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
360 struct v4l2_fmtdesc *f)
361 {
362 return enum_fmt(priv, f, CODA_FMT_ENC);
363 }
364
365 static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
366 struct v4l2_fmtdesc *f)
367 {
368 return enum_fmt(priv, f, CODA_FMT_RAW);
369 }
370
371 static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
372 {
373 struct vb2_queue *vq;
374 struct coda_q_data *q_data;
375 struct coda_ctx *ctx = fh_to_ctx(priv);
376
377 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
378 if (!vq)
379 return -EINVAL;
380
381 q_data = get_q_data(ctx, f->type);
382
383 f->fmt.pix.field = V4L2_FIELD_NONE;
384 f->fmt.pix.pixelformat = q_data->fmt->fourcc;
385 f->fmt.pix.width = q_data->width;
386 f->fmt.pix.height = q_data->height;
387 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
388 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
389 else /* encoded formats h.264/mpeg4 */
390 f->fmt.pix.bytesperline = 0;
391
392 f->fmt.pix.sizeimage = q_data->sizeimage;
393 f->fmt.pix.colorspace = ctx->colorspace;
394
395 return 0;
396 }
397
398 static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
399 {
400 enum v4l2_field field;
401
402 field = f->fmt.pix.field;
403 if (field == V4L2_FIELD_ANY)
404 field = V4L2_FIELD_NONE;
405 else if (V4L2_FIELD_NONE != field)
406 return -EINVAL;
407
408 /* V4L2 specification suggests the driver corrects the format struct
409 * if any of the dimensions is unsupported */
410 f->fmt.pix.field = field;
411
412 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
413 v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
414 W_ALIGN, &f->fmt.pix.height,
415 MIN_H, MAX_H, H_ALIGN, S_ALIGN);
416 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
417 f->fmt.pix.sizeimage = f->fmt.pix.width *
418 f->fmt.pix.height * 3 / 2;
419 } else { /*encoded formats h.264/mpeg4 */
420 f->fmt.pix.bytesperline = 0;
421 f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
422 }
423
424 return 0;
425 }
426
427 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
428 struct v4l2_format *f)
429 {
430 int ret;
431 struct coda_fmt *fmt;
432 struct coda_ctx *ctx = fh_to_ctx(priv);
433
434 fmt = find_format(ctx->dev, f);
435 /*
436 * Since decoding support is not implemented yet do not allow
437 * CODA_FMT_RAW formats in the capture interface.
438 */
439 if (!fmt || !(fmt->type == CODA_FMT_ENC))
440 f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
441
442 f->fmt.pix.colorspace = ctx->colorspace;
443
444 ret = vidioc_try_fmt(ctx->dev, f);
445 if (ret < 0)
446 return ret;
447
448 return 0;
449 }
450
451 static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
452 struct v4l2_format *f)
453 {
454 struct coda_ctx *ctx = fh_to_ctx(priv);
455 struct coda_fmt *fmt;
456 int ret;
457
458 fmt = find_format(ctx->dev, f);
459 /*
460 * Since decoding support is not implemented yet do not allow
461 * CODA_FMT formats in the capture interface.
462 */
463 if (!fmt || !(fmt->type == CODA_FMT_RAW))
464 f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
465
466 if (!f->fmt.pix.colorspace)
467 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
468
469 ret = vidioc_try_fmt(ctx->dev, f);
470 if (ret < 0)
471 return ret;
472
473 return 0;
474 }
475
476 static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
477 {
478 struct coda_q_data *q_data;
479 struct vb2_queue *vq;
480 int ret;
481
482 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
483 if (!vq)
484 return -EINVAL;
485
486 q_data = get_q_data(ctx, f->type);
487 if (!q_data)
488 return -EINVAL;
489
490 if (vb2_is_busy(vq)) {
491 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
492 return -EBUSY;
493 }
494
495 ret = vidioc_try_fmt(ctx->dev, f);
496 if (ret)
497 return ret;
498
499 q_data->fmt = find_format(ctx->dev, f);
500 q_data->width = f->fmt.pix.width;
501 q_data->height = f->fmt.pix.height;
502 q_data->sizeimage = f->fmt.pix.sizeimage;
503
504 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
505 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
506 f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
507
508 return 0;
509 }
510
511 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
512 struct v4l2_format *f)
513 {
514 int ret;
515
516 ret = vidioc_try_fmt_vid_cap(file, priv, f);
517 if (ret)
518 return ret;
519
520 return vidioc_s_fmt(fh_to_ctx(priv), f);
521 }
522
523 static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
524 struct v4l2_format *f)
525 {
526 struct coda_ctx *ctx = fh_to_ctx(priv);
527 int ret;
528
529 ret = vidioc_try_fmt_vid_out(file, priv, f);
530 if (ret)
531 return ret;
532
533 ret = vidioc_s_fmt(ctx, f);
534 if (ret)
535 ctx->colorspace = f->fmt.pix.colorspace;
536
537 return ret;
538 }
539
540 static int vidioc_reqbufs(struct file *file, void *priv,
541 struct v4l2_requestbuffers *reqbufs)
542 {
543 struct coda_ctx *ctx = fh_to_ctx(priv);
544
545 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
546 }
547
548 static int vidioc_querybuf(struct file *file, void *priv,
549 struct v4l2_buffer *buf)
550 {
551 struct coda_ctx *ctx = fh_to_ctx(priv);
552
553 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
554 }
555
556 static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
557 {
558 struct coda_ctx *ctx = fh_to_ctx(priv);
559
560 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
561 }
562
563 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
564 {
565 struct coda_ctx *ctx = fh_to_ctx(priv);
566
567 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
568 }
569
570 static int vidioc_streamon(struct file *file, void *priv,
571 enum v4l2_buf_type type)
572 {
573 struct coda_ctx *ctx = fh_to_ctx(priv);
574
575 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
576 }
577
578 static int vidioc_streamoff(struct file *file, void *priv,
579 enum v4l2_buf_type type)
580 {
581 struct coda_ctx *ctx = fh_to_ctx(priv);
582
583 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
584 }
585
586 static const struct v4l2_ioctl_ops coda_ioctl_ops = {
587 .vidioc_querycap = vidioc_querycap,
588
589 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
590 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
591 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
592 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
593
594 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
595 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
596 .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
597 .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
598
599 .vidioc_reqbufs = vidioc_reqbufs,
600 .vidioc_querybuf = vidioc_querybuf,
601
602 .vidioc_qbuf = vidioc_qbuf,
603 .vidioc_dqbuf = vidioc_dqbuf,
604
605 .vidioc_streamon = vidioc_streamon,
606 .vidioc_streamoff = vidioc_streamoff,
607 };
608
609 /*
610 * Mem-to-mem operations.
611 */
612 static void coda_device_run(void *m2m_priv)
613 {
614 struct coda_ctx *ctx = m2m_priv;
615 struct coda_q_data *q_data_src, *q_data_dst;
616 struct vb2_buffer *src_buf, *dst_buf;
617 struct coda_dev *dev = ctx->dev;
618 int force_ipicture;
619 int quant_param = 0;
620 u32 picture_y, picture_cb, picture_cr;
621 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
622 u32 dst_fourcc;
623
624 src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
625 dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
626 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
627 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
628 dst_fourcc = q_data_dst->fmt->fourcc;
629
630 src_buf->v4l2_buf.sequence = ctx->isequence;
631 dst_buf->v4l2_buf.sequence = ctx->isequence;
632 ctx->isequence++;
633
634 /*
635 * Workaround coda firmware BUG that only marks the first
636 * frame as IDR. This is a problem for some decoders that can't
637 * recover when a frame is lost.
638 */
639 if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
640 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
641 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
642 } else {
643 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
644 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
645 }
646
647 /*
648 * Copy headers at the beginning of the first frame for H.264 only.
649 * In MPEG4 they are already copied by the coda.
650 */
651 if (src_buf->v4l2_buf.sequence == 0) {
652 pic_stream_buffer_addr =
653 vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
654 ctx->vpu_header_size[0] +
655 ctx->vpu_header_size[1] +
656 ctx->vpu_header_size[2];
657 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
658 ctx->vpu_header_size[0] -
659 ctx->vpu_header_size[1] -
660 ctx->vpu_header_size[2];
661 memcpy(vb2_plane_vaddr(dst_buf, 0),
662 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
663 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
664 &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
665 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
666 ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
667 ctx->vpu_header_size[2]);
668 } else {
669 pic_stream_buffer_addr =
670 vb2_dma_contig_plane_dma_addr(dst_buf, 0);
671 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
672 }
673
674 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
675 force_ipicture = 1;
676 switch (dst_fourcc) {
677 case V4L2_PIX_FMT_H264:
678 quant_param = ctx->params.h264_intra_qp;
679 break;
680 case V4L2_PIX_FMT_MPEG4:
681 quant_param = ctx->params.mpeg4_intra_qp;
682 break;
683 default:
684 v4l2_warn(&ctx->dev->v4l2_dev,
685 "cannot set intra qp, fmt not supported\n");
686 break;
687 }
688 } else {
689 force_ipicture = 0;
690 switch (dst_fourcc) {
691 case V4L2_PIX_FMT_H264:
692 quant_param = ctx->params.h264_inter_qp;
693 break;
694 case V4L2_PIX_FMT_MPEG4:
695 quant_param = ctx->params.mpeg4_inter_qp;
696 break;
697 default:
698 v4l2_warn(&ctx->dev->v4l2_dev,
699 "cannot set inter qp, fmt not supported\n");
700 break;
701 }
702 }
703
704 /* submit */
705 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
706 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
707
708
709 picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
710 picture_cb = picture_y + q_data_src->width * q_data_src->height;
711 picture_cr = picture_cb + q_data_src->width / 2 *
712 q_data_src->height / 2;
713
714 coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
715 coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
716 coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
717 coda_write(dev, force_ipicture << 1 & 0x2,
718 CODA_CMD_ENC_PIC_OPTION);
719
720 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
721 coda_write(dev, pic_stream_buffer_size / 1024,
722 CODA_CMD_ENC_PIC_BB_SIZE);
723
724 if (dev->devtype->product == CODA_7541) {
725 coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
726 CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
727 CODA7_REG_BIT_AXI_SRAM_USE);
728 }
729
730 /* 1 second timeout in case CODA locks up */
731 schedule_delayed_work(&dev->timeout, HZ);
732
733 INIT_COMPLETION(dev->done);
734 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
735 }
736
737 static int coda_job_ready(void *m2m_priv)
738 {
739 struct coda_ctx *ctx = m2m_priv;
740
741 /*
742 * For both 'P' and 'key' frame cases 1 picture
743 * and 1 frame are needed.
744 */
745 if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
746 !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
747 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
748 "not ready: not enough video buffers.\n");
749 return 0;
750 }
751
752 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
753 "job ready\n");
754 return 1;
755 }
756
757 static void coda_job_abort(void *priv)
758 {
759 struct coda_ctx *ctx = priv;
760 struct coda_dev *dev = ctx->dev;
761
762 ctx->aborting = 1;
763
764 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
765 "Aborting task\n");
766
767 v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
768 }
769
770 static void coda_lock(void *m2m_priv)
771 {
772 struct coda_ctx *ctx = m2m_priv;
773 struct coda_dev *pcdev = ctx->dev;
774 mutex_lock(&pcdev->dev_mutex);
775 }
776
777 static void coda_unlock(void *m2m_priv)
778 {
779 struct coda_ctx *ctx = m2m_priv;
780 struct coda_dev *pcdev = ctx->dev;
781 mutex_unlock(&pcdev->dev_mutex);
782 }
783
784 static struct v4l2_m2m_ops coda_m2m_ops = {
785 .device_run = coda_device_run,
786 .job_ready = coda_job_ready,
787 .job_abort = coda_job_abort,
788 .lock = coda_lock,
789 .unlock = coda_unlock,
790 };
791
792 static void set_default_params(struct coda_ctx *ctx)
793 {
794 struct coda_dev *dev = ctx->dev;
795
796 ctx->params.codec_mode = CODA_MODE_INVALID;
797 ctx->colorspace = V4L2_COLORSPACE_REC709;
798 ctx->params.framerate = 30;
799 ctx->aborting = 0;
800
801 /* Default formats for output and input queues */
802 ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
803 ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
804 ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
805 ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
806 ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
807 ctx->q_data[V4L2_M2M_DST].width = MAX_W;
808 ctx->q_data[V4L2_M2M_DST].height = MAX_H;
809 ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
810 }
811
812 /*
813 * Queue operations
814 */
815 static int coda_queue_setup(struct vb2_queue *vq,
816 const struct v4l2_format *fmt,
817 unsigned int *nbuffers, unsigned int *nplanes,
818 unsigned int sizes[], void *alloc_ctxs[])
819 {
820 struct coda_ctx *ctx = vb2_get_drv_priv(vq);
821 struct coda_q_data *q_data;
822 unsigned int size;
823
824 q_data = get_q_data(ctx, vq->type);
825 size = q_data->sizeimage;
826
827 *nplanes = 1;
828 sizes[0] = size;
829
830 alloc_ctxs[0] = ctx->dev->alloc_ctx;
831
832 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
833 "get %d buffer(s) of size %d each.\n", *nbuffers, size);
834
835 return 0;
836 }
837
838 static int coda_buf_prepare(struct vb2_buffer *vb)
839 {
840 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
841 struct coda_q_data *q_data;
842
843 q_data = get_q_data(ctx, vb->vb2_queue->type);
844
845 if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
846 v4l2_warn(&ctx->dev->v4l2_dev,
847 "%s data will not fit into plane (%lu < %lu)\n",
848 __func__, vb2_plane_size(vb, 0),
849 (long)q_data->sizeimage);
850 return -EINVAL;
851 }
852
853 vb2_set_plane_payload(vb, 0, q_data->sizeimage);
854
855 return 0;
856 }
857
858 static void coda_buf_queue(struct vb2_buffer *vb)
859 {
860 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
861 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
862 }
863
864 static void coda_wait_prepare(struct vb2_queue *q)
865 {
866 struct coda_ctx *ctx = vb2_get_drv_priv(q);
867 coda_unlock(ctx);
868 }
869
870 static void coda_wait_finish(struct vb2_queue *q)
871 {
872 struct coda_ctx *ctx = vb2_get_drv_priv(q);
873 coda_lock(ctx);
874 }
875
876 static void coda_free_framebuffers(struct coda_ctx *ctx)
877 {
878 int i;
879
880 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++) {
881 if (ctx->internal_frames[i].vaddr) {
882 dma_free_coherent(&ctx->dev->plat_dev->dev,
883 ctx->internal_frames[i].size,
884 ctx->internal_frames[i].vaddr,
885 ctx->internal_frames[i].paddr);
886 ctx->internal_frames[i].vaddr = NULL;
887 }
888 }
889 }
890
891 static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
892 {
893 struct coda_dev *dev = ctx->dev;
894
895 int height = q_data->height;
896 int width = q_data->width;
897 u32 *p;
898 int i;
899
900 /* Allocate frame buffers */
901 ctx->num_internal_frames = CODA_MAX_FRAMEBUFFERS;
902 for (i = 0; i < ctx->num_internal_frames; i++) {
903 ctx->internal_frames[i].size = q_data->sizeimage;
904 if (fourcc == V4L2_PIX_FMT_H264 && dev->devtype->product != CODA_DX6)
905 ctx->internal_frames[i].size += width / 2 * height / 2;
906 ctx->internal_frames[i].vaddr = dma_alloc_coherent(
907 &dev->plat_dev->dev, ctx->internal_frames[i].size,
908 &ctx->internal_frames[i].paddr, GFP_KERNEL);
909 if (!ctx->internal_frames[i].vaddr) {
910 coda_free_framebuffers(ctx);
911 return -ENOMEM;
912 }
913 }
914
915 /* Register frame buffers in the parameter buffer */
916 p = ctx->parabuf.vaddr;
917
918 if (dev->devtype->product == CODA_DX6) {
919 for (i = 0; i < ctx->num_internal_frames; i++) {
920 p[i * 3] = ctx->internal_frames[i].paddr; /* Y */
921 p[i * 3 + 1] = p[i * 3] + width * height; /* Cb */
922 p[i * 3 + 2] = p[i * 3 + 1] + width / 2 * height / 2; /* Cr */
923 }
924 } else {
925 for (i = 0; i < ctx->num_internal_frames; i += 2) {
926 p[i * 3 + 1] = ctx->internal_frames[i].paddr; /* Y */
927 p[i * 3] = p[i * 3 + 1] + width * height; /* Cb */
928 p[i * 3 + 3] = p[i * 3] + (width / 2) * (height / 2); /* Cr */
929
930 if (fourcc == V4L2_PIX_FMT_H264)
931 p[96 + i + 1] = p[i * 3 + 3] + (width / 2) * (height / 2);
932
933 if (i + 1 < ctx->num_internal_frames) {
934 p[i * 3 + 2] = ctx->internal_frames[i+1].paddr; /* Y */
935 p[i * 3 + 5] = p[i * 3 + 2] + width * height ; /* Cb */
936 p[i * 3 + 4] = p[i * 3 + 5] + (width / 2) * (height / 2); /* Cr */
937
938 if (fourcc == V4L2_PIX_FMT_H264)
939 p[96 + i] = p[i * 3 + 4] + (width / 2) * (height / 2);
940 }
941 }
942 }
943
944 return 0;
945 }
946
947 static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
948 {
949 struct coda_ctx *ctx = vb2_get_drv_priv(q);
950 struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
951 u32 bitstream_buf, bitstream_size;
952 struct coda_dev *dev = ctx->dev;
953 struct coda_q_data *q_data_src, *q_data_dst;
954 struct vb2_buffer *buf;
955 u32 dst_fourcc;
956 u32 value;
957 int ret;
958
959 if (count < 1)
960 return -EINVAL;
961
962 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
963 ctx->rawstreamon = 1;
964 else
965 ctx->compstreamon = 1;
966
967 /* Don't start the coda unless both queues are on */
968 if (!(ctx->rawstreamon & ctx->compstreamon))
969 return 0;
970
971 if (coda_isbusy(dev))
972 if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0)
973 return -EBUSY;
974
975 ctx->gopcounter = ctx->params.gop_size - 1;
976
977 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
978 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
979 bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
980 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
981 bitstream_size = q_data_dst->sizeimage;
982 dst_fourcc = q_data_dst->fmt->fourcc;
983
984 /* Find out whether coda must encode or decode */
985 if (q_data_src->fmt->type == CODA_FMT_RAW &&
986 q_data_dst->fmt->type == CODA_FMT_ENC) {
987 ctx->inst_type = CODA_INST_ENCODER;
988 } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
989 q_data_dst->fmt->type == CODA_FMT_RAW) {
990 ctx->inst_type = CODA_INST_DECODER;
991 v4l2_err(v4l2_dev, "decoding not supported.\n");
992 return -EINVAL;
993 } else {
994 v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
995 return -EINVAL;
996 }
997
998 if (!coda_is_initialized(dev)) {
999 v4l2_err(v4l2_dev, "coda is not initialized.\n");
1000 return -EFAULT;
1001 }
1002 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1003 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
1004 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
1005 switch (dev->devtype->product) {
1006 case CODA_DX6:
1007 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
1008 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
1009 break;
1010 default:
1011 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
1012 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
1013 }
1014
1015 if (dev->devtype->product == CODA_DX6) {
1016 /* Configure the coda */
1017 coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
1018 }
1019
1020 /* Could set rotation here if needed */
1021 switch (dev->devtype->product) {
1022 case CODA_DX6:
1023 value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
1024 break;
1025 default:
1026 value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
1027 }
1028 value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
1029 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
1030 coda_write(dev, ctx->params.framerate,
1031 CODA_CMD_ENC_SEQ_SRC_F_RATE);
1032
1033 switch (dst_fourcc) {
1034 case V4L2_PIX_FMT_MPEG4:
1035 if (dev->devtype->product == CODA_DX6)
1036 ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
1037 else
1038 ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
1039
1040 coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
1041 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
1042 break;
1043 case V4L2_PIX_FMT_H264:
1044 if (dev->devtype->product == CODA_DX6)
1045 ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
1046 else
1047 ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
1048
1049 coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
1050 coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
1051 break;
1052 default:
1053 v4l2_err(v4l2_dev,
1054 "dst format (0x%08x) invalid.\n", dst_fourcc);
1055 return -EINVAL;
1056 }
1057
1058 switch (ctx->params.slice_mode) {
1059 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
1060 value = 0;
1061 break;
1062 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
1063 value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
1064 value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
1065 value |= 1 & CODA_SLICING_MODE_MASK;
1066 break;
1067 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
1068 value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
1069 value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
1070 value |= 1 & CODA_SLICING_MODE_MASK;
1071 break;
1072 }
1073 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
1074 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
1075 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
1076
1077 if (ctx->params.bitrate) {
1078 /* Rate control enabled */
1079 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
1080 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
1081 } else {
1082 value = 0;
1083 }
1084 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
1085
1086 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
1087 coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
1088
1089 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
1090 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
1091
1092 /* set default gamma */
1093 value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
1094 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
1095
1096 value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
1097 value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
1098 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1099
1100 if (dst_fourcc == V4L2_PIX_FMT_H264) {
1101 value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
1102 value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
1103 value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
1104 if (dev->devtype->product == CODA_DX6) {
1105 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1106 } else {
1107 coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1108 coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1109 }
1110 }
1111
1112 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1113 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1114 return -ETIMEDOUT;
1115 }
1116
1117 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
1118 return -EFAULT;
1119
1120 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1121 if (ret < 0)
1122 return ret;
1123
1124 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1125 coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
1126 if (dev->devtype->product != CODA_DX6) {
1127 coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1128 coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1129 coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1130 coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1131 coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1132 coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1133 }
1134 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1135 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1136 return -ETIMEDOUT;
1137 }
1138
1139 /* Save stream headers */
1140 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
1141 switch (dst_fourcc) {
1142 case V4L2_PIX_FMT_H264:
1143 /*
1144 * Get SPS in the first frame and copy it to an
1145 * intermediate buffer.
1146 */
1147 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1148 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1149 coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
1150 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1151 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1152 return -ETIMEDOUT;
1153 }
1154 ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1155 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1156 memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
1157 ctx->vpu_header_size[0]);
1158
1159 /*
1160 * Get PPS in the first frame and copy it to an
1161 * intermediate buffer.
1162 */
1163 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1164 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1165 coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
1166 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1167 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1168 return -ETIMEDOUT;
1169 }
1170 ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1171 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1172 memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
1173 ctx->vpu_header_size[1]);
1174 ctx->vpu_header_size[2] = 0;
1175 break;
1176 case V4L2_PIX_FMT_MPEG4:
1177 /*
1178 * Get VOS in the first frame and copy it to an
1179 * intermediate buffer
1180 */
1181 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1182 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1183 coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
1184 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1185 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1186 return -ETIMEDOUT;
1187 }
1188 ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1189 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1190 memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
1191 ctx->vpu_header_size[0]);
1192
1193 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1194 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1195 coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
1196 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1197 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
1198 return -ETIMEDOUT;
1199 }
1200 ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1201 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1202 memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
1203 ctx->vpu_header_size[1]);
1204
1205 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1206 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1207 coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
1208 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1209 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
1210 return -ETIMEDOUT;
1211 }
1212 ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1213 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1214 memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
1215 ctx->vpu_header_size[2]);
1216 break;
1217 default:
1218 /* No more formats need to save headers at the moment */
1219 break;
1220 }
1221
1222 return 0;
1223 }
1224
1225 static int coda_stop_streaming(struct vb2_queue *q)
1226 {
1227 struct coda_ctx *ctx = vb2_get_drv_priv(q);
1228 struct coda_dev *dev = ctx->dev;
1229
1230 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1231 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1232 "%s: output\n", __func__);
1233 ctx->rawstreamon = 0;
1234 } else {
1235 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1236 "%s: capture\n", __func__);
1237 ctx->compstreamon = 0;
1238 }
1239
1240 /* Don't stop the coda unless both queues are off */
1241 if (ctx->rawstreamon || ctx->compstreamon)
1242 return 0;
1243
1244 if (coda_isbusy(dev)) {
1245 if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0) {
1246 v4l2_warn(&dev->v4l2_dev,
1247 "%s: timeout, sending SEQ_END anyway\n", __func__);
1248 }
1249 }
1250
1251 cancel_delayed_work(&dev->timeout);
1252
1253 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1254 "%s: sent command 'SEQ_END' to coda\n", __func__);
1255 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1256 v4l2_err(&dev->v4l2_dev,
1257 "CODA_COMMAND_SEQ_END failed\n");
1258 return -ETIMEDOUT;
1259 }
1260
1261 coda_free_framebuffers(ctx);
1262
1263 return 0;
1264 }
1265
1266 static struct vb2_ops coda_qops = {
1267 .queue_setup = coda_queue_setup,
1268 .buf_prepare = coda_buf_prepare,
1269 .buf_queue = coda_buf_queue,
1270 .wait_prepare = coda_wait_prepare,
1271 .wait_finish = coda_wait_finish,
1272 .start_streaming = coda_start_streaming,
1273 .stop_streaming = coda_stop_streaming,
1274 };
1275
1276 static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
1277 {
1278 struct coda_ctx *ctx =
1279 container_of(ctrl->handler, struct coda_ctx, ctrls);
1280
1281 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1282 "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
1283
1284 switch (ctrl->id) {
1285 case V4L2_CID_HFLIP:
1286 if (ctrl->val)
1287 ctx->params.rot_mode |= CODA_MIR_HOR;
1288 else
1289 ctx->params.rot_mode &= ~CODA_MIR_HOR;
1290 break;
1291 case V4L2_CID_VFLIP:
1292 if (ctrl->val)
1293 ctx->params.rot_mode |= CODA_MIR_VER;
1294 else
1295 ctx->params.rot_mode &= ~CODA_MIR_VER;
1296 break;
1297 case V4L2_CID_MPEG_VIDEO_BITRATE:
1298 ctx->params.bitrate = ctrl->val / 1000;
1299 break;
1300 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
1301 ctx->params.gop_size = ctrl->val;
1302 break;
1303 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
1304 ctx->params.h264_intra_qp = ctrl->val;
1305 break;
1306 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
1307 ctx->params.h264_inter_qp = ctrl->val;
1308 break;
1309 case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
1310 ctx->params.mpeg4_intra_qp = ctrl->val;
1311 break;
1312 case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
1313 ctx->params.mpeg4_inter_qp = ctrl->val;
1314 break;
1315 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
1316 ctx->params.slice_mode = ctrl->val;
1317 break;
1318 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
1319 ctx->params.slice_max_mb = ctrl->val;
1320 break;
1321 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
1322 ctx->params.slice_max_bits = ctrl->val * 8;
1323 break;
1324 case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
1325 break;
1326 default:
1327 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1328 "Invalid control, id=%d, val=%d\n",
1329 ctrl->id, ctrl->val);
1330 return -EINVAL;
1331 }
1332
1333 return 0;
1334 }
1335
1336 static struct v4l2_ctrl_ops coda_ctrl_ops = {
1337 .s_ctrl = coda_s_ctrl,
1338 };
1339
1340 static int coda_ctrls_setup(struct coda_ctx *ctx)
1341 {
1342 v4l2_ctrl_handler_init(&ctx->ctrls, 9);
1343
1344 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1345 V4L2_CID_HFLIP, 0, 1, 1, 0);
1346 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1347 V4L2_CID_VFLIP, 0, 1, 1, 0);
1348 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1349 V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
1350 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1351 V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
1352 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1353 V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
1354 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1355 V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
1356 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1357 V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
1358 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1359 V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
1360 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1361 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
1362 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
1363 V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
1364 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1365 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
1366 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1367 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
1368 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1369 V4L2_CID_MPEG_VIDEO_HEADER_MODE,
1370 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
1371 (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
1372 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
1373
1374 if (ctx->ctrls.error) {
1375 v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
1376 ctx->ctrls.error);
1377 return -EINVAL;
1378 }
1379
1380 return v4l2_ctrl_handler_setup(&ctx->ctrls);
1381 }
1382
1383 static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
1384 struct vb2_queue *dst_vq)
1385 {
1386 struct coda_ctx *ctx = priv;
1387 int ret;
1388
1389 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1390 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1391 src_vq->drv_priv = ctx;
1392 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1393 src_vq->ops = &coda_qops;
1394 src_vq->mem_ops = &vb2_dma_contig_memops;
1395
1396 ret = vb2_queue_init(src_vq);
1397 if (ret)
1398 return ret;
1399
1400 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1401 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1402 dst_vq->drv_priv = ctx;
1403 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1404 dst_vq->ops = &coda_qops;
1405 dst_vq->mem_ops = &vb2_dma_contig_memops;
1406
1407 return vb2_queue_init(dst_vq);
1408 }
1409
1410 static int coda_next_free_instance(struct coda_dev *dev)
1411 {
1412 return ffz(dev->instance_mask);
1413 }
1414
1415 static int coda_open(struct file *file)
1416 {
1417 struct coda_dev *dev = video_drvdata(file);
1418 struct coda_ctx *ctx = NULL;
1419 int ret = 0;
1420 int idx;
1421
1422 idx = coda_next_free_instance(dev);
1423 if (idx >= CODA_MAX_INSTANCES)
1424 return -EBUSY;
1425 set_bit(idx, &dev->instance_mask);
1426
1427 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1428 if (!ctx)
1429 return -ENOMEM;
1430
1431 v4l2_fh_init(&ctx->fh, video_devdata(file));
1432 file->private_data = &ctx->fh;
1433 v4l2_fh_add(&ctx->fh);
1434 ctx->dev = dev;
1435 ctx->idx = idx;
1436
1437 set_default_params(ctx);
1438 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
1439 &coda_queue_init);
1440 if (IS_ERR(ctx->m2m_ctx)) {
1441 int ret = PTR_ERR(ctx->m2m_ctx);
1442
1443 v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
1444 __func__, ret);
1445 goto err;
1446 }
1447 ret = coda_ctrls_setup(ctx);
1448 if (ret) {
1449 v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
1450 goto err;
1451 }
1452
1453 ctx->fh.ctrl_handler = &ctx->ctrls;
1454
1455 ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
1456 CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
1457 if (!ctx->parabuf.vaddr) {
1458 v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
1459 ret = -ENOMEM;
1460 goto err;
1461 }
1462
1463 coda_lock(ctx);
1464 list_add(&ctx->list, &dev->instances);
1465 coda_unlock(ctx);
1466
1467 clk_prepare_enable(dev->clk_per);
1468 clk_prepare_enable(dev->clk_ahb);
1469
1470 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
1471 ctx->idx, ctx);
1472
1473 return 0;
1474
1475 err:
1476 v4l2_fh_del(&ctx->fh);
1477 v4l2_fh_exit(&ctx->fh);
1478 kfree(ctx);
1479 return ret;
1480 }
1481
1482 static int coda_release(struct file *file)
1483 {
1484 struct coda_dev *dev = video_drvdata(file);
1485 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1486
1487 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
1488 ctx);
1489
1490 coda_lock(ctx);
1491 list_del(&ctx->list);
1492 coda_unlock(ctx);
1493
1494 dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
1495 ctx->parabuf.vaddr, ctx->parabuf.paddr);
1496 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1497 v4l2_ctrl_handler_free(&ctx->ctrls);
1498 clk_disable_unprepare(dev->clk_per);
1499 clk_disable_unprepare(dev->clk_ahb);
1500 v4l2_fh_del(&ctx->fh);
1501 v4l2_fh_exit(&ctx->fh);
1502 clear_bit(ctx->idx, &dev->instance_mask);
1503 kfree(ctx);
1504
1505 return 0;
1506 }
1507
1508 static unsigned int coda_poll(struct file *file,
1509 struct poll_table_struct *wait)
1510 {
1511 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1512 int ret;
1513
1514 coda_lock(ctx);
1515 ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1516 coda_unlock(ctx);
1517 return ret;
1518 }
1519
1520 static int coda_mmap(struct file *file, struct vm_area_struct *vma)
1521 {
1522 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1523
1524 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1525 }
1526
1527 static const struct v4l2_file_operations coda_fops = {
1528 .owner = THIS_MODULE,
1529 .open = coda_open,
1530 .release = coda_release,
1531 .poll = coda_poll,
1532 .unlocked_ioctl = video_ioctl2,
1533 .mmap = coda_mmap,
1534 };
1535
1536 static irqreturn_t coda_irq_handler(int irq, void *data)
1537 {
1538 struct vb2_buffer *src_buf, *dst_buf;
1539 struct coda_dev *dev = data;
1540 u32 wr_ptr, start_ptr;
1541 struct coda_ctx *ctx;
1542
1543 cancel_delayed_work(&dev->timeout);
1544
1545 /* read status register to attend the IRQ */
1546 coda_read(dev, CODA_REG_BIT_INT_STATUS);
1547 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
1548 CODA_REG_BIT_INT_CLEAR);
1549
1550 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1551 if (ctx == NULL) {
1552 v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
1553 return IRQ_HANDLED;
1554 }
1555
1556 if (ctx->aborting) {
1557 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1558 "task has been aborted\n");
1559 return IRQ_HANDLED;
1560 }
1561
1562 if (coda_isbusy(ctx->dev)) {
1563 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1564 "coda is still busy!!!!\n");
1565 return IRQ_NONE;
1566 }
1567
1568 complete(&dev->done);
1569
1570 src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1571 dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
1572
1573 /* Get results from the coda */
1574 coda_read(dev, CODA_RET_ENC_PIC_TYPE);
1575 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1576 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
1577 /* Calculate bytesused field */
1578 if (dst_buf->v4l2_buf.sequence == 0) {
1579 dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
1580 ctx->vpu_header_size[0] +
1581 ctx->vpu_header_size[1] +
1582 ctx->vpu_header_size[2];
1583 } else {
1584 dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
1585 }
1586
1587 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1588 wr_ptr - start_ptr);
1589
1590 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1591 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1592
1593 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1594 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1595 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1596 } else {
1597 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1598 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1599 }
1600
1601 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1602 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1603
1604 ctx->gopcounter--;
1605 if (ctx->gopcounter < 0)
1606 ctx->gopcounter = ctx->params.gop_size - 1;
1607
1608 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1609 "job finished: encoding frame (%d) (%s)\n",
1610 dst_buf->v4l2_buf.sequence,
1611 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1612 "KEYFRAME" : "PFRAME");
1613
1614 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
1615
1616 return IRQ_HANDLED;
1617 }
1618
1619 static void coda_timeout(struct work_struct *work)
1620 {
1621 struct coda_ctx *ctx;
1622 struct coda_dev *dev = container_of(to_delayed_work(work),
1623 struct coda_dev, timeout);
1624
1625 if (completion_done(&dev->done))
1626 return;
1627
1628 complete(&dev->done);
1629
1630 v4l2_err(&dev->v4l2_dev, "CODA PIC_RUN timeout, stopping all streams\n");
1631
1632 mutex_lock(&dev->dev_mutex);
1633 list_for_each_entry(ctx, &dev->instances, list) {
1634 v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1635 v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1636 }
1637 mutex_unlock(&dev->dev_mutex);
1638 }
1639
1640 static u32 coda_supported_firmwares[] = {
1641 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
1642 CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
1643 };
1644
1645 static bool coda_firmware_supported(u32 vernum)
1646 {
1647 int i;
1648
1649 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
1650 if (vernum == coda_supported_firmwares[i])
1651 return true;
1652 return false;
1653 }
1654
1655 static char *coda_product_name(int product)
1656 {
1657 static char buf[9];
1658
1659 switch (product) {
1660 case CODA_DX6:
1661 return "CodaDx6";
1662 case CODA_7541:
1663 return "CODA7541";
1664 default:
1665 snprintf(buf, sizeof(buf), "(0x%04x)", product);
1666 return buf;
1667 }
1668 }
1669
1670 static int coda_hw_init(struct coda_dev *dev)
1671 {
1672 u16 product, major, minor, release;
1673 u32 data;
1674 u16 *p;
1675 int i;
1676
1677 clk_prepare_enable(dev->clk_per);
1678 clk_prepare_enable(dev->clk_ahb);
1679
1680 /*
1681 * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
1682 * The 16-bit chars in the code buffer are in memory access
1683 * order, re-sort them to CODA order for register download.
1684 * Data in this SRAM survives a reboot.
1685 */
1686 p = (u16 *)dev->codebuf.vaddr;
1687 if (dev->devtype->product == CODA_DX6) {
1688 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
1689 data = CODA_DOWN_ADDRESS_SET(i) |
1690 CODA_DOWN_DATA_SET(p[i ^ 1]);
1691 coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
1692 }
1693 } else {
1694 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
1695 data = CODA_DOWN_ADDRESS_SET(i) |
1696 CODA_DOWN_DATA_SET(p[round_down(i, 4) +
1697 3 - (i % 4)]);
1698 coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
1699 }
1700 }
1701
1702 /* Tell the BIT where to find everything it needs */
1703 coda_write(dev, dev->workbuf.paddr,
1704 CODA_REG_BIT_WORK_BUF_ADDR);
1705 coda_write(dev, dev->codebuf.paddr,
1706 CODA_REG_BIT_CODE_BUF_ADDR);
1707 coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
1708
1709 /* Set default values */
1710 switch (dev->devtype->product) {
1711 case CODA_DX6:
1712 coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
1713 break;
1714 default:
1715 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
1716 }
1717 coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
1718
1719 if (dev->devtype->product != CODA_DX6)
1720 coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
1721
1722 coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
1723 CODA_REG_BIT_INT_ENABLE);
1724
1725 /* Reset VPU and start processor */
1726 data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
1727 data |= CODA_REG_RESET_ENABLE;
1728 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
1729 udelay(10);
1730 data &= ~CODA_REG_RESET_ENABLE;
1731 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
1732 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
1733
1734 /* Load firmware */
1735 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
1736 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
1737 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
1738 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
1739 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
1740 if (coda_wait_timeout(dev)) {
1741 clk_disable_unprepare(dev->clk_per);
1742 clk_disable_unprepare(dev->clk_ahb);
1743 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
1744 return -EIO;
1745 }
1746
1747 /* Check we are compatible with the loaded firmware */
1748 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
1749 product = CODA_FIRMWARE_PRODUCT(data);
1750 major = CODA_FIRMWARE_MAJOR(data);
1751 minor = CODA_FIRMWARE_MINOR(data);
1752 release = CODA_FIRMWARE_RELEASE(data);
1753
1754 clk_disable_unprepare(dev->clk_per);
1755 clk_disable_unprepare(dev->clk_ahb);
1756
1757 if (product != dev->devtype->product) {
1758 v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
1759 " Version: %u.%u.%u\n",
1760 coda_product_name(dev->devtype->product),
1761 coda_product_name(product), major, minor, release);
1762 return -EINVAL;
1763 }
1764
1765 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
1766 coda_product_name(product));
1767
1768 if (coda_firmware_supported(data)) {
1769 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
1770 major, minor, release);
1771 } else {
1772 v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
1773 "%u.%u.%u\n", major, minor, release);
1774 }
1775
1776 return 0;
1777 }
1778
1779 static void coda_fw_callback(const struct firmware *fw, void *context)
1780 {
1781 struct coda_dev *dev = context;
1782 struct platform_device *pdev = dev->plat_dev;
1783 int ret;
1784
1785 if (!fw) {
1786 v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
1787 return;
1788 }
1789
1790 /* allocate auxiliary per-device code buffer for the BIT processor */
1791 dev->codebuf.size = fw->size;
1792 dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
1793 &dev->codebuf.paddr,
1794 GFP_KERNEL);
1795 if (!dev->codebuf.vaddr) {
1796 dev_err(&pdev->dev, "failed to allocate code buffer\n");
1797 return;
1798 }
1799
1800 /* Copy the whole firmware image to the code buffer */
1801 memcpy(dev->codebuf.vaddr, fw->data, fw->size);
1802 release_firmware(fw);
1803
1804 ret = coda_hw_init(dev);
1805 if (ret) {
1806 v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
1807 return;
1808 }
1809
1810 dev->vfd.fops = &coda_fops,
1811 dev->vfd.ioctl_ops = &coda_ioctl_ops;
1812 dev->vfd.release = video_device_release_empty,
1813 dev->vfd.lock = &dev->dev_mutex;
1814 dev->vfd.v4l2_dev = &dev->v4l2_dev;
1815 dev->vfd.vfl_dir = VFL_DIR_M2M;
1816 snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
1817 video_set_drvdata(&dev->vfd, dev);
1818
1819 dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1820 if (IS_ERR(dev->alloc_ctx)) {
1821 v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
1822 return;
1823 }
1824
1825 dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
1826 if (IS_ERR(dev->m2m_dev)) {
1827 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
1828 goto rel_ctx;
1829 }
1830
1831 ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
1832 if (ret) {
1833 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1834 goto rel_m2m;
1835 }
1836 v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
1837 dev->vfd.num);
1838
1839 return;
1840
1841 rel_m2m:
1842 v4l2_m2m_release(dev->m2m_dev);
1843 rel_ctx:
1844 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
1845 }
1846
1847 static int coda_firmware_request(struct coda_dev *dev)
1848 {
1849 char *fw = dev->devtype->firmware;
1850
1851 dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
1852 coda_product_name(dev->devtype->product));
1853
1854 return request_firmware_nowait(THIS_MODULE, true,
1855 fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
1856 }
1857
1858 enum coda_platform {
1859 CODA_IMX27,
1860 CODA_IMX53,
1861 };
1862
1863 static const struct coda_devtype coda_devdata[] = {
1864 [CODA_IMX27] = {
1865 .firmware = "v4l-codadx6-imx27.bin",
1866 .product = CODA_DX6,
1867 .formats = codadx6_formats,
1868 .num_formats = ARRAY_SIZE(codadx6_formats),
1869 },
1870 [CODA_IMX53] = {
1871 .firmware = "v4l-coda7541-imx53.bin",
1872 .product = CODA_7541,
1873 .formats = coda7_formats,
1874 .num_formats = ARRAY_SIZE(coda7_formats),
1875 },
1876 };
1877
1878 static struct platform_device_id coda_platform_ids[] = {
1879 { .name = "coda-imx27", .driver_data = CODA_IMX27 },
1880 { .name = "coda-imx53", .driver_data = CODA_IMX53 },
1881 { /* sentinel */ }
1882 };
1883 MODULE_DEVICE_TABLE(platform, coda_platform_ids);
1884
1885 #ifdef CONFIG_OF
1886 static const struct of_device_id coda_dt_ids[] = {
1887 { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
1888 { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
1889 { /* sentinel */ }
1890 };
1891 MODULE_DEVICE_TABLE(of, coda_dt_ids);
1892 #endif
1893
1894 static int coda_probe(struct platform_device *pdev)
1895 {
1896 const struct of_device_id *of_id =
1897 of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
1898 const struct platform_device_id *pdev_id;
1899 struct coda_dev *dev;
1900 struct resource *res;
1901 int ret, irq;
1902
1903 dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
1904 if (!dev) {
1905 dev_err(&pdev->dev, "Not enough memory for %s\n",
1906 CODA_NAME);
1907 return -ENOMEM;
1908 }
1909
1910 spin_lock_init(&dev->irqlock);
1911 INIT_LIST_HEAD(&dev->instances);
1912 INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
1913 init_completion(&dev->done);
1914 complete(&dev->done);
1915
1916 dev->plat_dev = pdev;
1917 dev->clk_per = devm_clk_get(&pdev->dev, "per");
1918 if (IS_ERR(dev->clk_per)) {
1919 dev_err(&pdev->dev, "Could not get per clock\n");
1920 return PTR_ERR(dev->clk_per);
1921 }
1922
1923 dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1924 if (IS_ERR(dev->clk_ahb)) {
1925 dev_err(&pdev->dev, "Could not get ahb clock\n");
1926 return PTR_ERR(dev->clk_ahb);
1927 }
1928
1929 /* Get memory for physical registers */
1930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1931 if (res == NULL) {
1932 dev_err(&pdev->dev, "failed to get memory region resource\n");
1933 return -ENOENT;
1934 }
1935
1936 if (devm_request_mem_region(&pdev->dev, res->start,
1937 resource_size(res), CODA_NAME) == NULL) {
1938 dev_err(&pdev->dev, "failed to request memory region\n");
1939 return -ENOENT;
1940 }
1941 dev->regs_base = devm_ioremap(&pdev->dev, res->start,
1942 resource_size(res));
1943 if (!dev->regs_base) {
1944 dev_err(&pdev->dev, "failed to ioremap address region\n");
1945 return -ENOENT;
1946 }
1947
1948 /* IRQ */
1949 irq = platform_get_irq(pdev, 0);
1950 if (irq < 0) {
1951 dev_err(&pdev->dev, "failed to get irq resource\n");
1952 return -ENOENT;
1953 }
1954
1955 if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
1956 0, CODA_NAME, dev) < 0) {
1957 dev_err(&pdev->dev, "failed to request irq\n");
1958 return -ENOENT;
1959 }
1960
1961 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1962 if (ret)
1963 return ret;
1964
1965 mutex_init(&dev->dev_mutex);
1966
1967 pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
1968
1969 if (of_id) {
1970 dev->devtype = of_id->data;
1971 } else if (pdev_id) {
1972 dev->devtype = &coda_devdata[pdev_id->driver_data];
1973 } else {
1974 v4l2_device_unregister(&dev->v4l2_dev);
1975 return -EINVAL;
1976 }
1977
1978 /* allocate auxiliary per-device buffers for the BIT processor */
1979 switch (dev->devtype->product) {
1980 case CODA_DX6:
1981 dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
1982 break;
1983 default:
1984 dev->workbuf.size = CODA7_WORK_BUF_SIZE;
1985 }
1986 dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
1987 &dev->workbuf.paddr,
1988 GFP_KERNEL);
1989 if (!dev->workbuf.vaddr) {
1990 dev_err(&pdev->dev, "failed to allocate work buffer\n");
1991 v4l2_device_unregister(&dev->v4l2_dev);
1992 return -ENOMEM;
1993 }
1994
1995 if (dev->devtype->product == CODA_DX6) {
1996 dev->iram_paddr = 0xffff4c00;
1997 } else {
1998 void __iomem *iram_vaddr;
1999
2000 iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
2001 &dev->iram_paddr);
2002 if (!iram_vaddr) {
2003 dev_err(&pdev->dev, "unable to alloc iram\n");
2004 return -ENOMEM;
2005 }
2006 }
2007
2008 platform_set_drvdata(pdev, dev);
2009
2010 return coda_firmware_request(dev);
2011 }
2012
2013 static int coda_remove(struct platform_device *pdev)
2014 {
2015 struct coda_dev *dev = platform_get_drvdata(pdev);
2016
2017 video_unregister_device(&dev->vfd);
2018 if (dev->m2m_dev)
2019 v4l2_m2m_release(dev->m2m_dev);
2020 if (dev->alloc_ctx)
2021 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2022 v4l2_device_unregister(&dev->v4l2_dev);
2023 if (dev->iram_paddr)
2024 iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
2025 if (dev->codebuf.vaddr)
2026 dma_free_coherent(&pdev->dev, dev->codebuf.size,
2027 &dev->codebuf.vaddr, dev->codebuf.paddr);
2028 if (dev->workbuf.vaddr)
2029 dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
2030 dev->workbuf.paddr);
2031 return 0;
2032 }
2033
2034 static struct platform_driver coda_driver = {
2035 .probe = coda_probe,
2036 .remove = coda_remove,
2037 .driver = {
2038 .name = CODA_NAME,
2039 .owner = THIS_MODULE,
2040 .of_match_table = of_match_ptr(coda_dt_ids),
2041 },
2042 .id_table = coda_platform_ids,
2043 };
2044
2045 module_platform_driver(coda_driver);
2046
2047 MODULE_LICENSE("GPL");
2048 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
2049 MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");
kernel source for telekom puls (alcatel/mediatek)