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b83dafa4e12cdcc79a023fe683f1394eeb05de72
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / dvb / frontends / tda1004x.c
1 /*
2 Driver for Philips tda1004xh OFDM Demodulator
3
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 */
22 /*
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware
27 * or /lib/firmware (depending on configuration of firmware hotplug).
28 */
29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/device.h>
36 #include <linux/jiffies.h>
37 #include <linux/string.h>
38 #include <linux/slab.h>
39
40 #include "dvb_frontend.h"
41 #include "tda1004x.h"
42
43 enum tda1004x_demod {
44 TDA1004X_DEMOD_TDA10045,
45 TDA1004X_DEMOD_TDA10046,
46 };
47
48 struct tda1004x_state {
49 struct i2c_adapter* i2c;
50 struct dvb_frontend_ops ops;
51 const struct tda1004x_config* config;
52 struct dvb_frontend frontend;
53
54 /* private demod data */
55 enum tda1004x_demod demod_type;
56 };
57
58 static int debug;
59 #define dprintk(args...) \
60 do { \
61 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
62 } while (0)
63
64 #define TDA1004X_CHIPID 0x00
65 #define TDA1004X_AUTO 0x01
66 #define TDA1004X_IN_CONF1 0x02
67 #define TDA1004X_IN_CONF2 0x03
68 #define TDA1004X_OUT_CONF1 0x04
69 #define TDA1004X_OUT_CONF2 0x05
70 #define TDA1004X_STATUS_CD 0x06
71 #define TDA1004X_CONFC4 0x07
72 #define TDA1004X_DSSPARE2 0x0C
73 #define TDA10045H_CODE_IN 0x0D
74 #define TDA10045H_FWPAGE 0x0E
75 #define TDA1004X_SCAN_CPT 0x10
76 #define TDA1004X_DSP_CMD 0x11
77 #define TDA1004X_DSP_ARG 0x12
78 #define TDA1004X_DSP_DATA1 0x13
79 #define TDA1004X_DSP_DATA2 0x14
80 #define TDA1004X_CONFADC1 0x15
81 #define TDA1004X_CONFC1 0x16
82 #define TDA10045H_S_AGC 0x1a
83 #define TDA10046H_AGC_TUN_LEVEL 0x1a
84 #define TDA1004X_SNR 0x1c
85 #define TDA1004X_CONF_TS1 0x1e
86 #define TDA1004X_CONF_TS2 0x1f
87 #define TDA1004X_CBER_RESET 0x20
88 #define TDA1004X_CBER_MSB 0x21
89 #define TDA1004X_CBER_LSB 0x22
90 #define TDA1004X_CVBER_LUT 0x23
91 #define TDA1004X_VBER_MSB 0x24
92 #define TDA1004X_VBER_MID 0x25
93 #define TDA1004X_VBER_LSB 0x26
94 #define TDA1004X_UNCOR 0x27
95
96 #define TDA10045H_CONFPLL_P 0x2D
97 #define TDA10045H_CONFPLL_M_MSB 0x2E
98 #define TDA10045H_CONFPLL_M_LSB 0x2F
99 #define TDA10045H_CONFPLL_N 0x30
100
101 #define TDA10046H_CONFPLL1 0x2D
102 #define TDA10046H_CONFPLL2 0x2F
103 #define TDA10046H_CONFPLL3 0x30
104 #define TDA10046H_TIME_WREF1 0x31
105 #define TDA10046H_TIME_WREF2 0x32
106 #define TDA10046H_TIME_WREF3 0x33
107 #define TDA10046H_TIME_WREF4 0x34
108 #define TDA10046H_TIME_WREF5 0x35
109
110 #define TDA10045H_UNSURW_MSB 0x31
111 #define TDA10045H_UNSURW_LSB 0x32
112 #define TDA10045H_WREF_MSB 0x33
113 #define TDA10045H_WREF_MID 0x34
114 #define TDA10045H_WREF_LSB 0x35
115 #define TDA10045H_MUXOUT 0x36
116 #define TDA1004X_CONFADC2 0x37
117
118 #define TDA10045H_IOFFSET 0x38
119
120 #define TDA10046H_CONF_TRISTATE1 0x3B
121 #define TDA10046H_CONF_TRISTATE2 0x3C
122 #define TDA10046H_CONF_POLARITY 0x3D
123 #define TDA10046H_FREQ_OFFSET 0x3E
124 #define TDA10046H_GPIO_OUT_SEL 0x41
125 #define TDA10046H_GPIO_SELECT 0x42
126 #define TDA10046H_AGC_CONF 0x43
127 #define TDA10046H_AGC_THR 0x44
128 #define TDA10046H_AGC_RENORM 0x45
129 #define TDA10046H_AGC_GAINS 0x46
130 #define TDA10046H_AGC_TUN_MIN 0x47
131 #define TDA10046H_AGC_TUN_MAX 0x48
132 #define TDA10046H_AGC_IF_MIN 0x49
133 #define TDA10046H_AGC_IF_MAX 0x4A
134
135 #define TDA10046H_FREQ_PHY2_MSB 0x4D
136 #define TDA10046H_FREQ_PHY2_LSB 0x4E
137
138 #define TDA10046H_CVBER_CTRL 0x4F
139 #define TDA10046H_AGC_IF_LEVEL 0x52
140 #define TDA10046H_CODE_CPT 0x57
141 #define TDA10046H_CODE_IN 0x58
142
143
144 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
145 {
146 int ret;
147 u8 buf[] = { reg, data };
148 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
149
150 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
151
152 msg.addr = state->config->demod_address;
153 ret = i2c_transfer(state->i2c, &msg, 1);
154
155 if (ret != 1)
156 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
157 __FUNCTION__, reg, data, ret);
158
159 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
160 reg, data, ret);
161 return (ret != 1) ? -1 : 0;
162 }
163
164 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
165 {
166 int ret;
167 u8 b0[] = { reg };
168 u8 b1[] = { 0 };
169 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
170 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
171
172 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
173
174 msg[0].addr = state->config->demod_address;
175 msg[1].addr = state->config->demod_address;
176 ret = i2c_transfer(state->i2c, msg, 2);
177
178 if (ret != 2) {
179 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
180 ret);
181 return -1;
182 }
183
184 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
185 reg, b1[0], ret);
186 return b1[0];
187 }
188
189 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
190 {
191 int val;
192 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
193 mask, data);
194
195 // read a byte and check
196 val = tda1004x_read_byte(state, reg);
197 if (val < 0)
198 return val;
199
200 // mask if off
201 val = val & ~mask;
202 val |= data & 0xff;
203
204 // write it out again
205 return tda1004x_write_byteI(state, reg, val);
206 }
207
208 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
209 {
210 int i;
211 int result;
212
213 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
214
215 result = 0;
216 for (i = 0; i < len; i++) {
217 result = tda1004x_write_byteI(state, reg + i, buf[i]);
218 if (result != 0)
219 break;
220 }
221
222 return result;
223 }
224
225 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
226 {
227 int result;
228 dprintk("%s\n", __FUNCTION__);
229
230 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
231 msleep(20);
232 return result;
233 }
234
235 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
236 {
237 dprintk("%s\n", __FUNCTION__);
238
239 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
240 }
241
242 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
243 fe_bandwidth_t bandwidth)
244 {
245 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
246 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
247 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
248
249 switch (bandwidth) {
250 case BANDWIDTH_6_MHZ:
251 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
252 break;
253
254 case BANDWIDTH_7_MHZ:
255 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
256 break;
257
258 case BANDWIDTH_8_MHZ:
259 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
260 break;
261
262 default:
263 return -EINVAL;
264 }
265
266 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
267
268 return 0;
269 }
270
271 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
272 fe_bandwidth_t bandwidth)
273 {
274 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
275 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
276 static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
277
278 static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
279 static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
280 static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
281 int tda10046_clk53m;
282
283 if ((state->config->if_freq == TDA10046_FREQ_045) ||
284 (state->config->if_freq == TDA10046_FREQ_052))
285 tda10046_clk53m = 0;
286 else
287 tda10046_clk53m = 1;
288 switch (bandwidth) {
289 case BANDWIDTH_6_MHZ:
290 if (tda10046_clk53m)
291 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
292 sizeof(bandwidth_6mhz_53M));
293 else
294 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
295 sizeof(bandwidth_6mhz_48M));
296 if (state->config->if_freq == TDA10046_FREQ_045) {
297 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
298 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
299 }
300 break;
301
302 case BANDWIDTH_7_MHZ:
303 if (tda10046_clk53m)
304 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
305 sizeof(bandwidth_7mhz_53M));
306 else
307 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
308 sizeof(bandwidth_7mhz_48M));
309 if (state->config->if_freq == TDA10046_FREQ_045) {
310 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
311 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
312 }
313 break;
314
315 case BANDWIDTH_8_MHZ:
316 if (tda10046_clk53m)
317 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
318 sizeof(bandwidth_8mhz_53M));
319 else
320 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
321 sizeof(bandwidth_8mhz_48M));
322 if (state->config->if_freq == TDA10046_FREQ_045) {
323 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
324 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
325 }
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return 0;
333 }
334
335 static int tda1004x_do_upload(struct tda1004x_state *state,
336 unsigned char *mem, unsigned int len,
337 u8 dspCodeCounterReg, u8 dspCodeInReg)
338 {
339 u8 buf[65];
340 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
341 int tx_size;
342 int pos = 0;
343
344 /* clear code counter */
345 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
346 fw_msg.addr = state->config->demod_address;
347
348 buf[0] = dspCodeInReg;
349 while (pos != len) {
350 // work out how much to send this time
351 tx_size = len - pos;
352 if (tx_size > 0x10)
353 tx_size = 0x10;
354
355 // send the chunk
356 memcpy(buf + 1, mem + pos, tx_size);
357 fw_msg.len = tx_size + 1;
358 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
359 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
360 return -EIO;
361 }
362 pos += tx_size;
363
364 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
365 }
366 // give the DSP a chance to settle 03/10/05 Hac
367 msleep(100);
368
369 return 0;
370 }
371
372 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
373 {
374 u8 data1, data2;
375 unsigned long timeout;
376
377 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
378 timeout = jiffies + 2 * HZ;
379 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
380 if (time_after(jiffies, timeout)) {
381 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
382 break;
383 }
384 msleep(1);
385 }
386 } else
387 msleep(100);
388
389 // check upload was OK
390 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
391 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
392
393 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
394 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
395 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
396 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
397 return -EIO;
398 }
399 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
400 return 0;
401 }
402
403 static int tda10045_fwupload(struct dvb_frontend* fe)
404 {
405 struct tda1004x_state* state = fe->demodulator_priv;
406 int ret;
407 const struct firmware *fw;
408
409 /* don't re-upload unless necessary */
410 if (tda1004x_check_upload_ok(state) == 0)
411 return 0;
412
413 /* request the firmware, this will block until someone uploads it */
414 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
415 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
416 if (ret) {
417 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
418 return ret;
419 }
420
421 /* reset chip */
422 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
423 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
424 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
425 msleep(10);
426
427 /* set parameters */
428 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
429
430 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
431 release_firmware(fw);
432 if (ret)
433 return ret;
434 printk(KERN_INFO "tda1004x: firmware upload complete\n");
435
436 /* wait for DSP to initialise */
437 /* DSPREADY doesn't seem to work on the TDA10045H */
438 msleep(100);
439
440 return tda1004x_check_upload_ok(state);
441 }
442
443 static void tda10046_init_plls(struct dvb_frontend* fe)
444 {
445 struct tda1004x_state* state = fe->demodulator_priv;
446 int tda10046_clk53m;
447
448 if ((state->config->if_freq == TDA10046_FREQ_045) ||
449 (state->config->if_freq == TDA10046_FREQ_052))
450 tda10046_clk53m = 0;
451 else
452 tda10046_clk53m = 1;
453
454 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
455 if(tda10046_clk53m) {
456 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
457 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
458 } else {
459 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
460 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
461 }
462 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
463 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
464 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
465 } else {
466 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
467 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
468 }
469 if(tda10046_clk53m)
470 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
471 else
472 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
473 /* Note clock frequency is handled implicitly */
474 switch (state->config->if_freq) {
475 case TDA10046_FREQ_045:
476 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
477 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
478 break;
479 case TDA10046_FREQ_052:
480 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
481 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
482 break;
483 case TDA10046_FREQ_3617:
484 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
485 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
486 break;
487 case TDA10046_FREQ_3613:
488 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
489 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
490 break;
491 }
492 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
493 /* let the PLLs settle */
494 msleep(120);
495 }
496
497 static int tda10046_fwupload(struct dvb_frontend* fe)
498 {
499 struct tda1004x_state* state = fe->demodulator_priv;
500 int ret;
501 const struct firmware *fw;
502
503 /* reset + wake up chip */
504 if (state->config->xtal_freq == TDA10046_XTAL_4M) {
505 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
506 } else {
507 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
508 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
509 }
510 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
511 /* let the clocks recover from sleep */
512 msleep(5);
513
514 /* The PLLs need to be reprogrammed after sleep */
515 tda10046_init_plls(fe);
516
517 /* don't re-upload unless necessary */
518 if (tda1004x_check_upload_ok(state) == 0)
519 return 0;
520
521 if (state->config->request_firmware != NULL) {
522 /* request the firmware, this will block until someone uploads it */
523 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
524 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
525 if (ret) {
526 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
527 return ret;
528 }
529 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
530 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
531 release_firmware(fw);
532 if (ret)
533 return ret;
534 } else {
535 /* boot from firmware eeprom */
536 printk(KERN_INFO "tda1004x: booting from eeprom\n");
537 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
538 msleep(300);
539 }
540 return tda1004x_check_upload_ok(state);
541 }
542
543 static int tda1004x_encode_fec(int fec)
544 {
545 // convert known FEC values
546 switch (fec) {
547 case FEC_1_2:
548 return 0;
549 case FEC_2_3:
550 return 1;
551 case FEC_3_4:
552 return 2;
553 case FEC_5_6:
554 return 3;
555 case FEC_7_8:
556 return 4;
557 }
558
559 // unsupported
560 return -EINVAL;
561 }
562
563 static int tda1004x_decode_fec(int tdafec)
564 {
565 // convert known FEC values
566 switch (tdafec) {
567 case 0:
568 return FEC_1_2;
569 case 1:
570 return FEC_2_3;
571 case 2:
572 return FEC_3_4;
573 case 3:
574 return FEC_5_6;
575 case 4:
576 return FEC_7_8;
577 }
578
579 // unsupported
580 return -1;
581 }
582
583 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
584 {
585 struct tda1004x_state* state = fe->demodulator_priv;
586
587 return tda1004x_write_byteI(state, reg, data);
588 }
589
590 static int tda10045_init(struct dvb_frontend* fe)
591 {
592 struct tda1004x_state* state = fe->demodulator_priv;
593
594 dprintk("%s\n", __FUNCTION__);
595
596 if (tda10045_fwupload(fe)) {
597 printk("tda1004x: firmware upload failed\n");
598 return -EIO;
599 }
600
601 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
602
603 // Init the PLL
604 if (state->config->pll_init) {
605 tda1004x_enable_tuner_i2c(state);
606 state->config->pll_init(fe);
607 tda1004x_disable_tuner_i2c(state);
608 }
609
610 // tda setup
611 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
612 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
613 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
614 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
615 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
616 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
617 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
618 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
619 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
620 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
621 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
622
623 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
624
625 return 0;
626 }
627
628 static int tda10046_init(struct dvb_frontend* fe)
629 {
630 struct tda1004x_state* state = fe->demodulator_priv;
631 dprintk("%s\n", __FUNCTION__);
632
633 if (tda10046_fwupload(fe)) {
634 printk("tda1004x: firmware upload failed\n");
635 return -EIO;
636 }
637
638 // Init the tuner PLL
639 if (state->config->pll_init) {
640 tda1004x_enable_tuner_i2c(state);
641 if (state->config->pll_init(fe)) {
642 printk(KERN_ERR "tda1004x: pll init failed\n");
643 return -EIO;
644 }
645 tda1004x_disable_tuner_i2c(state);
646 }
647
648 // tda setup
649 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
650 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
651 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
652
653 switch (state->config->agc_config) {
654 case TDA10046_AGC_DEFAULT:
655 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
656 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
657 break;
658 case TDA10046_AGC_IFO_AUTO_NEG:
659 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
660 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
661 break;
662 case TDA10046_AGC_IFO_AUTO_POS:
663 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
664 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
665 break;
666 case TDA10046_AGC_TDA827X:
667 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
668 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
669 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
670 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
671 break;
672 case TDA10046_AGC_TDA827X_GPL:
673 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
674 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
675 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
676 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
677 break;
678 }
679 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
680 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
681 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
682 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
683 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
684 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
685 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
686 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
687 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
688 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
689 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
690 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
691
692 return 0;
693 }
694
695 static int tda1004x_set_fe(struct dvb_frontend* fe,
696 struct dvb_frontend_parameters *fe_params)
697 {
698 struct tda1004x_state* state = fe->demodulator_priv;
699 int tmp;
700 int inversion;
701
702 dprintk("%s\n", __FUNCTION__);
703
704 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
705 // setup auto offset
706 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
707 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
708 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
709
710 // disable agc_conf[2]
711 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
712 }
713
714 // set frequency
715 tda1004x_enable_tuner_i2c(state);
716 if (state->config->pll_set(fe, fe_params)) {
717 printk(KERN_ERR "tda1004x: pll set failed\n");
718 return -EIO;
719 }
720 tda1004x_disable_tuner_i2c(state);
721
722 // Hardcoded to use auto as much as possible on the TDA10045 as it
723 // is very unreliable if AUTO mode is _not_ used.
724 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
725 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
726 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
727 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
728 }
729
730 // Set standard params.. or put them to auto
731 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
732 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
733 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
734 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
735 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
736 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
737 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
738 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
739 } else {
740 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
741
742 // set HP FEC
743 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
744 if (tmp < 0)
745 return tmp;
746 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
747
748 // set LP FEC
749 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
750 if (tmp < 0)
751 return tmp;
752 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
753
754 // set constellation
755 switch (fe_params->u.ofdm.constellation) {
756 case QPSK:
757 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
758 break;
759
760 case QAM_16:
761 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
762 break;
763
764 case QAM_64:
765 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
766 break;
767
768 default:
769 return -EINVAL;
770 }
771
772 // set hierarchy
773 switch (fe_params->u.ofdm.hierarchy_information) {
774 case HIERARCHY_NONE:
775 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
776 break;
777
778 case HIERARCHY_1:
779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
780 break;
781
782 case HIERARCHY_2:
783 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
784 break;
785
786 case HIERARCHY_4:
787 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
788 break;
789
790 default:
791 return -EINVAL;
792 }
793 }
794
795 // set bandwidth
796 switch (state->demod_type) {
797 case TDA1004X_DEMOD_TDA10045:
798 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
799 break;
800
801 case TDA1004X_DEMOD_TDA10046:
802 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
803 break;
804 }
805
806 // set inversion
807 inversion = fe_params->inversion;
808 if (state->config->invert)
809 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
810 switch (inversion) {
811 case INVERSION_OFF:
812 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
813 break;
814
815 case INVERSION_ON:
816 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
817 break;
818
819 default:
820 return -EINVAL;
821 }
822
823 // set guard interval
824 switch (fe_params->u.ofdm.guard_interval) {
825 case GUARD_INTERVAL_1_32:
826 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
827 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
828 break;
829
830 case GUARD_INTERVAL_1_16:
831 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
832 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
833 break;
834
835 case GUARD_INTERVAL_1_8:
836 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
837 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
838 break;
839
840 case GUARD_INTERVAL_1_4:
841 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
842 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
843 break;
844
845 case GUARD_INTERVAL_AUTO:
846 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
847 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
848 break;
849
850 default:
851 return -EINVAL;
852 }
853
854 // set transmission mode
855 switch (fe_params->u.ofdm.transmission_mode) {
856 case TRANSMISSION_MODE_2K:
857 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
858 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
859 break;
860
861 case TRANSMISSION_MODE_8K:
862 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
863 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
864 break;
865
866 case TRANSMISSION_MODE_AUTO:
867 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
868 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
869 break;
870
871 default:
872 return -EINVAL;
873 }
874
875 // start the lock
876 switch (state->demod_type) {
877 case TDA1004X_DEMOD_TDA10045:
878 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
879 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
880 break;
881
882 case TDA1004X_DEMOD_TDA10046:
883 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
884 msleep(1);
885 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
886 break;
887 }
888
889 msleep(10);
890
891 return 0;
892 }
893
894 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
895 {
896 struct tda1004x_state* state = fe->demodulator_priv;
897
898 dprintk("%s\n", __FUNCTION__);
899
900 // inversion status
901 fe_params->inversion = INVERSION_OFF;
902 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
903 fe_params->inversion = INVERSION_ON;
904 if (state->config->invert)
905 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
906
907 // bandwidth
908 switch (state->demod_type) {
909 case TDA1004X_DEMOD_TDA10045:
910 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
911 case 0x14:
912 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
913 break;
914 case 0xdb:
915 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
916 break;
917 case 0x4f:
918 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
919 break;
920 }
921 break;
922 case TDA1004X_DEMOD_TDA10046:
923 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
924 case 0x5c:
925 case 0x54:
926 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
927 break;
928 case 0x6a:
929 case 0x60:
930 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
931 break;
932 case 0x7b:
933 case 0x70:
934 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
935 break;
936 }
937 break;
938 }
939
940 // FEC
941 fe_params->u.ofdm.code_rate_HP =
942 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
943 fe_params->u.ofdm.code_rate_LP =
944 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
945
946 // constellation
947 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
948 case 0:
949 fe_params->u.ofdm.constellation = QPSK;
950 break;
951 case 1:
952 fe_params->u.ofdm.constellation = QAM_16;
953 break;
954 case 2:
955 fe_params->u.ofdm.constellation = QAM_64;
956 break;
957 }
958
959 // transmission mode
960 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
961 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
962 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
963
964 // guard interval
965 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
966 case 0:
967 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
968 break;
969 case 1:
970 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
971 break;
972 case 2:
973 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
974 break;
975 case 3:
976 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
977 break;
978 }
979
980 // hierarchy
981 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
982 case 0:
983 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
984 break;
985 case 1:
986 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
987 break;
988 case 2:
989 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
990 break;
991 case 3:
992 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
993 break;
994 }
995
996 return 0;
997 }
998
999 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
1000 {
1001 struct tda1004x_state* state = fe->demodulator_priv;
1002 int status;
1003 int cber;
1004 int vber;
1005
1006 dprintk("%s\n", __FUNCTION__);
1007
1008 // read status
1009 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
1010 if (status == -1)
1011 return -EIO;
1012
1013 // decode
1014 *fe_status = 0;
1015 if (status & 4)
1016 *fe_status |= FE_HAS_SIGNAL;
1017 if (status & 2)
1018 *fe_status |= FE_HAS_CARRIER;
1019 if (status & 8)
1020 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1021
1022 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1023 // is getting anything valid
1024 if (!(*fe_status & FE_HAS_VITERBI)) {
1025 // read the CBER
1026 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1027 if (cber == -1)
1028 return -EIO;
1029 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1030 if (status == -1)
1031 return -EIO;
1032 cber |= (status << 8);
1033 // The address 0x20 should be read to cope with a TDA10046 bug
1034 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1035
1036 if (cber != 65535)
1037 *fe_status |= FE_HAS_VITERBI;
1038 }
1039
1040 // if we DO have some valid VITERBI output, but don't already have SYNC
1041 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1042 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1043 // read the VBER
1044 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1045 if (vber == -1)
1046 return -EIO;
1047 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1048 if (status == -1)
1049 return -EIO;
1050 vber |= (status << 8);
1051 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1052 if (status == -1)
1053 return -EIO;
1054 vber |= (status & 0x0f) << 16;
1055 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1056 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1057
1058 // if RS has passed some valid TS packets, then we must be
1059 // getting some SYNC bytes
1060 if (vber < 16632)
1061 *fe_status |= FE_HAS_SYNC;
1062 }
1063
1064 // success
1065 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1066 return 0;
1067 }
1068
1069 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1070 {
1071 struct tda1004x_state* state = fe->demodulator_priv;
1072 int tmp;
1073 int reg = 0;
1074
1075 dprintk("%s\n", __FUNCTION__);
1076
1077 // determine the register to use
1078 switch (state->demod_type) {
1079 case TDA1004X_DEMOD_TDA10045:
1080 reg = TDA10045H_S_AGC;
1081 break;
1082
1083 case TDA1004X_DEMOD_TDA10046:
1084 reg = TDA10046H_AGC_IF_LEVEL;
1085 break;
1086 }
1087
1088 // read it
1089 tmp = tda1004x_read_byte(state, reg);
1090 if (tmp < 0)
1091 return -EIO;
1092
1093 *signal = (tmp << 8) | tmp;
1094 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1095 return 0;
1096 }
1097
1098 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1099 {
1100 struct tda1004x_state* state = fe->demodulator_priv;
1101 int tmp;
1102
1103 dprintk("%s\n", __FUNCTION__);
1104
1105 // read it
1106 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1107 if (tmp < 0)
1108 return -EIO;
1109 tmp = 255 - tmp;
1110
1111 *snr = ((tmp << 8) | tmp);
1112 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1113 return 0;
1114 }
1115
1116 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1117 {
1118 struct tda1004x_state* state = fe->demodulator_priv;
1119 int tmp;
1120 int tmp2;
1121 int counter;
1122
1123 dprintk("%s\n", __FUNCTION__);
1124
1125 // read the UCBLOCKS and reset
1126 counter = 0;
1127 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1128 if (tmp < 0)
1129 return -EIO;
1130 tmp &= 0x7f;
1131 while (counter++ < 5) {
1132 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1133 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1134 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1135
1136 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1137 if (tmp2 < 0)
1138 return -EIO;
1139 tmp2 &= 0x7f;
1140 if ((tmp2 < tmp) || (tmp2 == 0))
1141 break;
1142 }
1143
1144 if (tmp != 0x7f)
1145 *ucblocks = tmp;
1146 else
1147 *ucblocks = 0xffffffff;
1148
1149 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1150 return 0;
1151 }
1152
1153 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1154 {
1155 struct tda1004x_state* state = fe->demodulator_priv;
1156 int tmp;
1157
1158 dprintk("%s\n", __FUNCTION__);
1159
1160 // read it in
1161 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1162 if (tmp < 0)
1163 return -EIO;
1164 *ber = tmp << 1;
1165 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1166 if (tmp < 0)
1167 return -EIO;
1168 *ber |= (tmp << 9);
1169 // The address 0x20 should be read to cope with a TDA10046 bug
1170 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1171
1172 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1173 return 0;
1174 }
1175
1176 static int tda1004x_sleep(struct dvb_frontend* fe)
1177 {
1178 struct tda1004x_state* state = fe->demodulator_priv;
1179
1180 switch (state->demod_type) {
1181 case TDA1004X_DEMOD_TDA10045:
1182 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1183 break;
1184
1185 case TDA1004X_DEMOD_TDA10046:
1186 if (state->config->pll_sleep != NULL) {
1187 tda1004x_enable_tuner_i2c(state);
1188 state->config->pll_sleep(fe);
1189 if (state->config->if_freq != TDA10046_FREQ_052) {
1190 /* special hack for Philips EUROPA Based boards:
1191 * keep the I2c bridge open for tuner access in analog mode
1192 */
1193 tda1004x_disable_tuner_i2c(state);
1194 }
1195 }
1196 /* set outputs to tristate */
1197 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1198 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1199 break;
1200 }
1201
1202 return 0;
1203 }
1204
1205 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1206 {
1207 fesettings->min_delay_ms = 800;
1208 /* Drift compensation makes no sense for DVB-T */
1209 fesettings->step_size = 0;
1210 fesettings->max_drift = 0;
1211 return 0;
1212 }
1213
1214 static void tda1004x_release(struct dvb_frontend* fe)
1215 {
1216 struct tda1004x_state *state = fe->demodulator_priv;
1217 kfree(state);
1218 }
1219
1220 static struct dvb_frontend_ops tda10045_ops = {
1221 .info = {
1222 .name = "Philips TDA10045H DVB-T",
1223 .type = FE_OFDM,
1224 .frequency_min = 51000000,
1225 .frequency_max = 858000000,
1226 .frequency_stepsize = 166667,
1227 .caps =
1228 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1229 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1230 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1231 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1232 },
1233
1234 .release = tda1004x_release,
1235
1236 .init = tda10045_init,
1237 .sleep = tda1004x_sleep,
1238
1239 .set_frontend = tda1004x_set_fe,
1240 .get_frontend = tda1004x_get_fe,
1241 .get_tune_settings = tda1004x_get_tune_settings,
1242
1243 .read_status = tda1004x_read_status,
1244 .read_ber = tda1004x_read_ber,
1245 .read_signal_strength = tda1004x_read_signal_strength,
1246 .read_snr = tda1004x_read_snr,
1247 .read_ucblocks = tda1004x_read_ucblocks,
1248 };
1249
1250 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1251 struct i2c_adapter* i2c)
1252 {
1253 struct tda1004x_state *state;
1254
1255 /* allocate memory for the internal state */
1256 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1257 if (!state)
1258 return NULL;
1259
1260 /* setup the state */
1261 state->config = config;
1262 state->i2c = i2c;
1263 memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1264 state->demod_type = TDA1004X_DEMOD_TDA10045;
1265
1266 /* check if the demod is there */
1267 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1268 kfree(state);
1269 return NULL;
1270 }
1271
1272 /* create dvb_frontend */
1273 state->frontend.ops = &state->ops;
1274 state->frontend.demodulator_priv = state;
1275 return &state->frontend;
1276 }
1277
1278 static struct dvb_frontend_ops tda10046_ops = {
1279 .info = {
1280 .name = "Philips TDA10046H DVB-T",
1281 .type = FE_OFDM,
1282 .frequency_min = 51000000,
1283 .frequency_max = 858000000,
1284 .frequency_stepsize = 166667,
1285 .caps =
1286 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1287 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1288 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1289 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1290 },
1291
1292 .release = tda1004x_release,
1293
1294 .init = tda10046_init,
1295 .sleep = tda1004x_sleep,
1296
1297 .set_frontend = tda1004x_set_fe,
1298 .get_frontend = tda1004x_get_fe,
1299 .get_tune_settings = tda1004x_get_tune_settings,
1300
1301 .read_status = tda1004x_read_status,
1302 .read_ber = tda1004x_read_ber,
1303 .read_signal_strength = tda1004x_read_signal_strength,
1304 .read_snr = tda1004x_read_snr,
1305 .read_ucblocks = tda1004x_read_ucblocks,
1306 };
1307
1308 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1309 struct i2c_adapter* i2c)
1310 {
1311 struct tda1004x_state *state;
1312
1313 /* allocate memory for the internal state */
1314 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1315 if (!state)
1316 return NULL;
1317
1318 /* setup the state */
1319 state->config = config;
1320 state->i2c = i2c;
1321 memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1322 state->demod_type = TDA1004X_DEMOD_TDA10046;
1323
1324 /* check if the demod is there */
1325 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1326 kfree(state);
1327 return NULL;
1328 }
1329
1330 /* create dvb_frontend */
1331 state->frontend.ops = &state->ops;
1332 state->frontend.demodulator_priv = state;
1333 return &state->frontend;
1334 }
1335
1336 module_param(debug, int, 0644);
1337 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1338
1339 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1340 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1341 MODULE_LICENSE("GPL");
1342
1343 EXPORT_SYMBOL(tda10045_attach);
1344 EXPORT_SYMBOL(tda10046_attach);
1345 EXPORT_SYMBOL(tda1004x_write_byte);
kernel source for telekom puls (alcatel/mediatek)