4 * Driver for ST STV0900 satellite demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
33 #include "stv0900_reg.h"
34 #include "stv0900_priv.h"
35 #include "stv0900_init.h"
38 module_param_named(debug
, stvdebug
, int, 0644);
40 /* internal params node */
41 struct stv0900_inode
{
42 /* pointer for internal params, one for each pair of demods */
43 struct stv0900_internal
*internal
;
44 struct stv0900_inode
*next_inode
;
47 /* first internal params */
48 static struct stv0900_inode
*stv0900_first_inode
;
50 /* find chip by i2c adapter and i2c address */
51 static struct stv0900_inode
*find_inode(struct i2c_adapter
*i2c_adap
,
54 struct stv0900_inode
*temp_chip
= stv0900_first_inode
;
56 if (temp_chip
!= NULL
) {
58 Search of the last stv0900 chip or
59 find it by i2c adapter and i2c address */
60 while ((temp_chip
!= NULL
) &&
61 ((temp_chip
->internal
->i2c_adap
!= i2c_adap
) ||
62 (temp_chip
->internal
->i2c_addr
!= i2c_addr
)))
64 temp_chip
= temp_chip
->next_inode
;
71 /* deallocating chip */
72 static void remove_inode(struct stv0900_internal
*internal
)
74 struct stv0900_inode
*prev_node
= stv0900_first_inode
;
75 struct stv0900_inode
*del_node
= find_inode(internal
->i2c_adap
,
78 if (del_node
!= NULL
) {
79 if (del_node
== stv0900_first_inode
) {
80 stv0900_first_inode
= del_node
->next_inode
;
82 while (prev_node
->next_inode
!= del_node
)
83 prev_node
= prev_node
->next_inode
;
85 if (del_node
->next_inode
== NULL
)
86 prev_node
->next_inode
= NULL
;
88 prev_node
->next_inode
=
89 prev_node
->next_inode
->next_inode
;
96 /* allocating new chip */
97 static struct stv0900_inode
*append_internal(struct stv0900_internal
*internal
)
99 struct stv0900_inode
*new_node
= stv0900_first_inode
;
101 if (new_node
== NULL
) {
102 new_node
= kmalloc(sizeof(struct stv0900_inode
), GFP_KERNEL
);
103 stv0900_first_inode
= new_node
;
105 while (new_node
->next_inode
!= NULL
)
106 new_node
= new_node
->next_inode
;
108 new_node
->next_inode
= kmalloc(sizeof(struct stv0900_inode
),
110 if (new_node
->next_inode
!= NULL
)
111 new_node
= new_node
->next_inode
;
116 if (new_node
!= NULL
) {
117 new_node
->internal
= internal
;
118 new_node
->next_inode
= NULL
;
124 s32
ge2comp(s32 a
, s32 width
)
129 return (a
>= (1 << (width
- 1))) ? (a
- (1 << width
)) : a
;
132 void stv0900_write_reg(struct stv0900_internal
*intp
, u16 reg_addr
,
137 struct i2c_msg i2cmsg
= {
138 .addr
= intp
->i2c_addr
,
144 data
[0] = MSB(reg_addr
);
145 data
[1] = LSB(reg_addr
);
148 ret
= i2c_transfer(intp
->i2c_adap
, &i2cmsg
, 1);
150 dprintk("%s: i2c error %d\n", __func__
, ret
);
153 u8
stv0900_read_reg(struct stv0900_internal
*intp
, u16 reg
)
156 u8 b0
[] = { MSB(reg
), LSB(reg
) };
158 struct i2c_msg msg
[] = {
160 .addr
= intp
->i2c_addr
,
165 .addr
= intp
->i2c_addr
,
172 ret
= i2c_transfer(intp
->i2c_adap
, msg
, 2);
174 dprintk("%s: i2c error %d, reg[0x%02x]\n",
180 void extract_mask_pos(u32 label
, u8
*mask
, u8
*pos
)
182 u8 position
= 0, i
= 0;
184 (*mask
) = label
& 0xff;
186 while ((position
== 0) && (i
< 8)) {
187 position
= ((*mask
) >> i
) & 0x01;
194 void stv0900_write_bits(struct stv0900_internal
*intp
, u32 label
, u8 val
)
198 reg
= stv0900_read_reg(intp
, (label
>> 16) & 0xffff);
199 extract_mask_pos(label
, &mask
, &pos
);
201 val
= mask
& (val
<< pos
);
203 reg
= (reg
& (~mask
)) | val
;
204 stv0900_write_reg(intp
, (label
>> 16) & 0xffff, reg
);
208 u8
stv0900_get_bits(struct stv0900_internal
*intp
, u32 label
)
213 extract_mask_pos(label
, &mask
, &pos
);
215 val
= stv0900_read_reg(intp
, label
>> 16);
216 val
= (val
& mask
) >> pos
;
221 enum fe_stv0900_error
stv0900_initialize(struct stv0900_internal
*intp
)
226 return STV0900_INVALID_HANDLE
;
228 intp
->chip_id
= stv0900_read_reg(intp
, R0900_MID
);
230 if (intp
->errs
!= STV0900_NO_ERROR
)
234 stv0900_write_reg(intp
, R0900_P1_DMDISTATE
, 0x5c);
235 stv0900_write_reg(intp
, R0900_P2_DMDISTATE
, 0x5c);
237 stv0900_write_reg(intp
, R0900_P1_TNRCFG
, 0x6c);
238 stv0900_write_reg(intp
, R0900_P2_TNRCFG
, 0x6f);
239 stv0900_write_reg(intp
, R0900_P1_I2CRPT
, 0x20);
240 stv0900_write_reg(intp
, R0900_P2_I2CRPT
, 0x20);
241 stv0900_write_reg(intp
, R0900_NCOARSE
, 0x13);
243 stv0900_write_reg(intp
, R0900_I2CCFG
, 0x08);
245 switch (intp
->clkmode
) {
248 stv0900_write_reg(intp
, R0900_SYNTCTRL
, 0x20
252 /* preserve SELOSCI bit */
253 i
= 0x02 & stv0900_read_reg(intp
, R0900_SYNTCTRL
);
254 stv0900_write_reg(intp
, R0900_SYNTCTRL
, 0x20 | i
);
259 for (i
= 0; i
< 181; i
++)
260 stv0900_write_reg(intp
, STV0900_InitVal
[i
][0],
261 STV0900_InitVal
[i
][1]);
263 if (stv0900_read_reg(intp
, R0900_MID
) >= 0x20) {
264 stv0900_write_reg(intp
, R0900_TSGENERAL
, 0x0c);
265 for (i
= 0; i
< 32; i
++)
266 stv0900_write_reg(intp
, STV0900_Cut20_AddOnVal
[i
][0],
267 STV0900_Cut20_AddOnVal
[i
][1]);
270 stv0900_write_reg(intp
, R0900_P1_FSPYCFG
, 0x6c);
271 stv0900_write_reg(intp
, R0900_P2_FSPYCFG
, 0x6c);
273 stv0900_write_reg(intp
, R0900_P1_PDELCTRL2
, 0x01);
274 stv0900_write_reg(intp
, R0900_P2_PDELCTRL2
, 0x21);
276 stv0900_write_reg(intp
, R0900_P1_PDELCTRL3
, 0x20);
277 stv0900_write_reg(intp
, R0900_P2_PDELCTRL3
, 0x20);
279 stv0900_write_reg(intp
, R0900_TSTRES0
, 0x80);
280 stv0900_write_reg(intp
, R0900_TSTRES0
, 0x00);
282 return STV0900_NO_ERROR
;
285 u32
stv0900_get_mclk_freq(struct stv0900_internal
*intp
, u32 ext_clk
)
287 u32 mclk
= 90000000, div
= 0, ad_div
= 0;
289 div
= stv0900_get_bits(intp
, F0900_M_DIV
);
290 ad_div
= ((stv0900_get_bits(intp
, F0900_SELX1RATIO
) == 1) ? 4 : 6);
292 mclk
= (div
+ 1) * ext_clk
/ ad_div
;
294 dprintk("%s: Calculated Mclk = %d\n", __func__
, mclk
);
299 enum fe_stv0900_error
stv0900_set_mclk(struct stv0900_internal
*intp
, u32 mclk
)
303 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__
, mclk
,
307 return STV0900_INVALID_HANDLE
;
310 return STV0900_I2C_ERROR
;
312 clk_sel
= ((stv0900_get_bits(intp
, F0900_SELX1RATIO
) == 1) ? 4 : 6);
313 m_div
= ((clk_sel
* mclk
) / intp
->quartz
) - 1;
314 stv0900_write_bits(intp
, F0900_M_DIV
, m_div
);
315 intp
->mclk
= stv0900_get_mclk_freq(intp
,
318 /*Set the DiseqC frequency to 22KHz */
321 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
322 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
324 m_div
= intp
->mclk
/ 704000;
325 stv0900_write_reg(intp
, R0900_P1_F22TX
, m_div
);
326 stv0900_write_reg(intp
, R0900_P1_F22RX
, m_div
);
328 stv0900_write_reg(intp
, R0900_P2_F22TX
, m_div
);
329 stv0900_write_reg(intp
, R0900_P2_F22RX
, m_div
);
332 return STV0900_I2C_ERROR
;
334 return STV0900_NO_ERROR
;
337 u32
stv0900_get_err_count(struct stv0900_internal
*intp
, int cntr
,
338 enum fe_stv0900_demod_num demod
)
340 u32 lsb
, msb
, hsb
, err_val
;
345 hsb
= stv0900_get_bits(intp
, ERR_CNT12
);
346 msb
= stv0900_get_bits(intp
, ERR_CNT11
);
347 lsb
= stv0900_get_bits(intp
, ERR_CNT10
);
350 hsb
= stv0900_get_bits(intp
, ERR_CNT22
);
351 msb
= stv0900_get_bits(intp
, ERR_CNT21
);
352 lsb
= stv0900_get_bits(intp
, ERR_CNT20
);
356 err_val
= (hsb
<< 16) + (msb
<< 8) + (lsb
);
361 static int stv0900_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
363 struct stv0900_state
*state
= fe
->demodulator_priv
;
364 struct stv0900_internal
*intp
= state
->internal
;
365 enum fe_stv0900_demod_num demod
= state
->demod
;
367 stv0900_write_bits(intp
, I2CT_ON
, enable
);
372 static void stv0900_set_ts_parallel_serial(struct stv0900_internal
*intp
,
373 enum fe_stv0900_clock_type path1_ts
,
374 enum fe_stv0900_clock_type path2_ts
)
377 dprintk("%s\n", __func__
);
379 if (intp
->chip_id
>= 0x20) {
381 case STV0900_PARALLEL_PUNCT_CLOCK
:
382 case STV0900_DVBCI_CLOCK
:
384 case STV0900_SERIAL_PUNCT_CLOCK
:
385 case STV0900_SERIAL_CONT_CLOCK
:
387 stv0900_write_reg(intp
, R0900_TSGENERAL
,
390 case STV0900_PARALLEL_PUNCT_CLOCK
:
391 case STV0900_DVBCI_CLOCK
:
392 stv0900_write_reg(intp
, R0900_TSGENERAL
,
394 stv0900_write_bits(intp
,
395 F0900_P1_TSFIFO_MANSPEED
, 3);
396 stv0900_write_bits(intp
,
397 F0900_P2_TSFIFO_MANSPEED
, 0);
398 stv0900_write_reg(intp
,
399 R0900_P1_TSSPEED
, 0x14);
400 stv0900_write_reg(intp
,
401 R0900_P2_TSSPEED
, 0x28);
405 case STV0900_SERIAL_PUNCT_CLOCK
:
406 case STV0900_SERIAL_CONT_CLOCK
:
409 case STV0900_SERIAL_PUNCT_CLOCK
:
410 case STV0900_SERIAL_CONT_CLOCK
:
412 stv0900_write_reg(intp
,
413 R0900_TSGENERAL
, 0x0C);
415 case STV0900_PARALLEL_PUNCT_CLOCK
:
416 case STV0900_DVBCI_CLOCK
:
417 stv0900_write_reg(intp
,
418 R0900_TSGENERAL
, 0x0A);
419 dprintk("%s: 0x0a\n", __func__
);
426 case STV0900_PARALLEL_PUNCT_CLOCK
:
427 case STV0900_DVBCI_CLOCK
:
429 case STV0900_SERIAL_PUNCT_CLOCK
:
430 case STV0900_SERIAL_CONT_CLOCK
:
432 stv0900_write_reg(intp
, R0900_TSGENERAL1X
,
435 case STV0900_PARALLEL_PUNCT_CLOCK
:
436 case STV0900_DVBCI_CLOCK
:
437 stv0900_write_reg(intp
, R0900_TSGENERAL1X
,
439 stv0900_write_bits(intp
,
440 F0900_P1_TSFIFO_MANSPEED
, 3);
441 stv0900_write_bits(intp
,
442 F0900_P2_TSFIFO_MANSPEED
, 0);
443 stv0900_write_reg(intp
, R0900_P1_TSSPEED
,
445 stv0900_write_reg(intp
, R0900_P2_TSSPEED
,
451 case STV0900_SERIAL_PUNCT_CLOCK
:
452 case STV0900_SERIAL_CONT_CLOCK
:
455 case STV0900_SERIAL_PUNCT_CLOCK
:
456 case STV0900_SERIAL_CONT_CLOCK
:
458 stv0900_write_reg(intp
, R0900_TSGENERAL1X
,
461 case STV0900_PARALLEL_PUNCT_CLOCK
:
462 case STV0900_DVBCI_CLOCK
:
463 stv0900_write_reg(intp
, R0900_TSGENERAL1X
,
465 dprintk("%s: 0x12\n", __func__
);
474 case STV0900_PARALLEL_PUNCT_CLOCK
:
475 stv0900_write_bits(intp
, F0900_P1_TSFIFO_SERIAL
, 0x00);
476 stv0900_write_bits(intp
, F0900_P1_TSFIFO_DVBCI
, 0x00);
478 case STV0900_DVBCI_CLOCK
:
479 stv0900_write_bits(intp
, F0900_P1_TSFIFO_SERIAL
, 0x00);
480 stv0900_write_bits(intp
, F0900_P1_TSFIFO_DVBCI
, 0x01);
482 case STV0900_SERIAL_PUNCT_CLOCK
:
483 stv0900_write_bits(intp
, F0900_P1_TSFIFO_SERIAL
, 0x01);
484 stv0900_write_bits(intp
, F0900_P1_TSFIFO_DVBCI
, 0x00);
486 case STV0900_SERIAL_CONT_CLOCK
:
487 stv0900_write_bits(intp
, F0900_P1_TSFIFO_SERIAL
, 0x01);
488 stv0900_write_bits(intp
, F0900_P1_TSFIFO_DVBCI
, 0x01);
495 case STV0900_PARALLEL_PUNCT_CLOCK
:
496 stv0900_write_bits(intp
, F0900_P2_TSFIFO_SERIAL
, 0x00);
497 stv0900_write_bits(intp
, F0900_P2_TSFIFO_DVBCI
, 0x00);
499 case STV0900_DVBCI_CLOCK
:
500 stv0900_write_bits(intp
, F0900_P2_TSFIFO_SERIAL
, 0x00);
501 stv0900_write_bits(intp
, F0900_P2_TSFIFO_DVBCI
, 0x01);
503 case STV0900_SERIAL_PUNCT_CLOCK
:
504 stv0900_write_bits(intp
, F0900_P2_TSFIFO_SERIAL
, 0x01);
505 stv0900_write_bits(intp
, F0900_P2_TSFIFO_DVBCI
, 0x00);
507 case STV0900_SERIAL_CONT_CLOCK
:
508 stv0900_write_bits(intp
, F0900_P2_TSFIFO_SERIAL
, 0x01);
509 stv0900_write_bits(intp
, F0900_P2_TSFIFO_DVBCI
, 0x01);
515 stv0900_write_bits(intp
, F0900_P2_RST_HWARE
, 1);
516 stv0900_write_bits(intp
, F0900_P2_RST_HWARE
, 0);
517 stv0900_write_bits(intp
, F0900_P1_RST_HWARE
, 1);
518 stv0900_write_bits(intp
, F0900_P1_RST_HWARE
, 0);
521 void stv0900_set_tuner(struct dvb_frontend
*fe
, u32 frequency
,
524 struct dvb_frontend_ops
*frontend_ops
= NULL
;
525 struct dvb_tuner_ops
*tuner_ops
= NULL
;
528 frontend_ops
= &fe
->ops
;
530 if (&frontend_ops
->tuner_ops
)
531 tuner_ops
= &frontend_ops
->tuner_ops
;
533 if (tuner_ops
->set_frequency
) {
534 if ((tuner_ops
->set_frequency(fe
, frequency
)) < 0)
535 dprintk("%s: Invalid parameter\n", __func__
);
537 dprintk("%s: Frequency=%d\n", __func__
, frequency
);
541 if (tuner_ops
->set_bandwidth
) {
542 if ((tuner_ops
->set_bandwidth(fe
, bandwidth
)) < 0)
543 dprintk("%s: Invalid parameter\n", __func__
);
545 dprintk("%s: Bandwidth=%d\n", __func__
, bandwidth
);
550 void stv0900_set_bandwidth(struct dvb_frontend
*fe
, u32 bandwidth
)
552 struct dvb_frontend_ops
*frontend_ops
= NULL
;
553 struct dvb_tuner_ops
*tuner_ops
= NULL
;
556 frontend_ops
= &fe
->ops
;
558 if (&frontend_ops
->tuner_ops
)
559 tuner_ops
= &frontend_ops
->tuner_ops
;
561 if (tuner_ops
->set_bandwidth
) {
562 if ((tuner_ops
->set_bandwidth(fe
, bandwidth
)) < 0)
563 dprintk("%s: Invalid parameter\n", __func__
);
565 dprintk("%s: Bandwidth=%d\n", __func__
, bandwidth
);
570 static s32
stv0900_get_rf_level(struct stv0900_internal
*intp
,
571 const struct stv0900_table
*lookup
,
572 enum fe_stv0900_demod_num demod
)
580 dprintk("%s\n", __func__
);
582 if ((lookup
== NULL
) || (lookup
->size
<= 0))
585 agc_gain
= MAKEWORD(stv0900_get_bits(intp
, AGCIQ_VALUE1
),
586 stv0900_get_bits(intp
, AGCIQ_VALUE0
));
589 imax
= lookup
->size
- 1;
590 if (INRANGE(lookup
->table
[imin
].regval
, agc_gain
,
591 lookup
->table
[imax
].regval
)) {
592 while ((imax
- imin
) > 1) {
593 i
= (imax
+ imin
) >> 1;
595 if (INRANGE(lookup
->table
[imin
].regval
,
597 lookup
->table
[i
].regval
))
603 rf_lvl
= (s32
)agc_gain
- lookup
->table
[imin
].regval
;
604 rf_lvl
*= (lookup
->table
[imax
].realval
-
605 lookup
->table
[imin
].realval
);
606 rf_lvl
/= (lookup
->table
[imax
].regval
-
607 lookup
->table
[imin
].regval
);
608 rf_lvl
+= lookup
->table
[imin
].realval
;
609 } else if (agc_gain
> lookup
->table
[0].regval
)
611 else if (agc_gain
< lookup
->table
[lookup
->size
-1].regval
)
614 dprintk("%s: RFLevel = %d\n", __func__
, rf_lvl
);
619 static int stv0900_read_signal_strength(struct dvb_frontend
*fe
, u16
*strength
)
621 struct stv0900_state
*state
= fe
->demodulator_priv
;
622 struct stv0900_internal
*internal
= state
->internal
;
623 s32 rflevel
= stv0900_get_rf_level(internal
, &stv0900_rf
,
626 rflevel
= (rflevel
+ 100) * (65535 / 70);
638 static s32
stv0900_carr_get_quality(struct dvb_frontend
*fe
,
639 const struct stv0900_table
*lookup
)
641 struct stv0900_state
*state
= fe
->demodulator_priv
;
642 struct stv0900_internal
*intp
= state
->internal
;
643 enum fe_stv0900_demod_num demod
= state
->demod
;
653 dprintk("%s\n", __func__
);
655 if (stv0900_get_standard(fe
, demod
) == STV0900_DVBS2_STANDARD
) {
656 noise_field1
= NOSPLHT_NORMED1
;
657 noise_field0
= NOSPLHT_NORMED0
;
659 noise_field1
= NOSDATAT_NORMED1
;
660 noise_field0
= NOSDATAT_NORMED0
;
663 if (stv0900_get_bits(intp
, LOCK_DEFINITIF
)) {
664 if ((lookup
!= NULL
) && lookup
->size
) {
667 for (i
= 0; i
< 16; i
++) {
668 regval
+= MAKEWORD(stv0900_get_bits(intp
,
670 stv0900_get_bits(intp
,
677 imax
= lookup
->size
- 1;
678 if (INRANGE(lookup
->table
[imin
].regval
,
680 lookup
->table
[imax
].regval
)) {
681 while ((imax
- imin
) > 1) {
682 i
= (imax
+ imin
) >> 1;
683 if (INRANGE(lookup
->table
[imin
].regval
,
685 lookup
->table
[i
].regval
))
691 c_n
= ((regval
- lookup
->table
[imin
].regval
)
692 * (lookup
->table
[imax
].realval
693 - lookup
->table
[imin
].realval
)
694 / (lookup
->table
[imax
].regval
695 - lookup
->table
[imin
].regval
))
696 + lookup
->table
[imin
].realval
;
697 } else if (regval
< lookup
->table
[imin
].regval
)
705 static int stv0900_read_ucblocks(struct dvb_frontend
*fe
, u32
* ucblocks
)
707 struct stv0900_state
*state
= fe
->demodulator_priv
;
708 struct stv0900_internal
*intp
= state
->internal
;
709 enum fe_stv0900_demod_num demod
= state
->demod
;
710 u8 err_val1
, err_val0
;
711 u32 header_err_val
= 0;
714 if (stv0900_get_standard(fe
, demod
) == STV0900_DVBS2_STANDARD
) {
715 /* DVB-S2 delineator errors count */
717 /* retreiving number for errnous headers */
718 err_val1
= stv0900_read_reg(intp
, BBFCRCKO1
);
719 err_val0
= stv0900_read_reg(intp
, BBFCRCKO0
);
720 header_err_val
= (err_val1
<< 8) | err_val0
;
722 /* retreiving number for errnous packets */
723 err_val1
= stv0900_read_reg(intp
, UPCRCKO1
);
724 err_val0
= stv0900_read_reg(intp
, UPCRCKO0
);
725 *ucblocks
= (err_val1
<< 8) | err_val0
;
726 *ucblocks
+= header_err_val
;
732 static int stv0900_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
734 s32 snrlcl
= stv0900_carr_get_quality(fe
,
735 (const struct stv0900_table
*)&stv0900_s2_cn
);
736 snrlcl
= (snrlcl
+ 30) * 384;
748 static u32
stv0900_get_ber(struct stv0900_internal
*intp
,
749 enum fe_stv0900_demod_num demod
)
751 u32 ber
= 10000000, i
;
754 demod_state
= stv0900_get_bits(intp
, HEADER_MODE
);
756 switch (demod_state
) {
758 case STV0900_PLH_DETECTED
:
762 case STV0900_DVBS_FOUND
:
764 for (i
= 0; i
< 5; i
++) {
766 ber
+= stv0900_get_err_count(intp
, 0, demod
);
770 if (stv0900_get_bits(intp
, PRFVIT
)) {
776 case STV0900_DVBS2_FOUND
:
778 for (i
= 0; i
< 5; i
++) {
780 ber
+= stv0900_get_err_count(intp
, 0, demod
);
784 if (stv0900_get_bits(intp
, PKTDELIN_LOCK
)) {
795 static int stv0900_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
797 struct stv0900_state
*state
= fe
->demodulator_priv
;
798 struct stv0900_internal
*internal
= state
->internal
;
800 *ber
= stv0900_get_ber(internal
, state
->demod
);
805 int stv0900_get_demod_lock(struct stv0900_internal
*intp
,
806 enum fe_stv0900_demod_num demod
, s32 time_out
)
811 enum fe_stv0900_search_state dmd_state
;
813 while ((timer
< time_out
) && (lock
== 0)) {
814 dmd_state
= stv0900_get_bits(intp
, HEADER_MODE
);
815 dprintk("Demod State = %d\n", dmd_state
);
818 case STV0900_PLH_DETECTED
:
822 case STV0900_DVBS2_FOUND
:
823 case STV0900_DVBS_FOUND
:
824 lock
= stv0900_get_bits(intp
, LOCK_DEFINITIF
);
835 dprintk("DEMOD LOCK OK\n");
837 dprintk("DEMOD LOCK FAIL\n");
842 void stv0900_stop_all_s2_modcod(struct stv0900_internal
*intp
,
843 enum fe_stv0900_demod_num demod
)
848 dprintk("%s\n", __func__
);
850 regflist
= MODCODLST0
;
852 for (i
= 0; i
< 16; i
++)
853 stv0900_write_reg(intp
, regflist
+ i
, 0xff);
856 void stv0900_activate_s2_modcod(struct stv0900_internal
*intp
,
857 enum fe_stv0900_demod_num demod
)
865 dprintk("%s\n", __func__
);
867 if (intp
->chip_id
<= 0x11) {
870 mod_code
= stv0900_read_reg(intp
, PLHMODCOD
);
871 matype
= mod_code
& 0x3;
872 mod_code
= (mod_code
& 0x7f) >> 2;
874 reg_index
= MODCODLSTF
- mod_code
/ 2;
875 field_index
= mod_code
% 2;
893 if ((INRANGE(STV0900_QPSK_12
, mod_code
, STV0900_8PSK_910
))
895 if (field_index
== 0)
896 stv0900_write_reg(intp
, reg_index
,
899 stv0900_write_reg(intp
, reg_index
,
903 } else if (intp
->chip_id
>= 0x12) {
904 for (reg_index
= 0; reg_index
< 7; reg_index
++)
905 stv0900_write_reg(intp
, MODCODLST0
+ reg_index
, 0xff);
907 stv0900_write_reg(intp
, MODCODLSTE
, 0xff);
908 stv0900_write_reg(intp
, MODCODLSTF
, 0xcf);
909 for (reg_index
= 0; reg_index
< 8; reg_index
++)
910 stv0900_write_reg(intp
, MODCODLST7
+ reg_index
, 0xcc);
916 void stv0900_activate_s2_modcod_single(struct stv0900_internal
*intp
,
917 enum fe_stv0900_demod_num demod
)
921 dprintk("%s\n", __func__
);
923 stv0900_write_reg(intp
, MODCODLST0
, 0xff);
924 stv0900_write_reg(intp
, MODCODLST1
, 0xf0);
925 stv0900_write_reg(intp
, MODCODLSTF
, 0x0f);
926 for (reg_index
= 0; reg_index
< 13; reg_index
++)
927 stv0900_write_reg(intp
, MODCODLST2
+ reg_index
, 0);
931 static enum dvbfe_algo
stv0900_frontend_algo(struct dvb_frontend
*fe
)
933 return DVBFE_ALGO_CUSTOM
;
936 static int stb0900_set_property(struct dvb_frontend
*fe
,
937 struct dtv_property
*tvp
)
939 dprintk("%s(..)\n", __func__
);
944 static int stb0900_get_property(struct dvb_frontend
*fe
,
945 struct dtv_property
*tvp
)
947 dprintk("%s(..)\n", __func__
);
952 void stv0900_start_search(struct stv0900_internal
*intp
,
953 enum fe_stv0900_demod_num demod
)
958 stv0900_write_bits(intp
, DEMOD_MODE
, 0x1f);
959 if (intp
->chip_id
== 0x10)
960 stv0900_write_reg(intp
, CORRELEXP
, 0xaa);
962 if (intp
->chip_id
< 0x20)
963 stv0900_write_reg(intp
, CARHDR
, 0x55);
965 if (intp
->chip_id
<= 0x20) {
966 if (intp
->symbol_rate
[0] <= 5000000) {
967 stv0900_write_reg(intp
, CARCFG
, 0x44);
968 stv0900_write_reg(intp
, CFRUP1
, 0x0f);
969 stv0900_write_reg(intp
, CFRUP0
, 0xff);
970 stv0900_write_reg(intp
, CFRLOW1
, 0xf0);
971 stv0900_write_reg(intp
, CFRLOW0
, 0x00);
972 stv0900_write_reg(intp
, RTCS2
, 0x68);
974 stv0900_write_reg(intp
, CARCFG
, 0xc4);
975 stv0900_write_reg(intp
, RTCS2
, 0x44);
978 } else { /*cut 3.0 above*/
979 if (intp
->symbol_rate
[demod
] <= 5000000)
980 stv0900_write_reg(intp
, RTCS2
, 0x68);
982 stv0900_write_reg(intp
, RTCS2
, 0x44);
984 stv0900_write_reg(intp
, CARCFG
, 0x46);
985 if (intp
->srch_algo
[demod
] == STV0900_WARM_START
) {
987 freq
/= (intp
->mclk
/ 1000);
988 freq_s16
= (s16
)freq
;
990 freq
= (intp
->srch_range
[demod
] / 2000);
991 if (intp
->symbol_rate
[demod
] <= 5000000)
997 freq
/= (intp
->mclk
/ 1000);
998 freq_s16
= (s16
)freq
;
1001 stv0900_write_bits(intp
, CFR_UP1
, MSB(freq_s16
));
1002 stv0900_write_bits(intp
, CFR_UP0
, LSB(freq_s16
));
1004 stv0900_write_bits(intp
, CFR_LOW1
, MSB(freq_s16
));
1005 stv0900_write_bits(intp
, CFR_LOW0
, LSB(freq_s16
));
1008 stv0900_write_reg(intp
, CFRINIT1
, 0);
1009 stv0900_write_reg(intp
, CFRINIT0
, 0);
1011 if (intp
->chip_id
>= 0x20) {
1012 stv0900_write_reg(intp
, EQUALCFG
, 0x41);
1013 stv0900_write_reg(intp
, FFECFG
, 0x41);
1015 if ((intp
->srch_standard
[demod
] == STV0900_SEARCH_DVBS1
) ||
1016 (intp
->srch_standard
[demod
] == STV0900_SEARCH_DSS
) ||
1017 (intp
->srch_standard
[demod
] == STV0900_AUTO_SEARCH
)) {
1018 stv0900_write_reg(intp
, VITSCALE
,
1020 stv0900_write_reg(intp
, VAVSRVIT
, 0x0);
1024 stv0900_write_reg(intp
, SFRSTEP
, 0x00);
1025 stv0900_write_reg(intp
, TMGTHRISE
, 0xe0);
1026 stv0900_write_reg(intp
, TMGTHFALL
, 0xc0);
1027 stv0900_write_bits(intp
, SCAN_ENABLE
, 0);
1028 stv0900_write_bits(intp
, CFR_AUTOSCAN
, 0);
1029 stv0900_write_bits(intp
, S1S2_SEQUENTIAL
, 0);
1030 stv0900_write_reg(intp
, RTC
, 0x88);
1031 if (intp
->chip_id
>= 0x20) {
1032 if (intp
->symbol_rate
[demod
] < 2000000) {
1033 if (intp
->chip_id
<= 0x20)
1034 stv0900_write_reg(intp
, CARFREQ
, 0x39);
1036 stv0900_write_reg(intp
, CARFREQ
, 0x89);
1038 stv0900_write_reg(intp
, CARHDR
, 0x40);
1039 } else if (intp
->symbol_rate
[demod
] < 10000000) {
1040 stv0900_write_reg(intp
, CARFREQ
, 0x4c);
1041 stv0900_write_reg(intp
, CARHDR
, 0x20);
1043 stv0900_write_reg(intp
, CARFREQ
, 0x4b);
1044 stv0900_write_reg(intp
, CARHDR
, 0x20);
1048 if (intp
->symbol_rate
[demod
] < 10000000)
1049 stv0900_write_reg(intp
, CARFREQ
, 0xef);
1051 stv0900_write_reg(intp
, CARFREQ
, 0xed);
1054 switch (intp
->srch_algo
[demod
]) {
1055 case STV0900_WARM_START
:
1056 stv0900_write_reg(intp
, DMDISTATE
, 0x1f);
1057 stv0900_write_reg(intp
, DMDISTATE
, 0x18);
1059 case STV0900_COLD_START
:
1060 stv0900_write_reg(intp
, DMDISTATE
, 0x1f);
1061 stv0900_write_reg(intp
, DMDISTATE
, 0x15);
1068 u8
stv0900_get_optim_carr_loop(s32 srate
, enum fe_stv0900_modcode modcode
,
1069 s32 pilot
, u8 chip_id
)
1071 u8 aclc_value
= 0x29;
1073 const struct stv0900_car_loop_optim
*cls2
, *cllqs2
, *cllas2
;
1075 dprintk("%s\n", __func__
);
1077 if (chip_id
<= 0x12) {
1078 cls2
= FE_STV0900_S2CarLoop
;
1079 cllqs2
= FE_STV0900_S2LowQPCarLoopCut30
;
1080 cllas2
= FE_STV0900_S2APSKCarLoopCut30
;
1081 } else if (chip_id
== 0x20) {
1082 cls2
= FE_STV0900_S2CarLoopCut20
;
1083 cllqs2
= FE_STV0900_S2LowQPCarLoopCut20
;
1084 cllas2
= FE_STV0900_S2APSKCarLoopCut20
;
1086 cls2
= FE_STV0900_S2CarLoopCut30
;
1087 cllqs2
= FE_STV0900_S2LowQPCarLoopCut30
;
1088 cllas2
= FE_STV0900_S2APSKCarLoopCut30
;
1091 if (modcode
< STV0900_QPSK_12
) {
1093 while ((i
< 3) && (modcode
!= cllqs2
[i
].modcode
))
1100 while ((i
< 14) && (modcode
!= cls2
[i
].modcode
))
1105 while ((i
< 11) && (modcode
!= cllas2
[i
].modcode
))
1113 if (modcode
<= STV0900_QPSK_25
) {
1115 if (srate
<= 3000000)
1116 aclc_value
= cllqs2
[i
].car_loop_pilots_on_2
;
1117 else if (srate
<= 7000000)
1118 aclc_value
= cllqs2
[i
].car_loop_pilots_on_5
;
1119 else if (srate
<= 15000000)
1120 aclc_value
= cllqs2
[i
].car_loop_pilots_on_10
;
1121 else if (srate
<= 25000000)
1122 aclc_value
= cllqs2
[i
].car_loop_pilots_on_20
;
1124 aclc_value
= cllqs2
[i
].car_loop_pilots_on_30
;
1126 if (srate
<= 3000000)
1127 aclc_value
= cllqs2
[i
].car_loop_pilots_off_2
;
1128 else if (srate
<= 7000000)
1129 aclc_value
= cllqs2
[i
].car_loop_pilots_off_5
;
1130 else if (srate
<= 15000000)
1131 aclc_value
= cllqs2
[i
].car_loop_pilots_off_10
;
1132 else if (srate
<= 25000000)
1133 aclc_value
= cllqs2
[i
].car_loop_pilots_off_20
;
1135 aclc_value
= cllqs2
[i
].car_loop_pilots_off_30
;
1138 } else if (modcode
<= STV0900_8PSK_910
) {
1140 if (srate
<= 3000000)
1141 aclc_value
= cls2
[i
].car_loop_pilots_on_2
;
1142 else if (srate
<= 7000000)
1143 aclc_value
= cls2
[i
].car_loop_pilots_on_5
;
1144 else if (srate
<= 15000000)
1145 aclc_value
= cls2
[i
].car_loop_pilots_on_10
;
1146 else if (srate
<= 25000000)
1147 aclc_value
= cls2
[i
].car_loop_pilots_on_20
;
1149 aclc_value
= cls2
[i
].car_loop_pilots_on_30
;
1151 if (srate
<= 3000000)
1152 aclc_value
= cls2
[i
].car_loop_pilots_off_2
;
1153 else if (srate
<= 7000000)
1154 aclc_value
= cls2
[i
].car_loop_pilots_off_5
;
1155 else if (srate
<= 15000000)
1156 aclc_value
= cls2
[i
].car_loop_pilots_off_10
;
1157 else if (srate
<= 25000000)
1158 aclc_value
= cls2
[i
].car_loop_pilots_off_20
;
1160 aclc_value
= cls2
[i
].car_loop_pilots_off_30
;
1164 if (srate
<= 3000000)
1165 aclc_value
= cllas2
[i
].car_loop_pilots_on_2
;
1166 else if (srate
<= 7000000)
1167 aclc_value
= cllas2
[i
].car_loop_pilots_on_5
;
1168 else if (srate
<= 15000000)
1169 aclc_value
= cllas2
[i
].car_loop_pilots_on_10
;
1170 else if (srate
<= 25000000)
1171 aclc_value
= cllas2
[i
].car_loop_pilots_on_20
;
1173 aclc_value
= cllas2
[i
].car_loop_pilots_on_30
;
1179 u8
stv0900_get_optim_short_carr_loop(s32 srate
,
1180 enum fe_stv0900_modulation modulation
,
1183 const struct stv0900_short_frames_car_loop_optim
*s2scl
;
1184 const struct stv0900_short_frames_car_loop_optim_vs_mod
*s2sclc30
;
1186 u8 aclc_value
= 0x0b;
1188 dprintk("%s\n", __func__
);
1190 s2scl
= FE_STV0900_S2ShortCarLoop
;
1191 s2sclc30
= FE_STV0900_S2ShortCarLoopCut30
;
1193 switch (modulation
) {
1201 case STV0900_16APSK
:
1204 case STV0900_32APSK
:
1209 if (chip_id
>= 0x30) {
1210 if (srate
<= 3000000)
1211 aclc_value
= s2sclc30
[mod_index
].car_loop_2
;
1212 else if (srate
<= 7000000)
1213 aclc_value
= s2sclc30
[mod_index
].car_loop_5
;
1214 else if (srate
<= 15000000)
1215 aclc_value
= s2sclc30
[mod_index
].car_loop_10
;
1216 else if (srate
<= 25000000)
1217 aclc_value
= s2sclc30
[mod_index
].car_loop_20
;
1219 aclc_value
= s2sclc30
[mod_index
].car_loop_30
;
1221 } else if (chip_id
>= 0x20) {
1222 if (srate
<= 3000000)
1223 aclc_value
= s2scl
[mod_index
].car_loop_cut20_2
;
1224 else if (srate
<= 7000000)
1225 aclc_value
= s2scl
[mod_index
].car_loop_cut20_5
;
1226 else if (srate
<= 15000000)
1227 aclc_value
= s2scl
[mod_index
].car_loop_cut20_10
;
1228 else if (srate
<= 25000000)
1229 aclc_value
= s2scl
[mod_index
].car_loop_cut20_20
;
1231 aclc_value
= s2scl
[mod_index
].car_loop_cut20_30
;
1234 if (srate
<= 3000000)
1235 aclc_value
= s2scl
[mod_index
].car_loop_cut12_2
;
1236 else if (srate
<= 7000000)
1237 aclc_value
= s2scl
[mod_index
].car_loop_cut12_5
;
1238 else if (srate
<= 15000000)
1239 aclc_value
= s2scl
[mod_index
].car_loop_cut12_10
;
1240 else if (srate
<= 25000000)
1241 aclc_value
= s2scl
[mod_index
].car_loop_cut12_20
;
1243 aclc_value
= s2scl
[mod_index
].car_loop_cut12_30
;
1251 enum fe_stv0900_error
stv0900_st_dvbs2_single(struct stv0900_internal
*intp
,
1252 enum fe_stv0900_demod_mode LDPC_Mode
,
1253 enum fe_stv0900_demod_num demod
)
1255 enum fe_stv0900_error error
= STV0900_NO_ERROR
;
1258 dprintk("%s\n", __func__
);
1260 switch (LDPC_Mode
) {
1263 if ((intp
->demod_mode
!= STV0900_DUAL
)
1264 || (stv0900_get_bits(intp
, F0900_DDEMOD
) != 1)) {
1265 stv0900_write_reg(intp
, R0900_GENCFG
, 0x1d);
1267 intp
->demod_mode
= STV0900_DUAL
;
1269 stv0900_write_bits(intp
, F0900_FRESFEC
, 1);
1270 stv0900_write_bits(intp
, F0900_FRESFEC
, 0);
1272 for (reg_ind
= 0; reg_ind
< 7; reg_ind
++)
1273 stv0900_write_reg(intp
,
1274 R0900_P1_MODCODLST0
+ reg_ind
,
1276 for (reg_ind
= 0; reg_ind
< 8; reg_ind
++)
1277 stv0900_write_reg(intp
,
1278 R0900_P1_MODCODLST7
+ reg_ind
,
1281 stv0900_write_reg(intp
, R0900_P1_MODCODLSTE
, 0xff);
1282 stv0900_write_reg(intp
, R0900_P1_MODCODLSTF
, 0xcf);
1284 for (reg_ind
= 0; reg_ind
< 7; reg_ind
++)
1285 stv0900_write_reg(intp
,
1286 R0900_P2_MODCODLST0
+ reg_ind
,
1288 for (reg_ind
= 0; reg_ind
< 8; reg_ind
++)
1289 stv0900_write_reg(intp
,
1290 R0900_P2_MODCODLST7
+ reg_ind
,
1293 stv0900_write_reg(intp
, R0900_P2_MODCODLSTE
, 0xff);
1294 stv0900_write_reg(intp
, R0900_P2_MODCODLSTF
, 0xcf);
1298 case STV0900_SINGLE
:
1299 if (demod
== STV0900_DEMOD_2
) {
1300 stv0900_stop_all_s2_modcod(intp
, STV0900_DEMOD_1
);
1301 stv0900_activate_s2_modcod_single(intp
,
1303 stv0900_write_reg(intp
, R0900_GENCFG
, 0x06);
1305 stv0900_stop_all_s2_modcod(intp
, STV0900_DEMOD_2
);
1306 stv0900_activate_s2_modcod_single(intp
,
1308 stv0900_write_reg(intp
, R0900_GENCFG
, 0x04);
1311 intp
->demod_mode
= STV0900_SINGLE
;
1313 stv0900_write_bits(intp
, F0900_FRESFEC
, 1);
1314 stv0900_write_bits(intp
, F0900_FRESFEC
, 0);
1315 stv0900_write_bits(intp
, F0900_P1_ALGOSWRST
, 1);
1316 stv0900_write_bits(intp
, F0900_P1_ALGOSWRST
, 0);
1317 stv0900_write_bits(intp
, F0900_P2_ALGOSWRST
, 1);
1318 stv0900_write_bits(intp
, F0900_P2_ALGOSWRST
, 0);
1325 static enum fe_stv0900_error
stv0900_init_internal(struct dvb_frontend
*fe
,
1326 struct stv0900_init_params
*p_init
)
1328 struct stv0900_state
*state
= fe
->demodulator_priv
;
1329 enum fe_stv0900_error error
= STV0900_NO_ERROR
;
1330 enum fe_stv0900_error demodError
= STV0900_NO_ERROR
;
1331 struct stv0900_internal
*intp
= NULL
;
1335 struct stv0900_inode
*temp_int
= find_inode(state
->i2c_adap
,
1336 state
->config
->demod_address
);
1338 dprintk("%s\n", __func__
);
1340 if ((temp_int
!= NULL
) && (p_init
->demod_mode
== STV0900_DUAL
)) {
1341 state
->internal
= temp_int
->internal
;
1342 (state
->internal
->dmds_used
)++;
1343 dprintk("%s: Find Internal Structure!\n", __func__
);
1344 return STV0900_NO_ERROR
;
1346 state
->internal
= kmalloc(sizeof(struct stv0900_internal
),
1348 temp_int
= append_internal(state
->internal
);
1349 state
->internal
->dmds_used
= 1;
1350 state
->internal
->i2c_adap
= state
->i2c_adap
;
1351 state
->internal
->i2c_addr
= state
->config
->demod_address
;
1352 state
->internal
->clkmode
= state
->config
->clkmode
;
1353 state
->internal
->errs
= STV0900_NO_ERROR
;
1354 dprintk("%s: Create New Internal Structure!\n", __func__
);
1357 if (state
->internal
== NULL
) {
1358 error
= STV0900_INVALID_HANDLE
;
1362 demodError
= stv0900_initialize(state
->internal
);
1363 if (demodError
== STV0900_NO_ERROR
) {
1364 error
= STV0900_NO_ERROR
;
1366 if (demodError
== STV0900_INVALID_HANDLE
)
1367 error
= STV0900_INVALID_HANDLE
;
1369 error
= STV0900_I2C_ERROR
;
1374 if (state
->internal
== NULL
) {
1375 error
= STV0900_INVALID_HANDLE
;
1379 intp
= state
->internal
;
1381 intp
->demod_mode
= p_init
->demod_mode
;
1382 stv0900_st_dvbs2_single(intp
, intp
->demod_mode
, STV0900_DEMOD_1
);
1383 intp
->chip_id
= stv0900_read_reg(intp
, R0900_MID
);
1384 intp
->rolloff
= p_init
->rolloff
;
1385 intp
->quartz
= p_init
->dmd_ref_clk
;
1387 stv0900_write_bits(intp
, F0900_P1_ROLLOFF_CONTROL
, p_init
->rolloff
);
1388 stv0900_write_bits(intp
, F0900_P2_ROLLOFF_CONTROL
, p_init
->rolloff
);
1390 intp
->ts_config
= p_init
->ts_config
;
1391 if (intp
->ts_config
== NULL
)
1392 stv0900_set_ts_parallel_serial(intp
,
1393 p_init
->path1_ts_clock
,
1394 p_init
->path2_ts_clock
);
1396 for (i
= 0; intp
->ts_config
[i
].addr
!= 0xffff; i
++)
1397 stv0900_write_reg(intp
,
1398 intp
->ts_config
[i
].addr
,
1399 intp
->ts_config
[i
].val
);
1401 stv0900_write_bits(intp
, F0900_P2_RST_HWARE
, 1);
1402 stv0900_write_bits(intp
, F0900_P2_RST_HWARE
, 0);
1403 stv0900_write_bits(intp
, F0900_P1_RST_HWARE
, 1);
1404 stv0900_write_bits(intp
, F0900_P1_RST_HWARE
, 0);
1407 stv0900_write_bits(intp
, F0900_P1_TUN_MADDRESS
, p_init
->tun1_maddress
);
1408 switch (p_init
->tuner1_adc
) {
1410 stv0900_write_reg(intp
, R0900_TSTTNR1
, 0x26);
1416 stv0900_write_bits(intp
, F0900_P2_TUN_MADDRESS
, p_init
->tun2_maddress
);
1417 switch (p_init
->tuner2_adc
) {
1419 stv0900_write_reg(intp
, R0900_TSTTNR3
, 0x26);
1425 stv0900_write_bits(intp
, F0900_P1_TUN_IQSWAP
, p_init
->tun1_iq_inv
);
1426 stv0900_write_bits(intp
, F0900_P2_TUN_IQSWAP
, p_init
->tun2_iq_inv
);
1427 stv0900_set_mclk(intp
, 135000000);
1430 switch (intp
->clkmode
) {
1433 stv0900_write_reg(intp
, R0900_SYNTCTRL
, 0x20 | intp
->clkmode
);
1436 selosci
= 0x02 & stv0900_read_reg(intp
, R0900_SYNTCTRL
);
1437 stv0900_write_reg(intp
, R0900_SYNTCTRL
, 0x20 | selosci
);
1442 intp
->mclk
= stv0900_get_mclk_freq(intp
, intp
->quartz
);
1444 error
= STV0900_I2C_ERROR
;
1449 static int stv0900_status(struct stv0900_internal
*intp
,
1450 enum fe_stv0900_demod_num demod
)
1452 enum fe_stv0900_search_state demod_state
;
1454 u8 tsbitrate0_val
, tsbitrate1_val
;
1457 demod_state
= stv0900_get_bits(intp
, HEADER_MODE
);
1458 switch (demod_state
) {
1459 case STV0900_SEARCH
:
1460 case STV0900_PLH_DETECTED
:
1464 case STV0900_DVBS2_FOUND
:
1465 locked
= stv0900_get_bits(intp
, LOCK_DEFINITIF
) &&
1466 stv0900_get_bits(intp
, PKTDELIN_LOCK
) &&
1467 stv0900_get_bits(intp
, TSFIFO_LINEOK
);
1469 case STV0900_DVBS_FOUND
:
1470 locked
= stv0900_get_bits(intp
, LOCK_DEFINITIF
) &&
1471 stv0900_get_bits(intp
, LOCKEDVIT
) &&
1472 stv0900_get_bits(intp
, TSFIFO_LINEOK
);
1476 dprintk("%s: locked = %d\n", __func__
, locked
);
1479 /* Print TS bitrate */
1480 tsbitrate0_val
= stv0900_read_reg(intp
, TSBITRATE0
);
1481 tsbitrate1_val
= stv0900_read_reg(intp
, TSBITRATE1
);
1482 /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */
1483 bitrate
= (stv0900_get_mclk_freq(intp
, intp
->quartz
)/1000000)
1484 * (tsbitrate1_val
<< 8 | tsbitrate0_val
);
1486 dprintk("TS bitrate = %d Mbit/sec \n", bitrate
);
1492 static enum dvbfe_search
stv0900_search(struct dvb_frontend
*fe
,
1493 struct dvb_frontend_parameters
*params
)
1495 struct stv0900_state
*state
= fe
->demodulator_priv
;
1496 struct stv0900_internal
*intp
= state
->internal
;
1497 enum fe_stv0900_demod_num demod
= state
->demod
;
1498 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
1500 struct stv0900_search_params p_search
;
1501 struct stv0900_signal_info p_result
;
1503 enum fe_stv0900_error error
= STV0900_NO_ERROR
;
1505 dprintk("%s: ", __func__
);
1507 if (!(INRANGE(100000, c
->symbol_rate
, 70000000)))
1508 return DVBFE_ALGO_SEARCH_FAILED
;
1510 if (state
->config
->set_ts_params
)
1511 state
->config
->set_ts_params(fe
, 0);
1513 p_result
.locked
= FALSE
;
1514 p_search
.path
= demod
;
1515 p_search
.frequency
= c
->frequency
;
1516 p_search
.symbol_rate
= c
->symbol_rate
;
1517 p_search
.search_range
= 10000000;
1518 p_search
.fec
= STV0900_FEC_UNKNOWN
;
1519 p_search
.standard
= STV0900_AUTO_SEARCH
;
1520 p_search
.iq_inversion
= STV0900_IQ_AUTO
;
1521 p_search
.search_algo
= STV0900_BLIND_SEARCH
;
1523 intp
->srch_standard
[demod
] = p_search
.standard
;
1524 intp
->symbol_rate
[demod
] = p_search
.symbol_rate
;
1525 intp
->srch_range
[demod
] = p_search
.search_range
;
1526 intp
->freq
[demod
] = p_search
.frequency
;
1527 intp
->srch_algo
[demod
] = p_search
.search_algo
;
1528 intp
->srch_iq_inv
[demod
] = p_search
.iq_inversion
;
1529 intp
->fec
[demod
] = p_search
.fec
;
1530 if ((stv0900_algo(fe
) == STV0900_RANGEOK
) &&
1531 (intp
->errs
== STV0900_NO_ERROR
)) {
1532 p_result
.locked
= intp
->result
[demod
].locked
;
1533 p_result
.standard
= intp
->result
[demod
].standard
;
1534 p_result
.frequency
= intp
->result
[demod
].frequency
;
1535 p_result
.symbol_rate
= intp
->result
[demod
].symbol_rate
;
1536 p_result
.fec
= intp
->result
[demod
].fec
;
1537 p_result
.modcode
= intp
->result
[demod
].modcode
;
1538 p_result
.pilot
= intp
->result
[demod
].pilot
;
1539 p_result
.frame_len
= intp
->result
[demod
].frame_len
;
1540 p_result
.spectrum
= intp
->result
[demod
].spectrum
;
1541 p_result
.rolloff
= intp
->result
[demod
].rolloff
;
1542 p_result
.modulation
= intp
->result
[demod
].modulation
;
1544 p_result
.locked
= FALSE
;
1545 switch (intp
->err
[demod
]) {
1546 case STV0900_I2C_ERROR
:
1547 error
= STV0900_I2C_ERROR
;
1549 case STV0900_NO_ERROR
:
1551 error
= STV0900_SEARCH_FAILED
;
1556 if ((p_result
.locked
== TRUE
) && (error
== STV0900_NO_ERROR
)) {
1557 dprintk("Search Success\n");
1558 return DVBFE_ALGO_SEARCH_SUCCESS
;
1560 dprintk("Search Fail\n");
1561 return DVBFE_ALGO_SEARCH_FAILED
;
1566 static int stv0900_read_status(struct dvb_frontend
*fe
, enum fe_status
*status
)
1568 struct stv0900_state
*state
= fe
->demodulator_priv
;
1570 dprintk("%s: ", __func__
);
1572 if ((stv0900_status(state
->internal
, state
->demod
)) == TRUE
) {
1573 dprintk("DEMOD LOCK OK\n");
1574 *status
= FE_HAS_CARRIER
1579 dprintk("DEMOD LOCK FAIL\n");
1584 static int stv0900_track(struct dvb_frontend
*fe
,
1585 struct dvb_frontend_parameters
*p
)
1590 static int stv0900_stop_ts(struct dvb_frontend
*fe
, int stop_ts
)
1593 struct stv0900_state
*state
= fe
->demodulator_priv
;
1594 struct stv0900_internal
*intp
= state
->internal
;
1595 enum fe_stv0900_demod_num demod
= state
->demod
;
1597 if (stop_ts
== TRUE
)
1598 stv0900_write_bits(intp
, RST_HWARE
, 1);
1600 stv0900_write_bits(intp
, RST_HWARE
, 0);
1605 static int stv0900_diseqc_init(struct dvb_frontend
*fe
)
1607 struct stv0900_state
*state
= fe
->demodulator_priv
;
1608 struct stv0900_internal
*intp
= state
->internal
;
1609 enum fe_stv0900_demod_num demod
= state
->demod
;
1611 stv0900_write_bits(intp
, DISTX_MODE
, state
->config
->diseqc_mode
);
1612 stv0900_write_bits(intp
, DISEQC_RESET
, 1);
1613 stv0900_write_bits(intp
, DISEQC_RESET
, 0);
1618 static int stv0900_init(struct dvb_frontend
*fe
)
1620 dprintk("%s\n", __func__
);
1622 stv0900_stop_ts(fe
, 1);
1623 stv0900_diseqc_init(fe
);
1628 static int stv0900_diseqc_send(struct stv0900_internal
*intp
, u8
*data
,
1629 u32 NbData
, enum fe_stv0900_demod_num demod
)
1633 stv0900_write_bits(intp
, DIS_PRECHARGE
, 1);
1634 while (i
< NbData
) {
1635 while (stv0900_get_bits(intp
, FIFO_FULL
))
1636 ;/* checkpatch complains */
1637 stv0900_write_reg(intp
, DISTXDATA
, data
[i
]);
1641 stv0900_write_bits(intp
, DIS_PRECHARGE
, 0);
1643 while ((stv0900_get_bits(intp
, TX_IDLE
) != 1) && (i
< 10)) {
1651 static int stv0900_send_master_cmd(struct dvb_frontend
*fe
,
1652 struct dvb_diseqc_master_cmd
*cmd
)
1654 struct stv0900_state
*state
= fe
->demodulator_priv
;
1656 return stv0900_diseqc_send(state
->internal
,
1662 static int stv0900_send_burst(struct dvb_frontend
*fe
, fe_sec_mini_cmd_t burst
)
1664 struct stv0900_state
*state
= fe
->demodulator_priv
;
1665 struct stv0900_internal
*intp
= state
->internal
;
1666 enum fe_stv0900_demod_num demod
= state
->demod
;
1672 stv0900_write_bits(intp
, DISTX_MODE
, 3);/* Unmodulated */
1674 stv0900_diseqc_send(intp
, &data
, 1, state
->demod
);
1677 stv0900_write_bits(intp
, DISTX_MODE
, 2);/* Modulated */
1679 stv0900_diseqc_send(intp
, &data
, 1, state
->demod
);
1686 static int stv0900_recv_slave_reply(struct dvb_frontend
*fe
,
1687 struct dvb_diseqc_slave_reply
*reply
)
1689 struct stv0900_state
*state
= fe
->demodulator_priv
;
1690 struct stv0900_internal
*intp
= state
->internal
;
1691 enum fe_stv0900_demod_num demod
= state
->demod
;
1696 while ((stv0900_get_bits(intp
, RX_END
) != 1) && (i
< 10)) {
1701 if (stv0900_get_bits(intp
, RX_END
)) {
1702 reply
->msg_len
= stv0900_get_bits(intp
, FIFO_BYTENBR
);
1704 for (i
= 0; i
< reply
->msg_len
; i
++)
1705 reply
->msg
[i
] = stv0900_read_reg(intp
, DISRXDATA
);
1711 static int stv0900_set_tone(struct dvb_frontend
*fe
, fe_sec_tone_mode_t toneoff
)
1713 struct stv0900_state
*state
= fe
->demodulator_priv
;
1714 struct stv0900_internal
*intp
= state
->internal
;
1715 enum fe_stv0900_demod_num demod
= state
->demod
;
1717 dprintk("%s: %s\n", __func__
, ((toneoff
== 0) ? "On" : "Off"));
1721 /*Set the DiseqC mode to 22Khz _continues_ tone*/
1722 stv0900_write_bits(intp
, DISTX_MODE
, 0);
1723 stv0900_write_bits(intp
, DISEQC_RESET
, 1);
1724 /*release DiseqC reset to enable the 22KHz tone*/
1725 stv0900_write_bits(intp
, DISEQC_RESET
, 0);
1728 /*return diseqc mode to config->diseqc_mode.
1729 Usually it's without _continues_ tone */
1730 stv0900_write_bits(intp
, DISTX_MODE
,
1731 state
->config
->diseqc_mode
);
1732 /*maintain the DiseqC reset to disable the 22KHz tone*/
1733 stv0900_write_bits(intp
, DISEQC_RESET
, 1);
1734 stv0900_write_bits(intp
, DISEQC_RESET
, 0);
1743 static void stv0900_release(struct dvb_frontend
*fe
)
1745 struct stv0900_state
*state
= fe
->demodulator_priv
;
1747 dprintk("%s\n", __func__
);
1749 if ((--(state
->internal
->dmds_used
)) <= 0) {
1751 dprintk("%s: Actually removing\n", __func__
);
1753 remove_inode(state
->internal
);
1754 kfree(state
->internal
);
1760 static struct dvb_frontend_ops stv0900_ops
= {
1763 .name
= "STV0900 frontend",
1765 .frequency_min
= 950000,
1766 .frequency_max
= 2150000,
1767 .frequency_stepsize
= 125,
1768 .frequency_tolerance
= 0,
1769 .symbol_rate_min
= 1000000,
1770 .symbol_rate_max
= 45000000,
1771 .symbol_rate_tolerance
= 500,
1772 .caps
= FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
|
1773 FE_CAN_FEC_3_4
| FE_CAN_FEC_5_6
|
1774 FE_CAN_FEC_7_8
| FE_CAN_QPSK
|
1775 FE_CAN_2G_MODULATION
|
1778 .release
= stv0900_release
,
1779 .init
= stv0900_init
,
1780 .get_frontend_algo
= stv0900_frontend_algo
,
1781 .i2c_gate_ctrl
= stv0900_i2c_gate_ctrl
,
1782 .diseqc_send_master_cmd
= stv0900_send_master_cmd
,
1783 .diseqc_send_burst
= stv0900_send_burst
,
1784 .diseqc_recv_slave_reply
= stv0900_recv_slave_reply
,
1785 .set_tone
= stv0900_set_tone
,
1786 .set_property
= stb0900_set_property
,
1787 .get_property
= stb0900_get_property
,
1788 .search
= stv0900_search
,
1789 .track
= stv0900_track
,
1790 .read_status
= stv0900_read_status
,
1791 .read_ber
= stv0900_read_ber
,
1792 .read_signal_strength
= stv0900_read_signal_strength
,
1793 .read_snr
= stv0900_read_snr
,
1794 .read_ucblocks
= stv0900_read_ucblocks
,
1797 struct dvb_frontend
*stv0900_attach(const struct stv0900_config
*config
,
1798 struct i2c_adapter
*i2c
,
1801 struct stv0900_state
*state
= NULL
;
1802 struct stv0900_init_params init_params
;
1803 enum fe_stv0900_error err_stv0900
;
1805 state
= kzalloc(sizeof(struct stv0900_state
), GFP_KERNEL
);
1809 state
->demod
= demod
;
1810 state
->config
= config
;
1811 state
->i2c_adap
= i2c
;
1813 memcpy(&state
->frontend
.ops
, &stv0900_ops
,
1814 sizeof(struct dvb_frontend_ops
));
1815 state
->frontend
.demodulator_priv
= state
;
1820 init_params
.dmd_ref_clk
= config
->xtal
;
1821 init_params
.demod_mode
= config
->demod_mode
;
1822 init_params
.rolloff
= STV0900_35
;
1823 init_params
.path1_ts_clock
= config
->path1_mode
;
1824 init_params
.tun1_maddress
= config
->tun1_maddress
;
1825 init_params
.tun1_iq_inv
= STV0900_IQ_NORMAL
;
1826 init_params
.tuner1_adc
= config
->tun1_adc
;
1827 init_params
.path2_ts_clock
= config
->path2_mode
;
1828 init_params
.ts_config
= config
->ts_config_regs
;
1829 init_params
.tun2_maddress
= config
->tun2_maddress
;
1830 init_params
.tuner2_adc
= config
->tun2_adc
;
1831 init_params
.tun2_iq_inv
= STV0900_IQ_SWAPPED
;
1833 err_stv0900
= stv0900_init_internal(&state
->frontend
,
1845 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__
, demod
);
1846 return &state
->frontend
;
1849 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1854 EXPORT_SYMBOL(stv0900_attach
);
1856 MODULE_PARM_DESC(debug
, "Set debug");
1858 MODULE_AUTHOR("Igor M. Liplianin");
1859 MODULE_DESCRIPTION("ST STV0900 frontend");
1860 MODULE_LICENSE("GPL");