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Merge branch 'x86-bootmem-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / isdn / hardware / mISDN / hfcmulti.c
1 /*
2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
3 *
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
7 *
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *
28 * Thanks to Cologne Chip AG for this great controller!
29 */
30
31 /*
32 * module parameters:
33 * type:
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
41 * Bit 10 = spare
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
44 * Bit 13 = spare
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
49 * Bit 18 = spare
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
53 * bus (PCM master)
54 *
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
64 *
65 * HFC-E1 only bits:
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
73 * mode instead.
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
77 * (E1 only)
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
79 * for default.
80 * (all other bits are reserved and shall be 0)
81 *
82 * debug:
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
85 *
86 * poll:
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
92 *
93 * pcm:
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
105 *
106 * dslot:
107 * NOTE: only one dslot value must be given for every card.
108 * Also this value must be given for non-E1 cards. If omitted, the E1
109 * card has D-channel on time slot 16, which is default.
110 * If 1..15 or 17..31, an alternate time slot is used for D-channel.
111 * In this case, the application must be able to handle this.
112 * If -1 is given, the D-channel is disabled and all 31 slots can be used
113 * for B-channel. (only for specific applications)
114 * If you don't know how to use it, you don't need it!
115 *
116 * iomode:
117 * NOTE: only one mode value must be given for every card.
118 * -> See hfc_multi.h for HFC_IO_MODE_* values
119 * By default, the IO mode is pci memory IO (MEMIO).
120 * Some cards requre specific IO mode, so it cannot be changed.
121 * It may be usefull to set IO mode to register io (REGIO) to solve
122 * PCI bridge problems.
123 * If unsure, don't give this parameter.
124 *
125 * clockdelay_nt:
126 * NOTE: only one clockdelay_nt value must be given once for all cards.
127 * Give the value of the clock control register (A_ST_CLK_DLY)
128 * of the S/T interfaces in NT mode.
129 * This register is needed for the TBR3 certification, so don't change it.
130 *
131 * clockdelay_te:
132 * NOTE: only one clockdelay_te value must be given once
133 * Give the value of the clock control register (A_ST_CLK_DLY)
134 * of the S/T interfaces in TE mode.
135 * This register is needed for the TBR3 certification, so don't change it.
136 *
137 * clock:
138 * NOTE: only one clock value must be given once
139 * Selects interface with clock source for mISDN and applications.
140 * Set to card number starting with 1. Set to -1 to disable.
141 * By default, the first card is used as clock source.
142 *
143 * hwid:
144 * NOTE: only one hwid value must be given once
145 * Enable special embedded devices with XHFC controllers.
146 */
147
148 /*
149 * debug register access (never use this, it will flood your system log)
150 * #define HFC_REGISTER_DEBUG
151 */
152
153 #define HFC_MULTI_VERSION "2.03"
154
155 #include <linux/module.h>
156 #include <linux/pci.h>
157 #include <linux/delay.h>
158 #include <linux/mISDNhw.h>
159 #include <linux/mISDNdsp.h>
160
161 /*
162 #define IRQCOUNT_DEBUG
163 #define IRQ_DEBUG
164 */
165
166 #include "hfc_multi.h"
167 #ifdef ECHOPREP
168 #include "gaintab.h"
169 #endif
170
171 #define MAX_CARDS 8
172 #define MAX_PORTS (8 * MAX_CARDS)
173
174 static LIST_HEAD(HFClist);
175 static spinlock_t HFClock; /* global hfc list lock */
176
177 static void ph_state_change(struct dchannel *);
178
179 static struct hfc_multi *syncmaster;
180 static int plxsd_master; /* if we have a master card (yet) */
181 static spinlock_t plx_lock; /* may not acquire other lock inside */
182
183 #define TYP_E1 1
184 #define TYP_4S 4
185 #define TYP_8S 8
186
187 static int poll_timer = 6; /* default = 128 samples = 16ms */
188 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
189 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
190 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
191 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode
192 (0x60 MUST be included!) */
193
194 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
195 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
196 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
197
198 /*
199 * module stuff
200 */
201
202 static uint type[MAX_CARDS];
203 static int pcm[MAX_CARDS];
204 static int dslot[MAX_CARDS];
205 static uint iomode[MAX_CARDS];
206 static uint port[MAX_PORTS];
207 static uint debug;
208 static uint poll;
209 static int clock;
210 static uint timer;
211 static uint clockdelay_te = CLKDEL_TE;
212 static uint clockdelay_nt = CLKDEL_NT;
213 #define HWID_NONE 0
214 #define HWID_MINIP4 1
215 #define HWID_MINIP8 2
216 #define HWID_MINIP16 3
217 static uint hwid = HWID_NONE;
218
219 static int HFC_cnt, Port_cnt, PCM_cnt = 99;
220
221 MODULE_AUTHOR("Andreas Eversberg");
222 MODULE_LICENSE("GPL");
223 MODULE_VERSION(HFC_MULTI_VERSION);
224 module_param(debug, uint, S_IRUGO | S_IWUSR);
225 module_param(poll, uint, S_IRUGO | S_IWUSR);
226 module_param(clock, int, S_IRUGO | S_IWUSR);
227 module_param(timer, uint, S_IRUGO | S_IWUSR);
228 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
229 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
230 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
231 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
232 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
233 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
234 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
235 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
236
237 #ifdef HFC_REGISTER_DEBUG
238 #define HFC_outb(hc, reg, val) \
239 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
240 #define HFC_outb_nodebug(hc, reg, val) \
241 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
242 #define HFC_inb(hc, reg) \
243 (hc->HFC_inb(hc, reg, __func__, __LINE__))
244 #define HFC_inb_nodebug(hc, reg) \
245 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
246 #define HFC_inw(hc, reg) \
247 (hc->HFC_inw(hc, reg, __func__, __LINE__))
248 #define HFC_inw_nodebug(hc, reg) \
249 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
250 #define HFC_wait(hc) \
251 (hc->HFC_wait(hc, __func__, __LINE__))
252 #define HFC_wait_nodebug(hc) \
253 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
254 #else
255 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
256 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
257 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
258 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
259 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
260 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
261 #define HFC_wait(hc) (hc->HFC_wait(hc))
262 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
263 #endif
264
265 #ifdef CONFIG_MISDN_HFCMULTI_8xx
266 #include "hfc_multi_8xx.h"
267 #endif
268
269 /* HFC_IO_MODE_PCIMEM */
270 static void
271 #ifdef HFC_REGISTER_DEBUG
272 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
273 const char *function, int line)
274 #else
275 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
276 #endif
277 {
278 writeb(val, hc->pci_membase + reg);
279 }
280 static u_char
281 #ifdef HFC_REGISTER_DEBUG
282 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
283 #else
284 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
285 #endif
286 {
287 return readb(hc->pci_membase + reg);
288 }
289 static u_short
290 #ifdef HFC_REGISTER_DEBUG
291 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
292 #else
293 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
294 #endif
295 {
296 return readw(hc->pci_membase + reg);
297 }
298 static void
299 #ifdef HFC_REGISTER_DEBUG
300 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
301 #else
302 HFC_wait_pcimem(struct hfc_multi *hc)
303 #endif
304 {
305 while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
306 cpu_relax();
307 }
308
309 /* HFC_IO_MODE_REGIO */
310 static void
311 #ifdef HFC_REGISTER_DEBUG
312 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
313 const char *function, int line)
314 #else
315 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
316 #endif
317 {
318 outb(reg, hc->pci_iobase + 4);
319 outb(val, hc->pci_iobase);
320 }
321 static u_char
322 #ifdef HFC_REGISTER_DEBUG
323 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
324 #else
325 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
326 #endif
327 {
328 outb(reg, hc->pci_iobase + 4);
329 return inb(hc->pci_iobase);
330 }
331 static u_short
332 #ifdef HFC_REGISTER_DEBUG
333 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
334 #else
335 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
336 #endif
337 {
338 outb(reg, hc->pci_iobase + 4);
339 return inw(hc->pci_iobase);
340 }
341 static void
342 #ifdef HFC_REGISTER_DEBUG
343 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
344 #else
345 HFC_wait_regio(struct hfc_multi *hc)
346 #endif
347 {
348 outb(R_STATUS, hc->pci_iobase + 4);
349 while (inb(hc->pci_iobase) & V_BUSY)
350 cpu_relax();
351 }
352
353 #ifdef HFC_REGISTER_DEBUG
354 static void
355 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
356 const char *function, int line)
357 {
358 char regname[256] = "", bits[9] = "xxxxxxxx";
359 int i;
360
361 i = -1;
362 while (hfc_register_names[++i].name) {
363 if (hfc_register_names[i].reg == reg)
364 strcat(regname, hfc_register_names[i].name);
365 }
366 if (regname[0] == '\0')
367 strcpy(regname, "register");
368
369 bits[7] = '0' + (!!(val & 1));
370 bits[6] = '0' + (!!(val & 2));
371 bits[5] = '0' + (!!(val & 4));
372 bits[4] = '0' + (!!(val & 8));
373 bits[3] = '0' + (!!(val & 16));
374 bits[2] = '0' + (!!(val & 32));
375 bits[1] = '0' + (!!(val & 64));
376 bits[0] = '0' + (!!(val & 128));
377 printk(KERN_DEBUG
378 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
379 hc->id, reg, regname, val, bits, function, line);
380 HFC_outb_nodebug(hc, reg, val);
381 }
382 static u_char
383 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
384 {
385 char regname[256] = "", bits[9] = "xxxxxxxx";
386 u_char val = HFC_inb_nodebug(hc, reg);
387 int i;
388
389 i = 0;
390 while (hfc_register_names[i++].name)
391 ;
392 while (hfc_register_names[++i].name) {
393 if (hfc_register_names[i].reg == reg)
394 strcat(regname, hfc_register_names[i].name);
395 }
396 if (regname[0] == '\0')
397 strcpy(regname, "register");
398
399 bits[7] = '0' + (!!(val & 1));
400 bits[6] = '0' + (!!(val & 2));
401 bits[5] = '0' + (!!(val & 4));
402 bits[4] = '0' + (!!(val & 8));
403 bits[3] = '0' + (!!(val & 16));
404 bits[2] = '0' + (!!(val & 32));
405 bits[1] = '0' + (!!(val & 64));
406 bits[0] = '0' + (!!(val & 128));
407 printk(KERN_DEBUG
408 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
409 hc->id, reg, regname, val, bits, function, line);
410 return val;
411 }
412 static u_short
413 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
414 {
415 char regname[256] = "";
416 u_short val = HFC_inw_nodebug(hc, reg);
417 int i;
418
419 i = 0;
420 while (hfc_register_names[i++].name)
421 ;
422 while (hfc_register_names[++i].name) {
423 if (hfc_register_names[i].reg == reg)
424 strcat(regname, hfc_register_names[i].name);
425 }
426 if (regname[0] == '\0')
427 strcpy(regname, "register");
428
429 printk(KERN_DEBUG
430 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
431 hc->id, reg, regname, val, function, line);
432 return val;
433 }
434 static void
435 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
436 {
437 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
438 hc->id, function, line);
439 HFC_wait_nodebug(hc);
440 }
441 #endif
442
443 /* write fifo data (REGIO) */
444 static void
445 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
446 {
447 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
448 while (len>>2) {
449 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
450 data += 4;
451 len -= 4;
452 }
453 while (len>>1) {
454 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
455 data += 2;
456 len -= 2;
457 }
458 while (len) {
459 outb(*data, hc->pci_iobase);
460 data++;
461 len--;
462 }
463 }
464 /* write fifo data (PCIMEM) */
465 static void
466 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
467 {
468 while (len>>2) {
469 writel(cpu_to_le32(*(u32 *)data),
470 hc->pci_membase + A_FIFO_DATA0);
471 data += 4;
472 len -= 4;
473 }
474 while (len>>1) {
475 writew(cpu_to_le16(*(u16 *)data),
476 hc->pci_membase + A_FIFO_DATA0);
477 data += 2;
478 len -= 2;
479 }
480 while (len) {
481 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
482 data++;
483 len--;
484 }
485 }
486
487 /* read fifo data (REGIO) */
488 static void
489 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
490 {
491 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
492 while (len>>2) {
493 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
494 data += 4;
495 len -= 4;
496 }
497 while (len>>1) {
498 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
499 data += 2;
500 len -= 2;
501 }
502 while (len) {
503 *data = inb(hc->pci_iobase);
504 data++;
505 len--;
506 }
507 }
508
509 /* read fifo data (PCIMEM) */
510 static void
511 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
512 {
513 while (len>>2) {
514 *(u32 *)data =
515 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
516 data += 4;
517 len -= 4;
518 }
519 while (len>>1) {
520 *(u16 *)data =
521 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
522 data += 2;
523 len -= 2;
524 }
525 while (len) {
526 *data = readb(hc->pci_membase + A_FIFO_DATA0);
527 data++;
528 len--;
529 }
530 }
531
532 static void
533 enable_hwirq(struct hfc_multi *hc)
534 {
535 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
536 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
537 }
538
539 static void
540 disable_hwirq(struct hfc_multi *hc)
541 {
542 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
543 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
544 }
545
546 #define NUM_EC 2
547 #define MAX_TDM_CHAN 32
548
549
550 inline void
551 enablepcibridge(struct hfc_multi *c)
552 {
553 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
554 }
555
556 inline void
557 disablepcibridge(struct hfc_multi *c)
558 {
559 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
560 }
561
562 inline unsigned char
563 readpcibridge(struct hfc_multi *hc, unsigned char address)
564 {
565 unsigned short cipv;
566 unsigned char data;
567
568 if (!hc->pci_iobase)
569 return 0;
570
571 /* slow down a PCI read access by 1 PCI clock cycle */
572 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
573
574 if (address == 0)
575 cipv = 0x4000;
576 else
577 cipv = 0x5800;
578
579 /* select local bridge port address by writing to CIP port */
580 /* data = HFC_inb(c, cipv); * was _io before */
581 outw(cipv, hc->pci_iobase + 4);
582 data = inb(hc->pci_iobase);
583
584 /* restore R_CTRL for normal PCI read cycle speed */
585 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
586
587 return data;
588 }
589
590 inline void
591 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
592 {
593 unsigned short cipv;
594 unsigned int datav;
595
596 if (!hc->pci_iobase)
597 return;
598
599 if (address == 0)
600 cipv = 0x4000;
601 else
602 cipv = 0x5800;
603
604 /* select local bridge port address by writing to CIP port */
605 outw(cipv, hc->pci_iobase + 4);
606 /* define a 32 bit dword with 4 identical bytes for write sequence */
607 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
608 ((__u32) data << 24);
609
610 /*
611 * write this 32 bit dword to the bridge data port
612 * this will initiate a write sequence of up to 4 writes to the same
613 * address on the local bus interface the number of write accesses
614 * is undefined but >=1 and depends on the next PCI transaction
615 * during write sequence on the local bus
616 */
617 outl(datav, hc->pci_iobase);
618 }
619
620 inline void
621 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
622 {
623 /* Do data pin read low byte */
624 HFC_outb(hc, R_GPIO_OUT1, reg);
625 }
626
627 inline void
628 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
629 {
630 cpld_set_reg(hc, reg);
631
632 enablepcibridge(hc);
633 writepcibridge(hc, 1, val);
634 disablepcibridge(hc);
635
636 return;
637 }
638
639 inline unsigned char
640 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
641 {
642 unsigned char bytein;
643
644 cpld_set_reg(hc, reg);
645
646 /* Do data pin read low byte */
647 HFC_outb(hc, R_GPIO_OUT1, reg);
648
649 enablepcibridge(hc);
650 bytein = readpcibridge(hc, 1);
651 disablepcibridge(hc);
652
653 return bytein;
654 }
655
656 inline void
657 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
658 {
659 cpld_write_reg(hc, 0, 0xff & addr);
660 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
661 }
662
663 inline unsigned short
664 vpm_read_address(struct hfc_multi *c)
665 {
666 unsigned short addr;
667 unsigned short highbit;
668
669 addr = cpld_read_reg(c, 0);
670 highbit = cpld_read_reg(c, 1);
671
672 addr = addr | (highbit << 8);
673
674 return addr & 0x1ff;
675 }
676
677 inline unsigned char
678 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
679 {
680 unsigned char res;
681
682 vpm_write_address(c, addr);
683
684 if (!which)
685 cpld_set_reg(c, 2);
686 else
687 cpld_set_reg(c, 3);
688
689 enablepcibridge(c);
690 res = readpcibridge(c, 1);
691 disablepcibridge(c);
692
693 cpld_set_reg(c, 0);
694
695 return res;
696 }
697
698 inline void
699 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
700 unsigned char data)
701 {
702 vpm_write_address(c, addr);
703
704 enablepcibridge(c);
705
706 if (!which)
707 cpld_set_reg(c, 2);
708 else
709 cpld_set_reg(c, 3);
710
711 writepcibridge(c, 1, data);
712
713 cpld_set_reg(c, 0);
714
715 disablepcibridge(c);
716
717 {
718 unsigned char regin;
719 regin = vpm_in(c, which, addr);
720 if (regin != data)
721 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
722 "0x%x\n", data, addr, regin);
723 }
724
725 }
726
727
728 static void
729 vpm_init(struct hfc_multi *wc)
730 {
731 unsigned char reg;
732 unsigned int mask;
733 unsigned int i, x, y;
734 unsigned int ver;
735
736 for (x = 0; x < NUM_EC; x++) {
737 /* Setup GPIO's */
738 if (!x) {
739 ver = vpm_in(wc, x, 0x1a0);
740 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
741 }
742
743 for (y = 0; y < 4; y++) {
744 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
745 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
746 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
747 }
748
749 /* Setup TDM path - sets fsync and tdm_clk as inputs */
750 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
751 vpm_out(wc, x, 0x1a3, reg & ~2);
752
753 /* Setup Echo length (256 taps) */
754 vpm_out(wc, x, 0x022, 1);
755 vpm_out(wc, x, 0x023, 0xff);
756
757 /* Setup timeslots */
758 vpm_out(wc, x, 0x02f, 0x00);
759 mask = 0x02020202 << (x * 4);
760
761 /* Setup the tdm channel masks for all chips */
762 for (i = 0; i < 4; i++)
763 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
764
765 /* Setup convergence rate */
766 printk(KERN_DEBUG "VPM: A-law mode\n");
767 reg = 0x00 | 0x10 | 0x01;
768 vpm_out(wc, x, 0x20, reg);
769 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
770 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
771
772 vpm_out(wc, x, 0x24, 0x02);
773 reg = vpm_in(wc, x, 0x24);
774 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
775
776 /* Initialize echo cans */
777 for (i = 0; i < MAX_TDM_CHAN; i++) {
778 if (mask & (0x00000001 << i))
779 vpm_out(wc, x, i, 0x00);
780 }
781
782 /*
783 * ARM arch at least disallows a udelay of
784 * more than 2ms... it gives a fake "__bad_udelay"
785 * reference at link-time.
786 * long delays in kernel code are pretty sucky anyway
787 * for now work around it using 5 x 2ms instead of 1 x 10ms
788 */
789
790 udelay(2000);
791 udelay(2000);
792 udelay(2000);
793 udelay(2000);
794 udelay(2000);
795
796 /* Put in bypass mode */
797 for (i = 0; i < MAX_TDM_CHAN; i++) {
798 if (mask & (0x00000001 << i))
799 vpm_out(wc, x, i, 0x01);
800 }
801
802 /* Enable bypass */
803 for (i = 0; i < MAX_TDM_CHAN; i++) {
804 if (mask & (0x00000001 << i))
805 vpm_out(wc, x, 0x78 + i, 0x01);
806 }
807
808 }
809 }
810
811 #ifdef UNUSED
812 static void
813 vpm_check(struct hfc_multi *hctmp)
814 {
815 unsigned char gpi2;
816
817 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
818
819 if ((gpi2 & 0x3) != 0x3)
820 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
821 }
822 #endif /* UNUSED */
823
824
825 /*
826 * Interface to enable/disable the HW Echocan
827 *
828 * these functions are called within a spin_lock_irqsave on
829 * the channel instance lock, so we are not disturbed by irqs
830 *
831 * we can later easily change the interface to make other
832 * things configurable, for now we configure the taps
833 *
834 */
835
836 static void
837 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
838 {
839 unsigned int timeslot;
840 unsigned int unit;
841 struct bchannel *bch = hc->chan[ch].bch;
842 #ifdef TXADJ
843 int txadj = -4;
844 struct sk_buff *skb;
845 #endif
846 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
847 return;
848
849 if (!bch)
850 return;
851
852 #ifdef TXADJ
853 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
854 sizeof(int), &txadj, GFP_ATOMIC);
855 if (skb)
856 recv_Bchannel_skb(bch, skb);
857 #endif
858
859 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
860 unit = ch % 4;
861
862 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
863 taps, timeslot);
864
865 vpm_out(hc, unit, timeslot, 0x7e);
866 }
867
868 static void
869 vpm_echocan_off(struct hfc_multi *hc, int ch)
870 {
871 unsigned int timeslot;
872 unsigned int unit;
873 struct bchannel *bch = hc->chan[ch].bch;
874 #ifdef TXADJ
875 int txadj = 0;
876 struct sk_buff *skb;
877 #endif
878
879 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
880 return;
881
882 if (!bch)
883 return;
884
885 #ifdef TXADJ
886 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
887 sizeof(int), &txadj, GFP_ATOMIC);
888 if (skb)
889 recv_Bchannel_skb(bch, skb);
890 #endif
891
892 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
893 unit = ch % 4;
894
895 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
896 timeslot);
897 /* FILLME */
898 vpm_out(hc, unit, timeslot, 0x01);
899 }
900
901
902 /*
903 * Speech Design resync feature
904 * NOTE: This is called sometimes outside interrupt handler.
905 * We must lock irqsave, so no other interrupt (other card) will occurr!
906 * Also multiple interrupts may nest, so must lock each access (lists, card)!
907 */
908 static inline void
909 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
910 {
911 struct hfc_multi *hc, *next, *pcmmaster = NULL;
912 void __iomem *plx_acc_32;
913 u_int pv;
914 u_long flags;
915
916 spin_lock_irqsave(&HFClock, flags);
917 spin_lock(&plx_lock); /* must be locked inside other locks */
918
919 if (debug & DEBUG_HFCMULTI_PLXSD)
920 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
921 __func__, syncmaster);
922
923 /* select new master */
924 if (newmaster) {
925 if (debug & DEBUG_HFCMULTI_PLXSD)
926 printk(KERN_DEBUG "using provided controller\n");
927 } else {
928 list_for_each_entry_safe(hc, next, &HFClist, list) {
929 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
930 if (hc->syncronized) {
931 newmaster = hc;
932 break;
933 }
934 }
935 }
936 }
937
938 /* Disable sync of all cards */
939 list_for_each_entry_safe(hc, next, &HFClist, list) {
940 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
941 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
942 pv = readl(plx_acc_32);
943 pv &= ~PLX_SYNC_O_EN;
944 writel(pv, plx_acc_32);
945 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
946 pcmmaster = hc;
947 if (hc->ctype == HFC_TYPE_E1) {
948 if (debug & DEBUG_HFCMULTI_PLXSD)
949 printk(KERN_DEBUG
950 "Schedule SYNC_I\n");
951 hc->e1_resync |= 1; /* get SYNC_I */
952 }
953 }
954 }
955 }
956
957 if (newmaster) {
958 hc = newmaster;
959 if (debug & DEBUG_HFCMULTI_PLXSD)
960 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
961 "interface.\n", hc->id, hc);
962 /* Enable new sync master */
963 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
964 pv = readl(plx_acc_32);
965 pv |= PLX_SYNC_O_EN;
966 writel(pv, plx_acc_32);
967 /* switch to jatt PLL, if not disabled by RX_SYNC */
968 if (hc->ctype == HFC_TYPE_E1
969 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
970 if (debug & DEBUG_HFCMULTI_PLXSD)
971 printk(KERN_DEBUG "Schedule jatt PLL\n");
972 hc->e1_resync |= 2; /* switch to jatt */
973 }
974 } else {
975 if (pcmmaster) {
976 hc = pcmmaster;
977 if (debug & DEBUG_HFCMULTI_PLXSD)
978 printk(KERN_DEBUG
979 "id=%d (0x%p) = PCM master syncronized "
980 "with QUARTZ\n", hc->id, hc);
981 if (hc->ctype == HFC_TYPE_E1) {
982 /* Use the crystal clock for the PCM
983 master card */
984 if (debug & DEBUG_HFCMULTI_PLXSD)
985 printk(KERN_DEBUG
986 "Schedule QUARTZ for HFC-E1\n");
987 hc->e1_resync |= 4; /* switch quartz */
988 } else {
989 if (debug & DEBUG_HFCMULTI_PLXSD)
990 printk(KERN_DEBUG
991 "QUARTZ is automatically "
992 "enabled by HFC-%dS\n", hc->ctype);
993 }
994 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
995 pv = readl(plx_acc_32);
996 pv |= PLX_SYNC_O_EN;
997 writel(pv, plx_acc_32);
998 } else
999 if (!rm)
1000 printk(KERN_ERR "%s no pcm master, this MUST "
1001 "not happen!\n", __func__);
1002 }
1003 syncmaster = newmaster;
1004
1005 spin_unlock(&plx_lock);
1006 spin_unlock_irqrestore(&HFClock, flags);
1007 }
1008
1009 /* This must be called AND hc must be locked irqsave!!! */
1010 inline void
1011 plxsd_checksync(struct hfc_multi *hc, int rm)
1012 {
1013 if (hc->syncronized) {
1014 if (syncmaster == NULL) {
1015 if (debug & DEBUG_HFCMULTI_PLXSD)
1016 printk(KERN_DEBUG "%s: GOT sync on card %d"
1017 " (id=%d)\n", __func__, hc->id + 1,
1018 hc->id);
1019 hfcmulti_resync(hc, hc, rm);
1020 }
1021 } else {
1022 if (syncmaster == hc) {
1023 if (debug & DEBUG_HFCMULTI_PLXSD)
1024 printk(KERN_DEBUG "%s: LOST sync on card %d"
1025 " (id=%d)\n", __func__, hc->id + 1,
1026 hc->id);
1027 hfcmulti_resync(hc, NULL, rm);
1028 }
1029 }
1030 }
1031
1032
1033 /*
1034 * free hardware resources used by driver
1035 */
1036 static void
1037 release_io_hfcmulti(struct hfc_multi *hc)
1038 {
1039 void __iomem *plx_acc_32;
1040 u_int pv;
1041 u_long plx_flags;
1042
1043 if (debug & DEBUG_HFCMULTI_INIT)
1044 printk(KERN_DEBUG "%s: entered\n", __func__);
1045
1046 /* soft reset also masks all interrupts */
1047 hc->hw.r_cirm |= V_SRES;
1048 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1049 udelay(1000);
1050 hc->hw.r_cirm &= ~V_SRES;
1051 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1052 udelay(1000); /* instead of 'wait' that may cause locking */
1053
1054 /* release Speech Design card, if PLX was initialized */
1055 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1056 if (debug & DEBUG_HFCMULTI_PLXSD)
1057 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1058 __func__, hc->id + 1);
1059 spin_lock_irqsave(&plx_lock, plx_flags);
1060 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1061 writel(PLX_GPIOC_INIT, plx_acc_32);
1062 pv = readl(plx_acc_32);
1063 /* Termination off */
1064 pv &= ~PLX_TERM_ON;
1065 /* Disconnect the PCM */
1066 pv |= PLX_SLAVE_EN_N;
1067 pv &= ~PLX_MASTER_EN;
1068 pv &= ~PLX_SYNC_O_EN;
1069 /* Put the DSP in Reset */
1070 pv &= ~PLX_DSP_RES_N;
1071 writel(pv, plx_acc_32);
1072 if (debug & DEBUG_HFCMULTI_INIT)
1073 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1074 __func__, pv);
1075 spin_unlock_irqrestore(&plx_lock, plx_flags);
1076 }
1077
1078 /* disable memory mapped ports / io ports */
1079 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1080 if (hc->pci_dev)
1081 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1082 if (hc->pci_membase)
1083 iounmap(hc->pci_membase);
1084 if (hc->plx_membase)
1085 iounmap(hc->plx_membase);
1086 if (hc->pci_iobase)
1087 release_region(hc->pci_iobase, 8);
1088 if (hc->xhfc_membase)
1089 iounmap((void *)hc->xhfc_membase);
1090
1091 if (hc->pci_dev) {
1092 pci_disable_device(hc->pci_dev);
1093 pci_set_drvdata(hc->pci_dev, NULL);
1094 }
1095 if (debug & DEBUG_HFCMULTI_INIT)
1096 printk(KERN_DEBUG "%s: done\n", __func__);
1097 }
1098
1099 /*
1100 * function called to reset the HFC chip. A complete software reset of chip
1101 * and fifos is done. All configuration of the chip is done.
1102 */
1103
1104 static int
1105 init_chip(struct hfc_multi *hc)
1106 {
1107 u_long flags, val, val2 = 0, rev;
1108 int i, err = 0;
1109 u_char r_conf_en, rval;
1110 void __iomem *plx_acc_32;
1111 u_int pv;
1112 u_long plx_flags, hfc_flags;
1113 int plx_count;
1114 struct hfc_multi *pos, *next, *plx_last_hc;
1115
1116 spin_lock_irqsave(&hc->lock, flags);
1117 /* reset all registers */
1118 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1119
1120 /* revision check */
1121 if (debug & DEBUG_HFCMULTI_INIT)
1122 printk(KERN_DEBUG "%s: entered\n", __func__);
1123 val = HFC_inb(hc, R_CHIP_ID);
1124 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1125 (val >> 1) != 0x31) {
1126 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1127 err = -EIO;
1128 goto out;
1129 }
1130 rev = HFC_inb(hc, R_CHIP_RV);
1131 printk(KERN_INFO
1132 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1133 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1134 " (old FIFO handling)" : "");
1135 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1136 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1137 printk(KERN_WARNING
1138 "HFC_multi: NOTE: Your chip is revision 0, "
1139 "ask Cologne Chip for update. Newer chips "
1140 "have a better FIFO handling. Old chips "
1141 "still work but may have slightly lower "
1142 "HDLC transmit performance.\n");
1143 }
1144 if (rev > 1) {
1145 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1146 "consider chip revision = %ld. The chip / "
1147 "bridge may not work.\n", rev);
1148 }
1149
1150 /* set s-ram size */
1151 hc->Flen = 0x10;
1152 hc->Zmin = 0x80;
1153 hc->Zlen = 384;
1154 hc->DTMFbase = 0x1000;
1155 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1156 if (debug & DEBUG_HFCMULTI_INIT)
1157 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1158 __func__);
1159 hc->hw.r_ctrl |= V_EXT_RAM;
1160 hc->hw.r_ram_sz = 1;
1161 hc->Flen = 0x20;
1162 hc->Zmin = 0xc0;
1163 hc->Zlen = 1856;
1164 hc->DTMFbase = 0x2000;
1165 }
1166 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1167 if (debug & DEBUG_HFCMULTI_INIT)
1168 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1169 __func__);
1170 hc->hw.r_ctrl |= V_EXT_RAM;
1171 hc->hw.r_ram_sz = 2;
1172 hc->Flen = 0x20;
1173 hc->Zmin = 0xc0;
1174 hc->Zlen = 8000;
1175 hc->DTMFbase = 0x2000;
1176 }
1177 if (hc->ctype == HFC_TYPE_XHFC) {
1178 hc->Flen = 0x8;
1179 hc->Zmin = 0x0;
1180 hc->Zlen = 64;
1181 hc->DTMFbase = 0x0;
1182 }
1183 hc->max_trans = poll << 1;
1184 if (hc->max_trans > hc->Zlen)
1185 hc->max_trans = hc->Zlen;
1186
1187 /* Speech Design PLX bridge */
1188 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1189 if (debug & DEBUG_HFCMULTI_PLXSD)
1190 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1191 __func__, hc->id + 1);
1192 spin_lock_irqsave(&plx_lock, plx_flags);
1193 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1194 writel(PLX_GPIOC_INIT, plx_acc_32);
1195 pv = readl(plx_acc_32);
1196 /* The first and the last cards are terminating the PCM bus */
1197 pv |= PLX_TERM_ON; /* hc is currently the last */
1198 /* Disconnect the PCM */
1199 pv |= PLX_SLAVE_EN_N;
1200 pv &= ~PLX_MASTER_EN;
1201 pv &= ~PLX_SYNC_O_EN;
1202 /* Put the DSP in Reset */
1203 pv &= ~PLX_DSP_RES_N;
1204 writel(pv, plx_acc_32);
1205 spin_unlock_irqrestore(&plx_lock, plx_flags);
1206 if (debug & DEBUG_HFCMULTI_INIT)
1207 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1208 __func__, pv);
1209 /*
1210 * If we are the 3rd PLXSD card or higher, we must turn
1211 * termination of last PLXSD card off.
1212 */
1213 spin_lock_irqsave(&HFClock, hfc_flags);
1214 plx_count = 0;
1215 plx_last_hc = NULL;
1216 list_for_each_entry_safe(pos, next, &HFClist, list) {
1217 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1218 plx_count++;
1219 if (pos != hc)
1220 plx_last_hc = pos;
1221 }
1222 }
1223 if (plx_count >= 3) {
1224 if (debug & DEBUG_HFCMULTI_PLXSD)
1225 printk(KERN_DEBUG "%s: card %d is between, so "
1226 "we disable termination\n",
1227 __func__, plx_last_hc->id + 1);
1228 spin_lock_irqsave(&plx_lock, plx_flags);
1229 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1230 pv = readl(plx_acc_32);
1231 pv &= ~PLX_TERM_ON;
1232 writel(pv, plx_acc_32);
1233 spin_unlock_irqrestore(&plx_lock, plx_flags);
1234 if (debug & DEBUG_HFCMULTI_INIT)
1235 printk(KERN_DEBUG
1236 "%s: term off: PLX_GPIO=%x\n",
1237 __func__, pv);
1238 }
1239 spin_unlock_irqrestore(&HFClock, hfc_flags);
1240 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1241 }
1242
1243 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1244 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1245
1246 /* we only want the real Z2 read-pointer for revision > 0 */
1247 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1248 hc->hw.r_ram_sz |= V_FZ_MD;
1249
1250 /* select pcm mode */
1251 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1252 if (debug & DEBUG_HFCMULTI_INIT)
1253 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1254 __func__);
1255 } else
1256 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1257 if (debug & DEBUG_HFCMULTI_INIT)
1258 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1259 __func__);
1260 hc->hw.r_pcm_md0 |= V_PCM_MD;
1261 } else {
1262 if (debug & DEBUG_HFCMULTI_INIT)
1263 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1264 __func__);
1265 }
1266
1267 /* soft reset */
1268 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1269 if (hc->ctype == HFC_TYPE_XHFC)
1270 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1271 0x11 /* 16 Bytes TX/RX */);
1272 else
1273 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1274 HFC_outb(hc, R_FIFO_MD, 0);
1275 if (hc->ctype == HFC_TYPE_XHFC)
1276 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1277 else
1278 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1279 | V_RLD_EPR;
1280 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1281 udelay(100);
1282 hc->hw.r_cirm = 0;
1283 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1284 udelay(100);
1285 if (hc->ctype != HFC_TYPE_XHFC)
1286 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1287
1288 /* Speech Design PLX bridge pcm and sync mode */
1289 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1290 spin_lock_irqsave(&plx_lock, plx_flags);
1291 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1292 pv = readl(plx_acc_32);
1293 /* Connect PCM */
1294 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1295 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1296 pv |= PLX_SYNC_O_EN;
1297 if (debug & DEBUG_HFCMULTI_INIT)
1298 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1299 __func__, pv);
1300 } else {
1301 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1302 pv &= ~PLX_SYNC_O_EN;
1303 if (debug & DEBUG_HFCMULTI_INIT)
1304 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1305 __func__, pv);
1306 }
1307 writel(pv, plx_acc_32);
1308 spin_unlock_irqrestore(&plx_lock, plx_flags);
1309 }
1310
1311 /* PCM setup */
1312 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1313 if (hc->slots == 32)
1314 HFC_outb(hc, R_PCM_MD1, 0x00);
1315 if (hc->slots == 64)
1316 HFC_outb(hc, R_PCM_MD1, 0x10);
1317 if (hc->slots == 128)
1318 HFC_outb(hc, R_PCM_MD1, 0x20);
1319 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1320 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1321 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1322 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1323 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1324 else
1325 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1326 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1327 for (i = 0; i < 256; i++) {
1328 HFC_outb_nodebug(hc, R_SLOT, i);
1329 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1330 if (hc->ctype != HFC_TYPE_XHFC)
1331 HFC_outb_nodebug(hc, A_CONF, 0);
1332 hc->slot_owner[i] = -1;
1333 }
1334
1335 /* set clock speed */
1336 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1337 if (debug & DEBUG_HFCMULTI_INIT)
1338 printk(KERN_DEBUG
1339 "%s: setting double clock\n", __func__);
1340 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1341 }
1342
1343 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1344 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1345
1346 /* B410P GPIO */
1347 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1348 printk(KERN_NOTICE "Setting GPIOs\n");
1349 HFC_outb(hc, R_GPIO_SEL, 0x30);
1350 HFC_outb(hc, R_GPIO_EN1, 0x3);
1351 udelay(1000);
1352 printk(KERN_NOTICE "calling vpm_init\n");
1353 vpm_init(hc);
1354 }
1355
1356 /* check if R_F0_CNT counts (8 kHz frame count) */
1357 val = HFC_inb(hc, R_F0_CNTL);
1358 val += HFC_inb(hc, R_F0_CNTH) << 8;
1359 if (debug & DEBUG_HFCMULTI_INIT)
1360 printk(KERN_DEBUG
1361 "HFC_multi F0_CNT %ld after reset\n", val);
1362 spin_unlock_irqrestore(&hc->lock, flags);
1363 set_current_state(TASK_UNINTERRUPTIBLE);
1364 schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1365 spin_lock_irqsave(&hc->lock, flags);
1366 val2 = HFC_inb(hc, R_F0_CNTL);
1367 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1368 if (debug & DEBUG_HFCMULTI_INIT)
1369 printk(KERN_DEBUG
1370 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1371 val2);
1372 if (val2 >= val+8) { /* 1 ms */
1373 /* it counts, so we keep the pcm mode */
1374 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1375 printk(KERN_INFO "controller is PCM bus MASTER\n");
1376 else
1377 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1378 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1379 else {
1380 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1381 printk(KERN_INFO "controller is PCM bus SLAVE "
1382 "(auto detected)\n");
1383 }
1384 } else {
1385 /* does not count */
1386 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1387 controller_fail:
1388 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1389 "pulse. Seems that controller fails.\n");
1390 err = -EIO;
1391 goto out;
1392 }
1393 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1394 printk(KERN_INFO "controller is PCM bus SLAVE "
1395 "(ignoring missing PCM clock)\n");
1396 } else {
1397 /* only one pcm master */
1398 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1399 && plxsd_master) {
1400 printk(KERN_ERR "HFC_multi ERROR, no clock "
1401 "on another Speech Design card found. "
1402 "Please be sure to connect PCM cable.\n");
1403 err = -EIO;
1404 goto out;
1405 }
1406 /* retry with master clock */
1407 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1408 spin_lock_irqsave(&plx_lock, plx_flags);
1409 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1410 pv = readl(plx_acc_32);
1411 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1412 pv |= PLX_SYNC_O_EN;
1413 writel(pv, plx_acc_32);
1414 spin_unlock_irqrestore(&plx_lock, plx_flags);
1415 if (debug & DEBUG_HFCMULTI_INIT)
1416 printk(KERN_DEBUG "%s: master: "
1417 "PLX_GPIO=%x\n", __func__, pv);
1418 }
1419 hc->hw.r_pcm_md0 |= V_PCM_MD;
1420 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1421 spin_unlock_irqrestore(&hc->lock, flags);
1422 set_current_state(TASK_UNINTERRUPTIBLE);
1423 schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1424 spin_lock_irqsave(&hc->lock, flags);
1425 val2 = HFC_inb(hc, R_F0_CNTL);
1426 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1427 if (debug & DEBUG_HFCMULTI_INIT)
1428 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1429 "10 ms (2nd try)\n", val2);
1430 if (val2 >= val+8) { /* 1 ms */
1431 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1432 &hc->chip);
1433 printk(KERN_INFO "controller is PCM bus MASTER "
1434 "(auto detected)\n");
1435 } else
1436 goto controller_fail;
1437 }
1438 }
1439
1440 /* Release the DSP Reset */
1441 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1442 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1443 plxsd_master = 1;
1444 spin_lock_irqsave(&plx_lock, plx_flags);
1445 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1446 pv = readl(plx_acc_32);
1447 pv |= PLX_DSP_RES_N;
1448 writel(pv, plx_acc_32);
1449 spin_unlock_irqrestore(&plx_lock, plx_flags);
1450 if (debug & DEBUG_HFCMULTI_INIT)
1451 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1452 __func__, pv);
1453 }
1454
1455 /* pcm id */
1456 if (hc->pcm)
1457 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1458 hc->pcm);
1459 else {
1460 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1461 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1462 PCM_cnt++; /* SD has proprietary bridging */
1463 }
1464 hc->pcm = PCM_cnt;
1465 printk(KERN_INFO "controller has PCM BUS ID %d "
1466 "(auto selected)\n", hc->pcm);
1467 }
1468
1469 /* set up timer */
1470 HFC_outb(hc, R_TI_WD, poll_timer);
1471 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1472
1473 /* set E1 state machine IRQ */
1474 if (hc->ctype == HFC_TYPE_E1)
1475 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1476
1477 /* set DTMF detection */
1478 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1479 if (debug & DEBUG_HFCMULTI_INIT)
1480 printk(KERN_DEBUG "%s: enabling DTMF detection "
1481 "for all B-channel\n", __func__);
1482 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1483 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1484 hc->hw.r_dtmf |= V_ULAW_SEL;
1485 HFC_outb(hc, R_DTMF_N, 102 - 1);
1486 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1487 }
1488
1489 /* conference engine */
1490 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1491 r_conf_en = V_CONF_EN | V_ULAW;
1492 else
1493 r_conf_en = V_CONF_EN;
1494 if (hc->ctype != HFC_TYPE_XHFC)
1495 HFC_outb(hc, R_CONF_EN, r_conf_en);
1496
1497 /* setting leds */
1498 switch (hc->leds) {
1499 case 1: /* HFC-E1 OEM */
1500 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1501 HFC_outb(hc, R_GPIO_SEL, 0x32);
1502 else
1503 HFC_outb(hc, R_GPIO_SEL, 0x30);
1504
1505 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1506 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1507
1508 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1509 break;
1510
1511 case 2: /* HFC-4S OEM */
1512 case 3:
1513 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1514 HFC_outb(hc, R_GPIO_EN1, 0xff);
1515 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1516 break;
1517 }
1518
1519 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1520 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1521 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1522 }
1523
1524 /* set master clock */
1525 if (hc->masterclk >= 0) {
1526 if (debug & DEBUG_HFCMULTI_INIT)
1527 printk(KERN_DEBUG "%s: setting ST master clock "
1528 "to port %d (0..%d)\n",
1529 __func__, hc->masterclk, hc->ports-1);
1530 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1531 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1532 }
1533
1534
1535
1536 /* setting misc irq */
1537 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1538 if (debug & DEBUG_HFCMULTI_INIT)
1539 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1540 hc->hw.r_irqmsk_misc);
1541
1542 /* RAM access test */
1543 HFC_outb(hc, R_RAM_ADDR0, 0);
1544 HFC_outb(hc, R_RAM_ADDR1, 0);
1545 HFC_outb(hc, R_RAM_ADDR2, 0);
1546 for (i = 0; i < 256; i++) {
1547 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1548 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1549 }
1550 for (i = 0; i < 256; i++) {
1551 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1552 HFC_inb_nodebug(hc, R_RAM_DATA);
1553 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1554 if (rval != ((i * 3) & 0xff)) {
1555 printk(KERN_DEBUG
1556 "addr:%x val:%x should:%x\n", i, rval,
1557 (i * 3) & 0xff);
1558 err++;
1559 }
1560 }
1561 if (err) {
1562 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1563 err = -EIO;
1564 goto out;
1565 }
1566
1567 if (debug & DEBUG_HFCMULTI_INIT)
1568 printk(KERN_DEBUG "%s: done\n", __func__);
1569 out:
1570 spin_unlock_irqrestore(&hc->lock, flags);
1571 return err;
1572 }
1573
1574
1575 /*
1576 * control the watchdog
1577 */
1578 static void
1579 hfcmulti_watchdog(struct hfc_multi *hc)
1580 {
1581 hc->wdcount++;
1582
1583 if (hc->wdcount > 10) {
1584 hc->wdcount = 0;
1585 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1586 V_GPIO_OUT3 : V_GPIO_OUT2;
1587
1588 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1589 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1590 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1591 }
1592 }
1593
1594
1595
1596 /*
1597 * output leds
1598 */
1599 static void
1600 hfcmulti_leds(struct hfc_multi *hc)
1601 {
1602 unsigned long lled;
1603 unsigned long leddw;
1604 int i, state, active, leds;
1605 struct dchannel *dch;
1606 int led[4];
1607
1608 hc->ledcount += poll;
1609 if (hc->ledcount > 4096) {
1610 hc->ledcount -= 4096;
1611 hc->ledstate = 0xAFFEAFFE;
1612 }
1613
1614 switch (hc->leds) {
1615 case 1: /* HFC-E1 OEM */
1616 /* 2 red blinking: NT mode deactivate
1617 * 2 red steady: TE mode deactivate
1618 * left green: L1 active
1619 * left red: frame sync, but no L1
1620 * right green: L2 active
1621 */
1622 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1623 if (hc->chan[hc->dslot].dch->dev.D.protocol
1624 != ISDN_P_NT_E1) {
1625 led[0] = 1;
1626 led[1] = 1;
1627 } else if (hc->ledcount>>11) {
1628 led[0] = 1;
1629 led[1] = 1;
1630 } else {
1631 led[0] = 0;
1632 led[1] = 0;
1633 }
1634 led[2] = 0;
1635 led[3] = 0;
1636 } else { /* with frame sync */
1637 /* TODO make it work */
1638 led[0] = 0;
1639 led[1] = 0;
1640 led[2] = 0;
1641 led[3] = 1;
1642 }
1643 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1644 /* leds are inverted */
1645 if (leds != (int)hc->ledstate) {
1646 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1647 hc->ledstate = leds;
1648 }
1649 break;
1650
1651 case 2: /* HFC-4S OEM */
1652 /* red blinking = PH_DEACTIVATE NT Mode
1653 * red steady = PH_DEACTIVATE TE Mode
1654 * green steady = PH_ACTIVATE
1655 */
1656 for (i = 0; i < 4; i++) {
1657 state = 0;
1658 active = -1;
1659 dch = hc->chan[(i << 2) | 2].dch;
1660 if (dch) {
1661 state = dch->state;
1662 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1663 active = 3;
1664 else
1665 active = 7;
1666 }
1667 if (state) {
1668 if (state == active) {
1669 led[i] = 1; /* led green */
1670 } else
1671 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1672 /* TE mode: led red */
1673 led[i] = 2;
1674 else
1675 if (hc->ledcount>>11)
1676 /* led red */
1677 led[i] = 2;
1678 else
1679 /* led off */
1680 led[i] = 0;
1681 } else
1682 led[i] = 0; /* led off */
1683 }
1684 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1685 leds = 0;
1686 for (i = 0; i < 4; i++) {
1687 if (led[i] == 1) {
1688 /*green*/
1689 leds |= (0x2 << (i * 2));
1690 } else if (led[i] == 2) {
1691 /*red*/
1692 leds |= (0x1 << (i * 2));
1693 }
1694 }
1695 if (leds != (int)hc->ledstate) {
1696 vpm_out(hc, 0, 0x1a8 + 3, leds);
1697 hc->ledstate = leds;
1698 }
1699 } else {
1700 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1701 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1702 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1703 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1704 if (leds != (int)hc->ledstate) {
1705 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1706 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1707 hc->ledstate = leds;
1708 }
1709 }
1710 break;
1711
1712 case 3: /* HFC 1S/2S Beronet */
1713 /* red blinking = PH_DEACTIVATE NT Mode
1714 * red steady = PH_DEACTIVATE TE Mode
1715 * green steady = PH_ACTIVATE
1716 */
1717 for (i = 0; i < 2; i++) {
1718 state = 0;
1719 active = -1;
1720 dch = hc->chan[(i << 2) | 2].dch;
1721 if (dch) {
1722 state = dch->state;
1723 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1724 active = 3;
1725 else
1726 active = 7;
1727 }
1728 if (state) {
1729 if (state == active) {
1730 led[i] = 1; /* led green */
1731 } else
1732 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1733 /* TE mode: led red */
1734 led[i] = 2;
1735 else
1736 if (hc->ledcount >> 11)
1737 /* led red */
1738 led[i] = 2;
1739 else
1740 /* led off */
1741 led[i] = 0;
1742 } else
1743 led[i] = 0; /* led off */
1744 }
1745
1746
1747 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1748 | ((led[1]&1)<<3);
1749 if (leds != (int)hc->ledstate) {
1750 HFC_outb_nodebug(hc, R_GPIO_EN1,
1751 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1752 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1753 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1754 hc->ledstate = leds;
1755 }
1756 break;
1757 case 8: /* HFC 8S+ Beronet */
1758 lled = 0;
1759
1760 for (i = 0; i < 8; i++) {
1761 state = 0;
1762 active = -1;
1763 dch = hc->chan[(i << 2) | 2].dch;
1764 if (dch) {
1765 state = dch->state;
1766 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1767 active = 3;
1768 else
1769 active = 7;
1770 }
1771 if (state) {
1772 if (state == active) {
1773 lled |= 0 << i;
1774 } else
1775 if (hc->ledcount >> 11)
1776 lled |= 0 << i;
1777 else
1778 lled |= 1 << i;
1779 } else
1780 lled |= 1 << i;
1781 }
1782 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1783 if (leddw != hc->ledstate) {
1784 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1785 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1786 /* was _io before */
1787 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1788 outw(0x4000, hc->pci_iobase + 4);
1789 outl(leddw, hc->pci_iobase);
1790 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1791 hc->ledstate = leddw;
1792 }
1793 break;
1794 }
1795 }
1796 /*
1797 * read dtmf coefficients
1798 */
1799
1800 static void
1801 hfcmulti_dtmf(struct hfc_multi *hc)
1802 {
1803 s32 *coeff;
1804 u_int mantissa;
1805 int co, ch;
1806 struct bchannel *bch = NULL;
1807 u8 exponent;
1808 int dtmf = 0;
1809 int addr;
1810 u16 w_float;
1811 struct sk_buff *skb;
1812 struct mISDNhead *hh;
1813
1814 if (debug & DEBUG_HFCMULTI_DTMF)
1815 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1816 for (ch = 0; ch <= 31; ch++) {
1817 /* only process enabled B-channels */
1818 bch = hc->chan[ch].bch;
1819 if (!bch)
1820 continue;
1821 if (!hc->created[hc->chan[ch].port])
1822 continue;
1823 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1824 continue;
1825 if (debug & DEBUG_HFCMULTI_DTMF)
1826 printk(KERN_DEBUG "%s: dtmf channel %d:",
1827 __func__, ch);
1828 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1829 dtmf = 1;
1830 for (co = 0; co < 8; co++) {
1831 /* read W(n-1) coefficient */
1832 addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1833 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1834 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1835 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1836 | V_ADDR_INC);
1837 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1838 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1839 if (debug & DEBUG_HFCMULTI_DTMF)
1840 printk(" %04x", w_float);
1841
1842 /* decode float (see chip doc) */
1843 mantissa = w_float & 0x0fff;
1844 if (w_float & 0x8000)
1845 mantissa |= 0xfffff000;
1846 exponent = (w_float>>12) & 0x7;
1847 if (exponent) {
1848 mantissa ^= 0x1000;
1849 mantissa <<= (exponent-1);
1850 }
1851
1852 /* store coefficient */
1853 coeff[co<<1] = mantissa;
1854
1855 /* read W(n) coefficient */
1856 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1857 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1858 if (debug & DEBUG_HFCMULTI_DTMF)
1859 printk(" %04x", w_float);
1860
1861 /* decode float (see chip doc) */
1862 mantissa = w_float & 0x0fff;
1863 if (w_float & 0x8000)
1864 mantissa |= 0xfffff000;
1865 exponent = (w_float>>12) & 0x7;
1866 if (exponent) {
1867 mantissa ^= 0x1000;
1868 mantissa <<= (exponent-1);
1869 }
1870
1871 /* store coefficient */
1872 coeff[(co<<1)|1] = mantissa;
1873 }
1874 if (debug & DEBUG_HFCMULTI_DTMF)
1875 printk(" DTMF ready %08x %08x %08x %08x "
1876 "%08x %08x %08x %08x\n",
1877 coeff[0], coeff[1], coeff[2], coeff[3],
1878 coeff[4], coeff[5], coeff[6], coeff[7]);
1879 hc->chan[ch].coeff_count++;
1880 if (hc->chan[ch].coeff_count == 8) {
1881 hc->chan[ch].coeff_count = 0;
1882 skb = mI_alloc_skb(512, GFP_ATOMIC);
1883 if (!skb) {
1884 printk(KERN_DEBUG "%s: No memory for skb\n",
1885 __func__);
1886 continue;
1887 }
1888 hh = mISDN_HEAD_P(skb);
1889 hh->prim = PH_CONTROL_IND;
1890 hh->id = DTMF_HFC_COEF;
1891 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1892 recv_Bchannel_skb(bch, skb);
1893 }
1894 }
1895
1896 /* restart DTMF processing */
1897 hc->dtmf = dtmf;
1898 if (dtmf)
1899 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1900 }
1901
1902
1903 /*
1904 * fill fifo as much as possible
1905 */
1906
1907 static void
1908 hfcmulti_tx(struct hfc_multi *hc, int ch)
1909 {
1910 int i, ii, temp, len = 0;
1911 int Zspace, z1, z2; /* must be int for calculation */
1912 int Fspace, f1, f2;
1913 u_char *d;
1914 int *txpending, slot_tx;
1915 struct bchannel *bch;
1916 struct dchannel *dch;
1917 struct sk_buff **sp = NULL;
1918 int *idxp;
1919
1920 bch = hc->chan[ch].bch;
1921 dch = hc->chan[ch].dch;
1922 if ((!dch) && (!bch))
1923 return;
1924
1925 txpending = &hc->chan[ch].txpending;
1926 slot_tx = hc->chan[ch].slot_tx;
1927 if (dch) {
1928 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1929 return;
1930 sp = &dch->tx_skb;
1931 idxp = &dch->tx_idx;
1932 } else {
1933 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1934 return;
1935 sp = &bch->tx_skb;
1936 idxp = &bch->tx_idx;
1937 }
1938 if (*sp)
1939 len = (*sp)->len;
1940
1941 if ((!len) && *txpending != 1)
1942 return; /* no data */
1943
1944 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1945 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1946 (hc->chan[ch].slot_rx < 0) &&
1947 (hc->chan[ch].slot_tx < 0))
1948 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1949 else
1950 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1951 HFC_wait_nodebug(hc);
1952
1953 if (*txpending == 2) {
1954 /* reset fifo */
1955 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1956 HFC_wait_nodebug(hc);
1957 HFC_outb(hc, A_SUBCH_CFG, 0);
1958 *txpending = 1;
1959 }
1960 next_frame:
1961 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1962 f1 = HFC_inb_nodebug(hc, A_F1);
1963 f2 = HFC_inb_nodebug(hc, A_F2);
1964 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1965 if (debug & DEBUG_HFCMULTI_FIFO)
1966 printk(KERN_DEBUG
1967 "%s(card %d): reread f2 because %d!=%d\n",
1968 __func__, hc->id + 1, temp, f2);
1969 f2 = temp; /* repeat until F2 is equal */
1970 }
1971 Fspace = f2 - f1 - 1;
1972 if (Fspace < 0)
1973 Fspace += hc->Flen;
1974 /*
1975 * Old FIFO handling doesn't give us the current Z2 read
1976 * pointer, so we cannot send the next frame before the fifo
1977 * is empty. It makes no difference except for a slightly
1978 * lower performance.
1979 */
1980 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1981 if (f1 != f2)
1982 Fspace = 0;
1983 else
1984 Fspace = 1;
1985 }
1986 /* one frame only for ST D-channels, to allow resending */
1987 if (hc->ctype != HFC_TYPE_E1 && dch) {
1988 if (f1 != f2)
1989 Fspace = 0;
1990 }
1991 /* F-counter full condition */
1992 if (Fspace == 0)
1993 return;
1994 }
1995 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1996 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1997 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1998 if (debug & DEBUG_HFCMULTI_FIFO)
1999 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2000 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2001 z2 = temp; /* repeat unti Z2 is equal */
2002 }
2003 hc->chan[ch].Zfill = z1 - z2;
2004 if (hc->chan[ch].Zfill < 0)
2005 hc->chan[ch].Zfill += hc->Zlen;
2006 Zspace = z2 - z1;
2007 if (Zspace <= 0)
2008 Zspace += hc->Zlen;
2009 Zspace -= 4; /* keep not too full, so pointers will not overrun */
2010 /* fill transparent data only to maxinum transparent load (minus 4) */
2011 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2012 Zspace = Zspace - hc->Zlen + hc->max_trans;
2013 if (Zspace <= 0) /* no space of 4 bytes */
2014 return;
2015
2016 /* if no data */
2017 if (!len) {
2018 if (z1 == z2) { /* empty */
2019 /* if done with FIFO audio data during PCM connection */
2020 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2021 *txpending && slot_tx >= 0) {
2022 if (debug & DEBUG_HFCMULTI_MODE)
2023 printk(KERN_DEBUG
2024 "%s: reconnecting PCM due to no "
2025 "more FIFO data: channel %d "
2026 "slot_tx %d\n",
2027 __func__, ch, slot_tx);
2028 /* connect slot */
2029 if (hc->ctype == HFC_TYPE_XHFC)
2030 HFC_outb(hc, A_CON_HDLC, 0xc0
2031 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2032 /* Enable FIFO, no interrupt */
2033 else
2034 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2035 V_HDLC_TRP | V_IFF);
2036 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2037 HFC_wait_nodebug(hc);
2038 if (hc->ctype == HFC_TYPE_XHFC)
2039 HFC_outb(hc, A_CON_HDLC, 0xc0
2040 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2041 /* Enable FIFO, no interrupt */
2042 else
2043 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2044 V_HDLC_TRP | V_IFF);
2045 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2046 HFC_wait_nodebug(hc);
2047 }
2048 *txpending = 0;
2049 }
2050 return; /* no data */
2051 }
2052
2053 /* "fill fifo if empty" feature */
2054 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2055 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2056 if (debug & DEBUG_HFCMULTI_FILL)
2057 printk(KERN_DEBUG "%s: buffer empty, so we have "
2058 "underrun\n", __func__);
2059 /* fill buffer, to prevent future underrun */
2060 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2061 Zspace -= (poll >> 1);
2062 }
2063
2064 /* if audio data and connected slot */
2065 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2066 && slot_tx >= 0) {
2067 if (debug & DEBUG_HFCMULTI_MODE)
2068 printk(KERN_DEBUG "%s: disconnecting PCM due to "
2069 "FIFO data: channel %d slot_tx %d\n",
2070 __func__, ch, slot_tx);
2071 /* disconnect slot */
2072 if (hc->ctype == HFC_TYPE_XHFC)
2073 HFC_outb(hc, A_CON_HDLC, 0x80
2074 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2075 /* Enable FIFO, no interrupt */
2076 else
2077 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2078 V_HDLC_TRP | V_IFF);
2079 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2080 HFC_wait_nodebug(hc);
2081 if (hc->ctype == HFC_TYPE_XHFC)
2082 HFC_outb(hc, A_CON_HDLC, 0x80
2083 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2084 /* Enable FIFO, no interrupt */
2085 else
2086 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2087 V_HDLC_TRP | V_IFF);
2088 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2089 HFC_wait_nodebug(hc);
2090 }
2091 *txpending = 1;
2092
2093 /* show activity */
2094 hc->activity[hc->chan[ch].port] = 1;
2095
2096 /* fill fifo to what we have left */
2097 ii = len;
2098 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2099 temp = 1;
2100 else
2101 temp = 0;
2102 i = *idxp;
2103 d = (*sp)->data + i;
2104 if (ii - i > Zspace)
2105 ii = Zspace + i;
2106 if (debug & DEBUG_HFCMULTI_FIFO)
2107 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2108 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2109 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2110 temp ? "HDLC" : "TRANS");
2111
2112 /* Have to prep the audio data */
2113 hc->write_fifo(hc, d, ii - i);
2114 hc->chan[ch].Zfill += ii - i;
2115 *idxp = ii;
2116
2117 /* if not all data has been written */
2118 if (ii != len) {
2119 /* NOTE: fifo is started by the calling function */
2120 return;
2121 }
2122
2123 /* if all data has been written, terminate frame */
2124 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2125 /* increment f-counter */
2126 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2127 HFC_wait_nodebug(hc);
2128 }
2129
2130 /* send confirm, since get_net_bframe will not do it with trans */
2131 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2132 confirm_Bsend(bch);
2133
2134 /* check for next frame */
2135 dev_kfree_skb(*sp);
2136 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2137 len = (*sp)->len;
2138 goto next_frame;
2139 }
2140 if (dch && get_next_dframe(dch)) {
2141 len = (*sp)->len;
2142 goto next_frame;
2143 }
2144
2145 /*
2146 * now we have no more data, so in case of transparent,
2147 * we set the last byte in fifo to 'silence' in case we will get
2148 * no more data at all. this prevents sending an undefined value.
2149 */
2150 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2151 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2152 }
2153
2154
2155 /* NOTE: only called if E1 card is in active state */
2156 static void
2157 hfcmulti_rx(struct hfc_multi *hc, int ch)
2158 {
2159 int temp;
2160 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2161 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2162 int again = 0;
2163 struct bchannel *bch;
2164 struct dchannel *dch;
2165 struct sk_buff *skb, **sp = NULL;
2166 int maxlen;
2167
2168 bch = hc->chan[ch].bch;
2169 dch = hc->chan[ch].dch;
2170 if ((!dch) && (!bch))
2171 return;
2172 if (dch) {
2173 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2174 return;
2175 sp = &dch->rx_skb;
2176 maxlen = dch->maxlen;
2177 } else {
2178 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2179 return;
2180 sp = &bch->rx_skb;
2181 maxlen = bch->maxlen;
2182 }
2183 next_frame:
2184 /* on first AND before getting next valid frame, R_FIFO must be written
2185 to. */
2186 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2187 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2188 (hc->chan[ch].slot_rx < 0) &&
2189 (hc->chan[ch].slot_tx < 0))
2190 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2191 else
2192 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2193 HFC_wait_nodebug(hc);
2194
2195 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2196 if (hc->chan[ch].rx_off)
2197 return;
2198
2199 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2200 f1 = HFC_inb_nodebug(hc, A_F1);
2201 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2202 if (debug & DEBUG_HFCMULTI_FIFO)
2203 printk(KERN_DEBUG
2204 "%s(card %d): reread f1 because %d!=%d\n",
2205 __func__, hc->id + 1, temp, f1);
2206 f1 = temp; /* repeat until F1 is equal */
2207 }
2208 f2 = HFC_inb_nodebug(hc, A_F2);
2209 }
2210 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2211 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2212 if (debug & DEBUG_HFCMULTI_FIFO)
2213 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2214 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2215 z1 = temp; /* repeat until Z1 is equal */
2216 }
2217 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2218 Zsize = z1 - z2;
2219 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2220 /* complete hdlc frame */
2221 Zsize++;
2222 if (Zsize < 0)
2223 Zsize += hc->Zlen;
2224 /* if buffer is empty */
2225 if (Zsize <= 0)
2226 return;
2227
2228 if (*sp == NULL) {
2229 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2230 if (*sp == NULL) {
2231 printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2232 __func__);
2233 return;
2234 }
2235 }
2236 /* show activity */
2237 hc->activity[hc->chan[ch].port] = 1;
2238
2239 /* empty fifo with what we have */
2240 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2241 if (debug & DEBUG_HFCMULTI_FIFO)
2242 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2243 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2244 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2245 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2246 f1, f2, Zsize + (*sp)->len, again);
2247 /* HDLC */
2248 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2249 if (debug & DEBUG_HFCMULTI_FIFO)
2250 printk(KERN_DEBUG
2251 "%s(card %d): hdlc-frame too large.\n",
2252 __func__, hc->id + 1);
2253 skb_trim(*sp, 0);
2254 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2255 HFC_wait_nodebug(hc);
2256 return;
2257 }
2258
2259 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2260
2261 if (f1 != f2) {
2262 /* increment Z2,F2-counter */
2263 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2264 HFC_wait_nodebug(hc);
2265 /* check size */
2266 if ((*sp)->len < 4) {
2267 if (debug & DEBUG_HFCMULTI_FIFO)
2268 printk(KERN_DEBUG
2269 "%s(card %d): Frame below minimum "
2270 "size\n", __func__, hc->id + 1);
2271 skb_trim(*sp, 0);
2272 goto next_frame;
2273 }
2274 /* there is at least one complete frame, check crc */
2275 if ((*sp)->data[(*sp)->len - 1]) {
2276 if (debug & DEBUG_HFCMULTI_CRC)
2277 printk(KERN_DEBUG
2278 "%s: CRC-error\n", __func__);
2279 skb_trim(*sp, 0);
2280 goto next_frame;
2281 }
2282 skb_trim(*sp, (*sp)->len - 3);
2283 if ((*sp)->len < MISDN_COPY_SIZE) {
2284 skb = *sp;
2285 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2286 if (*sp) {
2287 memcpy(skb_put(*sp, skb->len),
2288 skb->data, skb->len);
2289 skb_trim(skb, 0);
2290 } else {
2291 printk(KERN_DEBUG "%s: No mem\n",
2292 __func__);
2293 *sp = skb;
2294 skb = NULL;
2295 }
2296 } else {
2297 skb = NULL;
2298 }
2299 if (debug & DEBUG_HFCMULTI_FIFO) {
2300 printk(KERN_DEBUG "%s(card %d):",
2301 __func__, hc->id + 1);
2302 temp = 0;
2303 while (temp < (*sp)->len)
2304 printk(" %02x", (*sp)->data[temp++]);
2305 printk("\n");
2306 }
2307 if (dch)
2308 recv_Dchannel(dch);
2309 else
2310 recv_Bchannel(bch, MISDN_ID_ANY);
2311 *sp = skb;
2312 again++;
2313 goto next_frame;
2314 }
2315 /* there is an incomplete frame */
2316 } else {
2317 /* transparent */
2318 if (Zsize > skb_tailroom(*sp))
2319 Zsize = skb_tailroom(*sp);
2320 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2321 if (((*sp)->len) < MISDN_COPY_SIZE) {
2322 skb = *sp;
2323 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2324 if (*sp) {
2325 memcpy(skb_put(*sp, skb->len),
2326 skb->data, skb->len);
2327 skb_trim(skb, 0);
2328 } else {
2329 printk(KERN_DEBUG "%s: No mem\n", __func__);
2330 *sp = skb;
2331 skb = NULL;
2332 }
2333 } else {
2334 skb = NULL;
2335 }
2336 if (debug & DEBUG_HFCMULTI_FIFO)
2337 printk(KERN_DEBUG
2338 "%s(card %d): fifo(%d) reading %d bytes "
2339 "(z1=%04x, z2=%04x) TRANS\n",
2340 __func__, hc->id + 1, ch, Zsize, z1, z2);
2341 /* only bch is transparent */
2342 recv_Bchannel(bch, hc->chan[ch].Zfill);
2343 *sp = skb;
2344 }
2345 }
2346
2347
2348 /*
2349 * Interrupt handler
2350 */
2351 static void
2352 signal_state_up(struct dchannel *dch, int info, char *msg)
2353 {
2354 struct sk_buff *skb;
2355 int id, data = info;
2356
2357 if (debug & DEBUG_HFCMULTI_STATE)
2358 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2359
2360 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2361
2362 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2363 GFP_ATOMIC);
2364 if (!skb)
2365 return;
2366 recv_Dchannel_skb(dch, skb);
2367 }
2368
2369 static inline void
2370 handle_timer_irq(struct hfc_multi *hc)
2371 {
2372 int ch, temp;
2373 struct dchannel *dch;
2374 u_long flags;
2375
2376 /* process queued resync jobs */
2377 if (hc->e1_resync) {
2378 /* lock, so e1_resync gets not changed */
2379 spin_lock_irqsave(&HFClock, flags);
2380 if (hc->e1_resync & 1) {
2381 if (debug & DEBUG_HFCMULTI_PLXSD)
2382 printk(KERN_DEBUG "Enable SYNC_I\n");
2383 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2384 /* disable JATT, if RX_SYNC is set */
2385 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2386 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2387 }
2388 if (hc->e1_resync & 2) {
2389 if (debug & DEBUG_HFCMULTI_PLXSD)
2390 printk(KERN_DEBUG "Enable jatt PLL\n");
2391 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2392 }
2393 if (hc->e1_resync & 4) {
2394 if (debug & DEBUG_HFCMULTI_PLXSD)
2395 printk(KERN_DEBUG
2396 "Enable QUARTZ for HFC-E1\n");
2397 /* set jatt to quartz */
2398 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2399 | V_JATT_OFF);
2400 /* switch to JATT, in case it is not already */
2401 HFC_outb(hc, R_SYNC_OUT, 0);
2402 }
2403 hc->e1_resync = 0;
2404 spin_unlock_irqrestore(&HFClock, flags);
2405 }
2406
2407 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2408 for (ch = 0; ch <= 31; ch++) {
2409 if (hc->created[hc->chan[ch].port]) {
2410 hfcmulti_tx(hc, ch);
2411 /* fifo is started when switching to rx-fifo */
2412 hfcmulti_rx(hc, ch);
2413 if (hc->chan[ch].dch &&
2414 hc->chan[ch].nt_timer > -1) {
2415 dch = hc->chan[ch].dch;
2416 if (!(--hc->chan[ch].nt_timer)) {
2417 schedule_event(dch,
2418 FLG_PHCHANGE);
2419 if (debug &
2420 DEBUG_HFCMULTI_STATE)
2421 printk(KERN_DEBUG
2422 "%s: nt_timer at "
2423 "state %x\n",
2424 __func__,
2425 dch->state);
2426 }
2427 }
2428 }
2429 }
2430 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2431 dch = hc->chan[hc->dslot].dch;
2432 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2433 /* LOS */
2434 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2435 if (!temp && hc->chan[hc->dslot].los)
2436 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2437 "LOS detected");
2438 if (temp && !hc->chan[hc->dslot].los)
2439 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2440 "LOS gone");
2441 hc->chan[hc->dslot].los = temp;
2442 }
2443 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2444 /* AIS */
2445 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2446 if (!temp && hc->chan[hc->dslot].ais)
2447 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2448 "AIS detected");
2449 if (temp && !hc->chan[hc->dslot].ais)
2450 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2451 "AIS gone");
2452 hc->chan[hc->dslot].ais = temp;
2453 }
2454 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2455 /* SLIP */
2456 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2457 if (!temp && hc->chan[hc->dslot].slip_rx)
2458 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2459 " bit SLIP detected RX");
2460 hc->chan[hc->dslot].slip_rx = temp;
2461 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2462 if (!temp && hc->chan[hc->dslot].slip_tx)
2463 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2464 " bit SLIP detected TX");
2465 hc->chan[hc->dslot].slip_tx = temp;
2466 }
2467 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2468 /* RDI */
2469 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2470 if (!temp && hc->chan[hc->dslot].rdi)
2471 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2472 "RDI detected");
2473 if (temp && !hc->chan[hc->dslot].rdi)
2474 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2475 "RDI gone");
2476 hc->chan[hc->dslot].rdi = temp;
2477 }
2478 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2479 switch (hc->chan[hc->dslot].sync) {
2480 case 0:
2481 if ((temp & 0x60) == 0x60) {
2482 if (debug & DEBUG_HFCMULTI_SYNC)
2483 printk(KERN_DEBUG
2484 "%s: (id=%d) E1 now "
2485 "in clock sync\n",
2486 __func__, hc->id);
2487 HFC_outb(hc, R_RX_OFF,
2488 hc->chan[hc->dslot].jitter | V_RX_INIT);
2489 HFC_outb(hc, R_TX_OFF,
2490 hc->chan[hc->dslot].jitter | V_RX_INIT);
2491 hc->chan[hc->dslot].sync = 1;
2492 goto check_framesync;
2493 }
2494 break;
2495 case 1:
2496 if ((temp & 0x60) != 0x60) {
2497 if (debug & DEBUG_HFCMULTI_SYNC)
2498 printk(KERN_DEBUG
2499 "%s: (id=%d) E1 "
2500 "lost clock sync\n",
2501 __func__, hc->id);
2502 hc->chan[hc->dslot].sync = 0;
2503 break;
2504 }
2505 check_framesync:
2506 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2507 if (temp == 0x27) {
2508 if (debug & DEBUG_HFCMULTI_SYNC)
2509 printk(KERN_DEBUG
2510 "%s: (id=%d) E1 "
2511 "now in frame sync\n",
2512 __func__, hc->id);
2513 hc->chan[hc->dslot].sync = 2;
2514 }
2515 break;
2516 case 2:
2517 if ((temp & 0x60) != 0x60) {
2518 if (debug & DEBUG_HFCMULTI_SYNC)
2519 printk(KERN_DEBUG
2520 "%s: (id=%d) E1 lost "
2521 "clock & frame sync\n",
2522 __func__, hc->id);
2523 hc->chan[hc->dslot].sync = 0;
2524 break;
2525 }
2526 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2527 if (temp != 0x27) {
2528 if (debug & DEBUG_HFCMULTI_SYNC)
2529 printk(KERN_DEBUG
2530 "%s: (id=%d) E1 "
2531 "lost frame sync\n",
2532 __func__, hc->id);
2533 hc->chan[hc->dslot].sync = 1;
2534 }
2535 break;
2536 }
2537 }
2538
2539 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2540 hfcmulti_watchdog(hc);
2541
2542 if (hc->leds)
2543 hfcmulti_leds(hc);
2544 }
2545
2546 static void
2547 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2548 {
2549 struct dchannel *dch;
2550 int ch;
2551 int active;
2552 u_char st_status, temp;
2553
2554 /* state machine */
2555 for (ch = 0; ch <= 31; ch++) {
2556 if (hc->chan[ch].dch) {
2557 dch = hc->chan[ch].dch;
2558 if (r_irq_statech & 1) {
2559 HFC_outb_nodebug(hc, R_ST_SEL,
2560 hc->chan[ch].port);
2561 /* undocumented: delay after R_ST_SEL */
2562 udelay(1);
2563 /* undocumented: status changes during read */
2564 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2565 while (st_status != (temp =
2566 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2567 if (debug & DEBUG_HFCMULTI_STATE)
2568 printk(KERN_DEBUG "%s: reread "
2569 "STATE because %d!=%d\n",
2570 __func__, temp,
2571 st_status);
2572 st_status = temp; /* repeat */
2573 }
2574
2575 /* Speech Design TE-sync indication */
2576 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2577 dch->dev.D.protocol == ISDN_P_TE_S0) {
2578 if (st_status & V_FR_SYNC_ST)
2579 hc->syncronized |=
2580 (1 << hc->chan[ch].port);
2581 else
2582 hc->syncronized &=
2583 ~(1 << hc->chan[ch].port);
2584 }
2585 dch->state = st_status & 0x0f;
2586 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2587 active = 3;
2588 else
2589 active = 7;
2590 if (dch->state == active) {
2591 HFC_outb_nodebug(hc, R_FIFO,
2592 (ch << 1) | 1);
2593 HFC_wait_nodebug(hc);
2594 HFC_outb_nodebug(hc,
2595 R_INC_RES_FIFO, V_RES_F);
2596 HFC_wait_nodebug(hc);
2597 dch->tx_idx = 0;
2598 }
2599 schedule_event(dch, FLG_PHCHANGE);
2600 if (debug & DEBUG_HFCMULTI_STATE)
2601 printk(KERN_DEBUG
2602 "%s: S/T newstate %x port %d\n",
2603 __func__, dch->state,
2604 hc->chan[ch].port);
2605 }
2606 r_irq_statech >>= 1;
2607 }
2608 }
2609 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2610 plxsd_checksync(hc, 0);
2611 }
2612
2613 static void
2614 fifo_irq(struct hfc_multi *hc, int block)
2615 {
2616 int ch, j;
2617 struct dchannel *dch;
2618 struct bchannel *bch;
2619 u_char r_irq_fifo_bl;
2620
2621 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2622 j = 0;
2623 while (j < 8) {
2624 ch = (block << 2) + (j >> 1);
2625 dch = hc->chan[ch].dch;
2626 bch = hc->chan[ch].bch;
2627 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2628 j += 2;
2629 continue;
2630 }
2631 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2632 test_bit(FLG_ACTIVE, &dch->Flags)) {
2633 hfcmulti_tx(hc, ch);
2634 /* start fifo */
2635 HFC_outb_nodebug(hc, R_FIFO, 0);
2636 HFC_wait_nodebug(hc);
2637 }
2638 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2639 test_bit(FLG_ACTIVE, &bch->Flags)) {
2640 hfcmulti_tx(hc, ch);
2641 /* start fifo */
2642 HFC_outb_nodebug(hc, R_FIFO, 0);
2643 HFC_wait_nodebug(hc);
2644 }
2645 j++;
2646 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2647 test_bit(FLG_ACTIVE, &dch->Flags)) {
2648 hfcmulti_rx(hc, ch);
2649 }
2650 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2651 test_bit(FLG_ACTIVE, &bch->Flags)) {
2652 hfcmulti_rx(hc, ch);
2653 }
2654 j++;
2655 }
2656 }
2657
2658 #ifdef IRQ_DEBUG
2659 int irqsem;
2660 #endif
2661 static irqreturn_t
2662 hfcmulti_interrupt(int intno, void *dev_id)
2663 {
2664 #ifdef IRQCOUNT_DEBUG
2665 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2666 iq5 = 0, iq6 = 0, iqcnt = 0;
2667 #endif
2668 struct hfc_multi *hc = dev_id;
2669 struct dchannel *dch;
2670 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2671 int i;
2672 void __iomem *plx_acc;
2673 u_short wval;
2674 u_char e1_syncsta, temp;
2675 u_long flags;
2676
2677 if (!hc) {
2678 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2679 return IRQ_NONE;
2680 }
2681
2682 spin_lock(&hc->lock);
2683
2684 #ifdef IRQ_DEBUG
2685 if (irqsem)
2686 printk(KERN_ERR "irq for card %d during irq from "
2687 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2688 irqsem = hc->id + 1;
2689 #endif
2690 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2691 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2692 goto irq_notforus;
2693 #endif
2694 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2695 spin_lock_irqsave(&plx_lock, flags);
2696 plx_acc = hc->plx_membase + PLX_INTCSR;
2697 wval = readw(plx_acc);
2698 spin_unlock_irqrestore(&plx_lock, flags);
2699 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2700 goto irq_notforus;
2701 }
2702
2703 status = HFC_inb_nodebug(hc, R_STATUS);
2704 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2705 #ifdef IRQCOUNT_DEBUG
2706 if (r_irq_statech)
2707 iq1++;
2708 if (status & V_DTMF_STA)
2709 iq2++;
2710 if (status & V_LOST_STA)
2711 iq3++;
2712 if (status & V_EXT_IRQSTA)
2713 iq4++;
2714 if (status & V_MISC_IRQSTA)
2715 iq5++;
2716 if (status & V_FR_IRQSTA)
2717 iq6++;
2718 if (iqcnt++ > 5000) {
2719 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2720 iq1, iq2, iq3, iq4, iq5, iq6);
2721 iqcnt = 0;
2722 }
2723 #endif
2724
2725 if (!r_irq_statech &&
2726 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2727 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2728 /* irq is not for us */
2729 goto irq_notforus;
2730 }
2731 hc->irqcnt++;
2732 if (r_irq_statech) {
2733 if (hc->ctype != HFC_TYPE_E1)
2734 ph_state_irq(hc, r_irq_statech);
2735 }
2736 if (status & V_EXT_IRQSTA)
2737 ; /* external IRQ */
2738 if (status & V_LOST_STA) {
2739 /* LOST IRQ */
2740 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2741 }
2742 if (status & V_MISC_IRQSTA) {
2743 /* misc IRQ */
2744 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2745 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2746 if (r_irq_misc & V_STA_IRQ) {
2747 if (hc->ctype == HFC_TYPE_E1) {
2748 /* state machine */
2749 dch = hc->chan[hc->dslot].dch;
2750 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2751 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2752 && hc->e1_getclock) {
2753 if (e1_syncsta & V_FR_SYNC_E1)
2754 hc->syncronized = 1;
2755 else
2756 hc->syncronized = 0;
2757 }
2758 /* undocumented: status changes during read */
2759 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2760 while (dch->state != (temp =
2761 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2762 if (debug & DEBUG_HFCMULTI_STATE)
2763 printk(KERN_DEBUG "%s: reread "
2764 "STATE because %d!=%d\n",
2765 __func__, temp,
2766 dch->state);
2767 dch->state = temp; /* repeat */
2768 }
2769 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2770 & 0x7;
2771 schedule_event(dch, FLG_PHCHANGE);
2772 if (debug & DEBUG_HFCMULTI_STATE)
2773 printk(KERN_DEBUG
2774 "%s: E1 (id=%d) newstate %x\n",
2775 __func__, hc->id, dch->state);
2776 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2777 plxsd_checksync(hc, 0);
2778 }
2779 }
2780 if (r_irq_misc & V_TI_IRQ) {
2781 if (hc->iclock_on)
2782 mISDN_clock_update(hc->iclock, poll, NULL);
2783 handle_timer_irq(hc);
2784 }
2785
2786 if (r_irq_misc & V_DTMF_IRQ)
2787 hfcmulti_dtmf(hc);
2788
2789 if (r_irq_misc & V_IRQ_PROC) {
2790 static int irq_proc_cnt;
2791 if (!irq_proc_cnt++)
2792 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2793 " this should not happen\n", __func__);
2794 }
2795
2796 }
2797 if (status & V_FR_IRQSTA) {
2798 /* FIFO IRQ */
2799 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2800 for (i = 0; i < 8; i++) {
2801 if (r_irq_oview & (1 << i))
2802 fifo_irq(hc, i);
2803 }
2804 }
2805
2806 #ifdef IRQ_DEBUG
2807 irqsem = 0;
2808 #endif
2809 spin_unlock(&hc->lock);
2810 return IRQ_HANDLED;
2811
2812 irq_notforus:
2813 #ifdef IRQ_DEBUG
2814 irqsem = 0;
2815 #endif
2816 spin_unlock(&hc->lock);
2817 return IRQ_NONE;
2818 }
2819
2820
2821 /*
2822 * timer callback for D-chan busy resolution. Currently no function
2823 */
2824
2825 static void
2826 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2827 {
2828 }
2829
2830
2831 /*
2832 * activate/deactivate hardware for selected channels and mode
2833 *
2834 * configure B-channel with the given protocol
2835 * ch eqals to the HFC-channel (0-31)
2836 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2837 * for S/T, 1-31 for E1)
2838 * the hdlc interrupts will be set/unset
2839 */
2840 static int
2841 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2842 int bank_tx, int slot_rx, int bank_rx)
2843 {
2844 int flow_tx = 0, flow_rx = 0, routing = 0;
2845 int oslot_tx, oslot_rx;
2846 int conf;
2847
2848 if (ch < 0 || ch > 31)
2849 return -EINVAL;
2850 oslot_tx = hc->chan[ch].slot_tx;
2851 oslot_rx = hc->chan[ch].slot_rx;
2852 conf = hc->chan[ch].conf;
2853
2854 if (debug & DEBUG_HFCMULTI_MODE)
2855 printk(KERN_DEBUG
2856 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2857 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2858 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2859 bank_tx, oslot_rx, slot_rx, bank_rx);
2860
2861 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2862 /* remove from slot */
2863 if (debug & DEBUG_HFCMULTI_MODE)
2864 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2865 __func__, oslot_tx);
2866 if (hc->slot_owner[oslot_tx<<1] == ch) {
2867 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2868 HFC_outb(hc, A_SL_CFG, 0);
2869 if (hc->ctype != HFC_TYPE_XHFC)
2870 HFC_outb(hc, A_CONF, 0);
2871 hc->slot_owner[oslot_tx<<1] = -1;
2872 } else {
2873 if (debug & DEBUG_HFCMULTI_MODE)
2874 printk(KERN_DEBUG
2875 "%s: we are not owner of this tx slot "
2876 "anymore, channel %d is.\n",
2877 __func__, hc->slot_owner[oslot_tx<<1]);
2878 }
2879 }
2880
2881 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2882 /* remove from slot */
2883 if (debug & DEBUG_HFCMULTI_MODE)
2884 printk(KERN_DEBUG
2885 "%s: remove from slot %d (RX)\n",
2886 __func__, oslot_rx);
2887 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2888 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2889 HFC_outb(hc, A_SL_CFG, 0);
2890 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2891 } else {
2892 if (debug & DEBUG_HFCMULTI_MODE)
2893 printk(KERN_DEBUG
2894 "%s: we are not owner of this rx slot "
2895 "anymore, channel %d is.\n",
2896 __func__,
2897 hc->slot_owner[(oslot_rx << 1) | 1]);
2898 }
2899 }
2900
2901 if (slot_tx < 0) {
2902 flow_tx = 0x80; /* FIFO->ST */
2903 /* disable pcm slot */
2904 hc->chan[ch].slot_tx = -1;
2905 hc->chan[ch].bank_tx = 0;
2906 } else {
2907 /* set pcm slot */
2908 if (hc->chan[ch].txpending)
2909 flow_tx = 0x80; /* FIFO->ST */
2910 else
2911 flow_tx = 0xc0; /* PCM->ST */
2912 /* put on slot */
2913 routing = bank_tx ? 0xc0 : 0x80;
2914 if (conf >= 0 || bank_tx > 1)
2915 routing = 0x40; /* loop */
2916 if (debug & DEBUG_HFCMULTI_MODE)
2917 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2918 " %d flow %02x routing %02x conf %d (TX)\n",
2919 __func__, ch, slot_tx, bank_tx,
2920 flow_tx, routing, conf);
2921 HFC_outb(hc, R_SLOT, slot_tx << 1);
2922 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2923 if (hc->ctype != HFC_TYPE_XHFC)
2924 HFC_outb(hc, A_CONF,
2925 (conf < 0) ? 0 : (conf | V_CONF_SL));
2926 hc->slot_owner[slot_tx << 1] = ch;
2927 hc->chan[ch].slot_tx = slot_tx;
2928 hc->chan[ch].bank_tx = bank_tx;
2929 }
2930 if (slot_rx < 0) {
2931 /* disable pcm slot */
2932 flow_rx = 0x80; /* ST->FIFO */
2933 hc->chan[ch].slot_rx = -1;
2934 hc->chan[ch].bank_rx = 0;
2935 } else {
2936 /* set pcm slot */
2937 if (hc->chan[ch].txpending)
2938 flow_rx = 0x80; /* ST->FIFO */
2939 else
2940 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2941 /* put on slot */
2942 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2943 if (conf >= 0 || bank_rx > 1)
2944 routing = 0x40; /* loop */
2945 if (debug & DEBUG_HFCMULTI_MODE)
2946 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2947 " %d flow %02x routing %02x conf %d (RX)\n",
2948 __func__, ch, slot_rx, bank_rx,
2949 flow_rx, routing, conf);
2950 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2951 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2952 hc->slot_owner[(slot_rx<<1)|1] = ch;
2953 hc->chan[ch].slot_rx = slot_rx;
2954 hc->chan[ch].bank_rx = bank_rx;
2955 }
2956
2957 switch (protocol) {
2958 case (ISDN_P_NONE):
2959 /* disable TX fifo */
2960 HFC_outb(hc, R_FIFO, ch << 1);
2961 HFC_wait(hc);
2962 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2963 HFC_outb(hc, A_SUBCH_CFG, 0);
2964 HFC_outb(hc, A_IRQ_MSK, 0);
2965 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2966 HFC_wait(hc);
2967 /* disable RX fifo */
2968 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2969 HFC_wait(hc);
2970 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2971 HFC_outb(hc, A_SUBCH_CFG, 0);
2972 HFC_outb(hc, A_IRQ_MSK, 0);
2973 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2974 HFC_wait(hc);
2975 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2976 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2977 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
2978 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2979 /* undocumented: delay after R_ST_SEL */
2980 udelay(1);
2981 HFC_outb(hc, A_ST_CTRL0,
2982 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2983 }
2984 if (hc->chan[ch].bch) {
2985 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2986 test_and_clear_bit(FLG_TRANSPARENT,
2987 &hc->chan[ch].bch->Flags);
2988 }
2989 break;
2990 case (ISDN_P_B_RAW): /* B-channel */
2991
2992 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2993 (hc->chan[ch].slot_rx < 0) &&
2994 (hc->chan[ch].slot_tx < 0)) {
2995
2996 printk(KERN_DEBUG
2997 "Setting B-channel %d to echo cancelable "
2998 "state on PCM slot %d\n", ch,
2999 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3000 printk(KERN_DEBUG
3001 "Enabling pass through for channel\n");
3002 vpm_out(hc, ch, ((ch / 4) * 8) +
3003 ((ch % 4) * 4) + 1, 0x01);
3004 /* rx path */
3005 /* S/T -> PCM */
3006 HFC_outb(hc, R_FIFO, (ch << 1));
3007 HFC_wait(hc);
3008 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3009 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3010 ((ch % 4) * 4) + 1) << 1);
3011 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3012
3013 /* PCM -> FIFO */
3014 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3015 HFC_wait(hc);
3016 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3017 HFC_outb(hc, A_SUBCH_CFG, 0);
3018 HFC_outb(hc, A_IRQ_MSK, 0);
3019 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3020 HFC_wait(hc);
3021 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3022 ((ch % 4) * 4) + 1) << 1) | 1);
3023 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3024
3025 /* tx path */
3026 /* PCM -> S/T */
3027 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3028 HFC_wait(hc);
3029 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3030 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3031 ((ch % 4) * 4)) << 1) | 1);
3032 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3033
3034 /* FIFO -> PCM */
3035 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3036 HFC_wait(hc);
3037 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3038 HFC_outb(hc, A_SUBCH_CFG, 0);
3039 HFC_outb(hc, A_IRQ_MSK, 0);
3040 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3041 HFC_wait(hc);
3042 /* tx silence */
3043 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3044 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3045 ((ch % 4) * 4)) << 1);
3046 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3047 } else {
3048 /* enable TX fifo */
3049 HFC_outb(hc, R_FIFO, ch << 1);
3050 HFC_wait(hc);
3051 if (hc->ctype == HFC_TYPE_XHFC)
3052 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3053 V_HDLC_TRP | V_IFF);
3054 /* Enable FIFO, no interrupt */
3055 else
3056 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3057 V_HDLC_TRP | V_IFF);
3058 HFC_outb(hc, A_SUBCH_CFG, 0);
3059 HFC_outb(hc, A_IRQ_MSK, 0);
3060 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3061 HFC_wait(hc);
3062 /* tx silence */
3063 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3064 /* enable RX fifo */
3065 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3066 HFC_wait(hc);
3067 if (hc->ctype == HFC_TYPE_XHFC)
3068 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3069 V_HDLC_TRP);
3070 /* Enable FIFO, no interrupt*/
3071 else
3072 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3073 V_HDLC_TRP);
3074 HFC_outb(hc, A_SUBCH_CFG, 0);
3075 HFC_outb(hc, A_IRQ_MSK, 0);
3076 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3077 HFC_wait(hc);
3078 }
3079 if (hc->ctype != HFC_TYPE_E1) {
3080 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3081 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3082 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3083 /* undocumented: delay after R_ST_SEL */
3084 udelay(1);
3085 HFC_outb(hc, A_ST_CTRL0,
3086 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3087 }
3088 if (hc->chan[ch].bch)
3089 test_and_set_bit(FLG_TRANSPARENT,
3090 &hc->chan[ch].bch->Flags);
3091 break;
3092 case (ISDN_P_B_HDLC): /* B-channel */
3093 case (ISDN_P_TE_S0): /* D-channel */
3094 case (ISDN_P_NT_S0):
3095 case (ISDN_P_TE_E1):
3096 case (ISDN_P_NT_E1):
3097 /* enable TX fifo */
3098 HFC_outb(hc, R_FIFO, ch<<1);
3099 HFC_wait(hc);
3100 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3101 /* E1 or B-channel */
3102 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3103 HFC_outb(hc, A_SUBCH_CFG, 0);
3104 } else {
3105 /* D-Channel without HDLC fill flags */
3106 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3107 HFC_outb(hc, A_SUBCH_CFG, 2);
3108 }
3109 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3110 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3111 HFC_wait(hc);
3112 /* enable RX fifo */
3113 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3114 HFC_wait(hc);
3115 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3116 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3117 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3118 else
3119 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3120 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3121 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3122 HFC_wait(hc);
3123 if (hc->chan[ch].bch) {
3124 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3125 if (hc->ctype != HFC_TYPE_E1) {
3126 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3127 ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3128 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3129 /* undocumented: delay after R_ST_SEL */
3130 udelay(1);
3131 HFC_outb(hc, A_ST_CTRL0,
3132 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3133 }
3134 }
3135 break;
3136 default:
3137 printk(KERN_DEBUG "%s: protocol not known %x\n",
3138 __func__, protocol);
3139 hc->chan[ch].protocol = ISDN_P_NONE;
3140 return -ENOPROTOOPT;
3141 }
3142 hc->chan[ch].protocol = protocol;
3143 return 0;
3144 }
3145
3146
3147 /*
3148 * connect/disconnect PCM
3149 */
3150
3151 static void
3152 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3153 int slot_rx, int bank_rx)
3154 {
3155 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3156 /* disable PCM */
3157 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3158 return;
3159 }
3160
3161 /* enable pcm */
3162 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3163 slot_rx, bank_rx);
3164 }
3165
3166 /*
3167 * set/disable conference
3168 */
3169
3170 static void
3171 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3172 {
3173 if (num >= 0 && num <= 7)
3174 hc->chan[ch].conf = num;
3175 else
3176 hc->chan[ch].conf = -1;
3177 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3178 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3179 hc->chan[ch].bank_rx);
3180 }
3181
3182
3183 /*
3184 * set/disable sample loop
3185 */
3186
3187 /* NOTE: this function is experimental and therefore disabled */
3188
3189 /*
3190 * Layer 1 callback function
3191 */
3192 static int
3193 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3194 {
3195 struct hfc_multi *hc = dch->hw;
3196 u_long flags;
3197
3198 switch (cmd) {
3199 case INFO3_P8:
3200 case INFO3_P10:
3201 break;
3202 case HW_RESET_REQ:
3203 /* start activation */
3204 spin_lock_irqsave(&hc->lock, flags);
3205 if (hc->ctype == HFC_TYPE_E1) {
3206 if (debug & DEBUG_HFCMULTI_MSG)
3207 printk(KERN_DEBUG
3208 "%s: HW_RESET_REQ no BRI\n",
3209 __func__);
3210 } else {
3211 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3212 /* undocumented: delay after R_ST_SEL */
3213 udelay(1);
3214 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3215 udelay(6); /* wait at least 5,21us */
3216 HFC_outb(hc, A_ST_WR_STATE, 3);
3217 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3218 /* activate */
3219 }
3220 spin_unlock_irqrestore(&hc->lock, flags);
3221 l1_event(dch->l1, HW_POWERUP_IND);
3222 break;
3223 case HW_DEACT_REQ:
3224 /* start deactivation */
3225 spin_lock_irqsave(&hc->lock, flags);
3226 if (hc->ctype == HFC_TYPE_E1) {
3227 if (debug & DEBUG_HFCMULTI_MSG)
3228 printk(KERN_DEBUG
3229 "%s: HW_DEACT_REQ no BRI\n",
3230 __func__);
3231 } else {
3232 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3233 /* undocumented: delay after R_ST_SEL */
3234 udelay(1);
3235 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3236 /* deactivate */
3237 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3238 hc->syncronized &=
3239 ~(1 << hc->chan[dch->slot].port);
3240 plxsd_checksync(hc, 0);
3241 }
3242 }
3243 skb_queue_purge(&dch->squeue);
3244 if (dch->tx_skb) {
3245 dev_kfree_skb(dch->tx_skb);
3246 dch->tx_skb = NULL;
3247 }
3248 dch->tx_idx = 0;
3249 if (dch->rx_skb) {
3250 dev_kfree_skb(dch->rx_skb);
3251 dch->rx_skb = NULL;
3252 }
3253 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3254 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3255 del_timer(&dch->timer);
3256 spin_unlock_irqrestore(&hc->lock, flags);
3257 break;
3258 case HW_POWERUP_REQ:
3259 spin_lock_irqsave(&hc->lock, flags);
3260 if (hc->ctype == HFC_TYPE_E1) {
3261 if (debug & DEBUG_HFCMULTI_MSG)
3262 printk(KERN_DEBUG
3263 "%s: HW_POWERUP_REQ no BRI\n",
3264 __func__);
3265 } else {
3266 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3267 /* undocumented: delay after R_ST_SEL */
3268 udelay(1);
3269 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3270 udelay(6); /* wait at least 5,21us */
3271 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3272 }
3273 spin_unlock_irqrestore(&hc->lock, flags);
3274 break;
3275 case PH_ACTIVATE_IND:
3276 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3277 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3278 GFP_ATOMIC);
3279 break;
3280 case PH_DEACTIVATE_IND:
3281 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3282 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3283 GFP_ATOMIC);
3284 break;
3285 default:
3286 if (dch->debug & DEBUG_HW)
3287 printk(KERN_DEBUG "%s: unknown command %x\n",
3288 __func__, cmd);
3289 return -1;
3290 }
3291 return 0;
3292 }
3293
3294 /*
3295 * Layer2 -> Layer 1 Transfer
3296 */
3297
3298 static int
3299 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3300 {
3301 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3302 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3303 struct hfc_multi *hc = dch->hw;
3304 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3305 int ret = -EINVAL;
3306 unsigned int id;
3307 u_long flags;
3308
3309 switch (hh->prim) {
3310 case PH_DATA_REQ:
3311 if (skb->len < 1)
3312 break;
3313 spin_lock_irqsave(&hc->lock, flags);
3314 ret = dchannel_senddata(dch, skb);
3315 if (ret > 0) { /* direct TX */
3316 id = hh->id; /* skb can be freed */
3317 hfcmulti_tx(hc, dch->slot);
3318 ret = 0;
3319 /* start fifo */
3320 HFC_outb(hc, R_FIFO, 0);
3321 HFC_wait(hc);
3322 spin_unlock_irqrestore(&hc->lock, flags);
3323 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3324 } else
3325 spin_unlock_irqrestore(&hc->lock, flags);
3326 return ret;
3327 case PH_ACTIVATE_REQ:
3328 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3329 spin_lock_irqsave(&hc->lock, flags);
3330 ret = 0;
3331 if (debug & DEBUG_HFCMULTI_MSG)
3332 printk(KERN_DEBUG
3333 "%s: PH_ACTIVATE port %d (0..%d)\n",
3334 __func__, hc->chan[dch->slot].port,
3335 hc->ports-1);
3336 /* start activation */
3337 if (hc->ctype == HFC_TYPE_E1) {
3338 ph_state_change(dch);
3339 if (debug & DEBUG_HFCMULTI_STATE)
3340 printk(KERN_DEBUG
3341 "%s: E1 report state %x \n",
3342 __func__, dch->state);
3343 } else {
3344 HFC_outb(hc, R_ST_SEL,
3345 hc->chan[dch->slot].port);
3346 /* undocumented: delay after R_ST_SEL */
3347 udelay(1);
3348 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3349 /* G1 */
3350 udelay(6); /* wait at least 5,21us */
3351 HFC_outb(hc, A_ST_WR_STATE, 1);
3352 HFC_outb(hc, A_ST_WR_STATE, 1 |
3353 (V_ST_ACT*3)); /* activate */
3354 dch->state = 1;
3355 }
3356 spin_unlock_irqrestore(&hc->lock, flags);
3357 } else
3358 ret = l1_event(dch->l1, hh->prim);
3359 break;
3360 case PH_DEACTIVATE_REQ:
3361 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3362 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3363 spin_lock_irqsave(&hc->lock, flags);
3364 if (debug & DEBUG_HFCMULTI_MSG)
3365 printk(KERN_DEBUG
3366 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3367 __func__, hc->chan[dch->slot].port,
3368 hc->ports-1);
3369 /* start deactivation */
3370 if (hc->ctype == HFC_TYPE_E1) {
3371 if (debug & DEBUG_HFCMULTI_MSG)
3372 printk(KERN_DEBUG
3373 "%s: PH_DEACTIVATE no BRI\n",
3374 __func__);
3375 } else {
3376 HFC_outb(hc, R_ST_SEL,
3377 hc->chan[dch->slot].port);
3378 /* undocumented: delay after R_ST_SEL */
3379 udelay(1);
3380 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3381 /* deactivate */
3382 dch->state = 1;
3383 }
3384 skb_queue_purge(&dch->squeue);
3385 if (dch->tx_skb) {
3386 dev_kfree_skb(dch->tx_skb);
3387 dch->tx_skb = NULL;
3388 }
3389 dch->tx_idx = 0;
3390 if (dch->rx_skb) {
3391 dev_kfree_skb(dch->rx_skb);
3392 dch->rx_skb = NULL;
3393 }
3394 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3395 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3396 del_timer(&dch->timer);
3397 #ifdef FIXME
3398 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3399 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3400 #endif
3401 ret = 0;
3402 spin_unlock_irqrestore(&hc->lock, flags);
3403 } else
3404 ret = l1_event(dch->l1, hh->prim);
3405 break;
3406 }
3407 if (!ret)
3408 dev_kfree_skb(skb);
3409 return ret;
3410 }
3411
3412 static void
3413 deactivate_bchannel(struct bchannel *bch)
3414 {
3415 struct hfc_multi *hc = bch->hw;
3416 u_long flags;
3417
3418 spin_lock_irqsave(&hc->lock, flags);
3419 mISDN_clear_bchannel(bch);
3420 hc->chan[bch->slot].coeff_count = 0;
3421 hc->chan[bch->slot].rx_off = 0;
3422 hc->chan[bch->slot].conf = -1;
3423 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3424 spin_unlock_irqrestore(&hc->lock, flags);
3425 }
3426
3427 static int
3428 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3429 {
3430 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3431 struct hfc_multi *hc = bch->hw;
3432 int ret = -EINVAL;
3433 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3434 unsigned int id;
3435 u_long flags;
3436
3437 switch (hh->prim) {
3438 case PH_DATA_REQ:
3439 if (!skb->len)
3440 break;
3441 spin_lock_irqsave(&hc->lock, flags);
3442 ret = bchannel_senddata(bch, skb);
3443 if (ret > 0) { /* direct TX */
3444 id = hh->id; /* skb can be freed */
3445 hfcmulti_tx(hc, bch->slot);
3446 ret = 0;
3447 /* start fifo */
3448 HFC_outb_nodebug(hc, R_FIFO, 0);
3449 HFC_wait_nodebug(hc);
3450 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3451 spin_unlock_irqrestore(&hc->lock, flags);
3452 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3453 } else
3454 spin_unlock_irqrestore(&hc->lock, flags);
3455 } else
3456 spin_unlock_irqrestore(&hc->lock, flags);
3457 return ret;
3458 case PH_ACTIVATE_REQ:
3459 if (debug & DEBUG_HFCMULTI_MSG)
3460 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3461 __func__, bch->slot);
3462 spin_lock_irqsave(&hc->lock, flags);
3463 /* activate B-channel if not already activated */
3464 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3465 hc->chan[bch->slot].txpending = 0;
3466 ret = mode_hfcmulti(hc, bch->slot,
3467 ch->protocol,
3468 hc->chan[bch->slot].slot_tx,
3469 hc->chan[bch->slot].bank_tx,
3470 hc->chan[bch->slot].slot_rx,
3471 hc->chan[bch->slot].bank_rx);
3472 if (!ret) {
3473 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3474 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3475 /* start decoder */
3476 hc->dtmf = 1;
3477 if (debug & DEBUG_HFCMULTI_DTMF)
3478 printk(KERN_DEBUG
3479 "%s: start dtmf decoder\n",
3480 __func__);
3481 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3482 V_RST_DTMF);
3483 }
3484 }
3485 } else
3486 ret = 0;
3487 spin_unlock_irqrestore(&hc->lock, flags);
3488 if (!ret)
3489 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3490 GFP_KERNEL);
3491 break;
3492 case PH_CONTROL_REQ:
3493 spin_lock_irqsave(&hc->lock, flags);
3494 switch (hh->id) {
3495 case HFC_SPL_LOOP_ON: /* set sample loop */
3496 if (debug & DEBUG_HFCMULTI_MSG)
3497 printk(KERN_DEBUG
3498 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3499 __func__, skb->len);
3500 ret = 0;
3501 break;
3502 case HFC_SPL_LOOP_OFF: /* set silence */
3503 if (debug & DEBUG_HFCMULTI_MSG)
3504 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3505 __func__);
3506 ret = 0;
3507 break;
3508 default:
3509 printk(KERN_ERR
3510 "%s: unknown PH_CONTROL_REQ info %x\n",
3511 __func__, hh->id);
3512 ret = -EINVAL;
3513 }
3514 spin_unlock_irqrestore(&hc->lock, flags);
3515 break;
3516 case PH_DEACTIVATE_REQ:
3517 deactivate_bchannel(bch); /* locked there */
3518 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3519 GFP_KERNEL);
3520 ret = 0;
3521 break;
3522 }
3523 if (!ret)
3524 dev_kfree_skb(skb);
3525 return ret;
3526 }
3527
3528 /*
3529 * bchannel control function
3530 */
3531 static int
3532 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3533 {
3534 int ret = 0;
3535 struct dsp_features *features =
3536 (struct dsp_features *)(*((u_long *)&cq->p1));
3537 struct hfc_multi *hc = bch->hw;
3538 int slot_tx;
3539 int bank_tx;
3540 int slot_rx;
3541 int bank_rx;
3542 int num;
3543
3544 switch (cq->op) {
3545 case MISDN_CTRL_GETOP:
3546 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3547 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3548 break;
3549 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3550 hc->chan[bch->slot].rx_off = !!cq->p1;
3551 if (!hc->chan[bch->slot].rx_off) {
3552 /* reset fifo on rx on */
3553 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3554 HFC_wait_nodebug(hc);
3555 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3556 HFC_wait_nodebug(hc);
3557 }
3558 if (debug & DEBUG_HFCMULTI_MSG)
3559 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3560 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3561 break;
3562 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3563 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3564 if (debug & DEBUG_HFCMULTI_MSG)
3565 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3566 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3567 break;
3568 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3569 if (debug & DEBUG_HFCMULTI_MSG)
3570 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3571 __func__);
3572 /* create confirm */
3573 features->hfc_id = hc->id;
3574 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3575 features->hfc_dtmf = 1;
3576 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3577 features->hfc_conf = 1;
3578 features->hfc_loops = 0;
3579 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3580 features->hfc_echocanhw = 1;
3581 } else {
3582 features->pcm_id = hc->pcm;
3583 features->pcm_slots = hc->slots;
3584 features->pcm_banks = 2;
3585 }
3586 break;
3587 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3588 slot_tx = cq->p1 & 0xff;
3589 bank_tx = cq->p1 >> 8;
3590 slot_rx = cq->p2 & 0xff;
3591 bank_rx = cq->p2 >> 8;
3592 if (debug & DEBUG_HFCMULTI_MSG)
3593 printk(KERN_DEBUG
3594 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3595 "slot %d bank %d (RX)\n",
3596 __func__, slot_tx, bank_tx,
3597 slot_rx, bank_rx);
3598 if (slot_tx < hc->slots && bank_tx <= 2 &&
3599 slot_rx < hc->slots && bank_rx <= 2)
3600 hfcmulti_pcm(hc, bch->slot,
3601 slot_tx, bank_tx, slot_rx, bank_rx);
3602 else {
3603 printk(KERN_WARNING
3604 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3605 "slot %d bank %d (RX) out of range\n",
3606 __func__, slot_tx, bank_tx,
3607 slot_rx, bank_rx);
3608 ret = -EINVAL;
3609 }
3610 break;
3611 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3612 if (debug & DEBUG_HFCMULTI_MSG)
3613 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3614 __func__);
3615 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3616 break;
3617 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3618 num = cq->p1 & 0xff;
3619 if (debug & DEBUG_HFCMULTI_MSG)
3620 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3621 __func__, num);
3622 if (num <= 7)
3623 hfcmulti_conf(hc, bch->slot, num);
3624 else {
3625 printk(KERN_WARNING
3626 "%s: HW_CONF_JOIN conf %d out of range\n",
3627 __func__, num);
3628 ret = -EINVAL;
3629 }
3630 break;
3631 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3632 if (debug & DEBUG_HFCMULTI_MSG)
3633 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3634 hfcmulti_conf(hc, bch->slot, -1);
3635 break;
3636 case MISDN_CTRL_HFC_ECHOCAN_ON:
3637 if (debug & DEBUG_HFCMULTI_MSG)
3638 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3639 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3640 vpm_echocan_on(hc, bch->slot, cq->p1);
3641 else
3642 ret = -EINVAL;
3643 break;
3644
3645 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3646 if (debug & DEBUG_HFCMULTI_MSG)
3647 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3648 __func__);
3649 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3650 vpm_echocan_off(hc, bch->slot);
3651 else
3652 ret = -EINVAL;
3653 break;
3654 default:
3655 printk(KERN_WARNING "%s: unknown Op %x\n",
3656 __func__, cq->op);
3657 ret = -EINVAL;
3658 break;
3659 }
3660 return ret;
3661 }
3662
3663 static int
3664 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3665 {
3666 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3667 struct hfc_multi *hc = bch->hw;
3668 int err = -EINVAL;
3669 u_long flags;
3670
3671 if (bch->debug & DEBUG_HW)
3672 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3673 __func__, cmd, arg);
3674 switch (cmd) {
3675 case CLOSE_CHANNEL:
3676 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3677 if (test_bit(FLG_ACTIVE, &bch->Flags))
3678 deactivate_bchannel(bch); /* locked there */
3679 ch->protocol = ISDN_P_NONE;
3680 ch->peer = NULL;
3681 module_put(THIS_MODULE);
3682 err = 0;
3683 break;
3684 case CONTROL_CHANNEL:
3685 spin_lock_irqsave(&hc->lock, flags);
3686 err = channel_bctrl(bch, arg);
3687 spin_unlock_irqrestore(&hc->lock, flags);
3688 break;
3689 default:
3690 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3691 __func__, cmd);
3692 }
3693 return err;
3694 }
3695
3696 /*
3697 * handle D-channel events
3698 *
3699 * handle state change event
3700 */
3701 static void
3702 ph_state_change(struct dchannel *dch)
3703 {
3704 struct hfc_multi *hc;
3705 int ch, i;
3706
3707 if (!dch) {
3708 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3709 return;
3710 }
3711 hc = dch->hw;
3712 ch = dch->slot;
3713
3714 if (hc->ctype == HFC_TYPE_E1) {
3715 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3716 if (debug & DEBUG_HFCMULTI_STATE)
3717 printk(KERN_DEBUG
3718 "%s: E1 TE (id=%d) newstate %x\n",
3719 __func__, hc->id, dch->state);
3720 } else {
3721 if (debug & DEBUG_HFCMULTI_STATE)
3722 printk(KERN_DEBUG
3723 "%s: E1 NT (id=%d) newstate %x\n",
3724 __func__, hc->id, dch->state);
3725 }
3726 switch (dch->state) {
3727 case (1):
3728 if (hc->e1_state != 1) {
3729 for (i = 1; i <= 31; i++) {
3730 /* reset fifos on e1 activation */
3731 HFC_outb_nodebug(hc, R_FIFO,
3732 (i << 1) | 1);
3733 HFC_wait_nodebug(hc);
3734 HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3735 V_RES_F);
3736 HFC_wait_nodebug(hc);
3737 }
3738 }
3739 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3740 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3741 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3742 break;
3743
3744 default:
3745 if (hc->e1_state != 1)
3746 return;
3747 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3748 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3749 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3750 }
3751 hc->e1_state = dch->state;
3752 } else {
3753 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3754 if (debug & DEBUG_HFCMULTI_STATE)
3755 printk(KERN_DEBUG
3756 "%s: S/T TE newstate %x\n",
3757 __func__, dch->state);
3758 switch (dch->state) {
3759 case (0):
3760 l1_event(dch->l1, HW_RESET_IND);
3761 break;
3762 case (3):
3763 l1_event(dch->l1, HW_DEACT_IND);
3764 break;
3765 case (5):
3766 case (8):
3767 l1_event(dch->l1, ANYSIGNAL);
3768 break;
3769 case (6):
3770 l1_event(dch->l1, INFO2);
3771 break;
3772 case (7):
3773 l1_event(dch->l1, INFO4_P8);
3774 break;
3775 }
3776 } else {
3777 if (debug & DEBUG_HFCMULTI_STATE)
3778 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3779 __func__, dch->state);
3780 switch (dch->state) {
3781 case (2):
3782 if (hc->chan[ch].nt_timer == 0) {
3783 hc->chan[ch].nt_timer = -1;
3784 HFC_outb(hc, R_ST_SEL,
3785 hc->chan[ch].port);
3786 /* undocumented: delay after R_ST_SEL */
3787 udelay(1);
3788 HFC_outb(hc, A_ST_WR_STATE, 4 |
3789 V_ST_LD_STA); /* G4 */
3790 udelay(6); /* wait at least 5,21us */
3791 HFC_outb(hc, A_ST_WR_STATE, 4);
3792 dch->state = 4;
3793 } else {
3794 /* one extra count for the next event */
3795 hc->chan[ch].nt_timer =
3796 nt_t1_count[poll_timer] + 1;
3797 HFC_outb(hc, R_ST_SEL,
3798 hc->chan[ch].port);
3799 /* undocumented: delay after R_ST_SEL */
3800 udelay(1);
3801 /* allow G2 -> G3 transition */
3802 HFC_outb(hc, A_ST_WR_STATE, 2 |
3803 V_SET_G2_G3);
3804 }
3805 break;
3806 case (1):
3807 hc->chan[ch].nt_timer = -1;
3808 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3809 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3810 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3811 break;
3812 case (4):
3813 hc->chan[ch].nt_timer = -1;
3814 break;
3815 case (3):
3816 hc->chan[ch].nt_timer = -1;
3817 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3818 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3819 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3820 break;
3821 }
3822 }
3823 }
3824 }
3825
3826 /*
3827 * called for card mode init message
3828 */
3829
3830 static void
3831 hfcmulti_initmode(struct dchannel *dch)
3832 {
3833 struct hfc_multi *hc = dch->hw;
3834 u_char a_st_wr_state, r_e1_wr_sta;
3835 int i, pt;
3836
3837 if (debug & DEBUG_HFCMULTI_INIT)
3838 printk(KERN_DEBUG "%s: entered\n", __func__);
3839
3840 if (hc->ctype == HFC_TYPE_E1) {
3841 hc->chan[hc->dslot].slot_tx = -1;
3842 hc->chan[hc->dslot].slot_rx = -1;
3843 hc->chan[hc->dslot].conf = -1;
3844 if (hc->dslot) {
3845 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3846 -1, 0, -1, 0);
3847 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3848 dch->timer.data = (long) dch;
3849 init_timer(&dch->timer);
3850 }
3851 for (i = 1; i <= 31; i++) {
3852 if (i == hc->dslot)
3853 continue;
3854 hc->chan[i].slot_tx = -1;
3855 hc->chan[i].slot_rx = -1;
3856 hc->chan[i].conf = -1;
3857 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3858 }
3859 /* E1 */
3860 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3861 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3862 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3863 }
3864 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3865 HFC_outb(hc, R_RX0, 0);
3866 hc->hw.r_tx0 = 0 | V_OUT_EN;
3867 } else {
3868 HFC_outb(hc, R_RX0, 1);
3869 hc->hw.r_tx0 = 1 | V_OUT_EN;
3870 }
3871 hc->hw.r_tx1 = V_ATX | V_NTRI;
3872 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3873 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3874 HFC_outb(hc, R_TX_FR0, 0x00);
3875 HFC_outb(hc, R_TX_FR1, 0xf8);
3876
3877 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3878 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3879
3880 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3881
3882 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3883 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3884
3885 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3886 if (debug & DEBUG_HFCMULTI_INIT)
3887 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3888 __func__);
3889 r_e1_wr_sta = 0; /* G0 */
3890 hc->e1_getclock = 0;
3891 } else {
3892 if (debug & DEBUG_HFCMULTI_INIT)
3893 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3894 __func__);
3895 r_e1_wr_sta = 0; /* F0 */
3896 hc->e1_getclock = 1;
3897 }
3898 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3899 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3900 else
3901 HFC_outb(hc, R_SYNC_OUT, 0);
3902 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3903 hc->e1_getclock = 1;
3904 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3905 hc->e1_getclock = 0;
3906 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3907 /* SLAVE (clock master) */
3908 if (debug & DEBUG_HFCMULTI_INIT)
3909 printk(KERN_DEBUG
3910 "%s: E1 port is clock master "
3911 "(clock from PCM)\n", __func__);
3912 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3913 } else {
3914 if (hc->e1_getclock) {
3915 /* MASTER (clock slave) */
3916 if (debug & DEBUG_HFCMULTI_INIT)
3917 printk(KERN_DEBUG
3918 "%s: E1 port is clock slave "
3919 "(clock to PCM)\n", __func__);
3920 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3921 } else {
3922 /* MASTER (clock master) */
3923 if (debug & DEBUG_HFCMULTI_INIT)
3924 printk(KERN_DEBUG "%s: E1 port is "
3925 "clock master "
3926 "(clock from QUARTZ)\n",
3927 __func__);
3928 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3929 V_PCM_SYNC | V_JATT_OFF);
3930 HFC_outb(hc, R_SYNC_OUT, 0);
3931 }
3932 }
3933 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3934 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3935 HFC_outb(hc, R_PWM0, 0x50);
3936 HFC_outb(hc, R_PWM1, 0xff);
3937 /* state machine setup */
3938 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3939 udelay(6); /* wait at least 5,21us */
3940 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3941 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3942 hc->syncronized = 0;
3943 plxsd_checksync(hc, 0);
3944 }
3945 } else {
3946 i = dch->slot;
3947 hc->chan[i].slot_tx = -1;
3948 hc->chan[i].slot_rx = -1;
3949 hc->chan[i].conf = -1;
3950 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3951 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3952 dch->timer.data = (long) dch;
3953 init_timer(&dch->timer);
3954 hc->chan[i - 2].slot_tx = -1;
3955 hc->chan[i - 2].slot_rx = -1;
3956 hc->chan[i - 2].conf = -1;
3957 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3958 hc->chan[i - 1].slot_tx = -1;
3959 hc->chan[i - 1].slot_rx = -1;
3960 hc->chan[i - 1].conf = -1;
3961 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3962 /* ST */
3963 pt = hc->chan[i].port;
3964 /* select interface */
3965 HFC_outb(hc, R_ST_SEL, pt);
3966 /* undocumented: delay after R_ST_SEL */
3967 udelay(1);
3968 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3969 if (debug & DEBUG_HFCMULTI_INIT)
3970 printk(KERN_DEBUG
3971 "%s: ST port %d is NT-mode\n",
3972 __func__, pt);
3973 /* clock delay */
3974 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3975 a_st_wr_state = 1; /* G1 */
3976 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3977 } else {
3978 if (debug & DEBUG_HFCMULTI_INIT)
3979 printk(KERN_DEBUG
3980 "%s: ST port %d is TE-mode\n",
3981 __func__, pt);
3982 /* clock delay */
3983 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3984 a_st_wr_state = 2; /* F2 */
3985 hc->hw.a_st_ctrl0[pt] = 0;
3986 }
3987 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3988 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3989 if (hc->ctype == HFC_TYPE_XHFC) {
3990 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
3991 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
3992 0x7c << 1 /* V_ST_PULSE */);
3993 }
3994 /* line setup */
3995 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
3996 /* disable E-channel */
3997 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3998 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3999 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4000 else
4001 HFC_outb(hc, A_ST_CTRL1, 0);
4002 /* enable B-channel receive */
4003 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
4004 /* state machine setup */
4005 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4006 udelay(6); /* wait at least 5,21us */
4007 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4008 hc->hw.r_sci_msk |= 1 << pt;
4009 /* state machine interrupts */
4010 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4011 /* unset sync on port */
4012 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4013 hc->syncronized &=
4014 ~(1 << hc->chan[dch->slot].port);
4015 plxsd_checksync(hc, 0);
4016 }
4017 }
4018 if (debug & DEBUG_HFCMULTI_INIT)
4019 printk("%s: done\n", __func__);
4020 }
4021
4022
4023 static int
4024 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4025 struct channel_req *rq)
4026 {
4027 int err = 0;
4028 u_long flags;
4029
4030 if (debug & DEBUG_HW_OPEN)
4031 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4032 dch->dev.id, __builtin_return_address(0));
4033 if (rq->protocol == ISDN_P_NONE)
4034 return -EINVAL;
4035 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4036 (dch->dev.D.protocol != rq->protocol)) {
4037 if (debug & DEBUG_HFCMULTI_MODE)
4038 printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4039 __func__, dch->dev.D.protocol, rq->protocol);
4040 }
4041 if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4042 (rq->protocol != ISDN_P_TE_S0))
4043 l1_event(dch->l1, CLOSE_CHANNEL);
4044 if (dch->dev.D.protocol != rq->protocol) {
4045 if (rq->protocol == ISDN_P_TE_S0) {
4046 err = create_l1(dch, hfcm_l1callback);
4047 if (err)
4048 return err;
4049 }
4050 dch->dev.D.protocol = rq->protocol;
4051 spin_lock_irqsave(&hc->lock, flags);
4052 hfcmulti_initmode(dch);
4053 spin_unlock_irqrestore(&hc->lock, flags);
4054 }
4055
4056 if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
4057 ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
4058 ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
4059 ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
4060 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4061 0, NULL, GFP_KERNEL);
4062 }
4063 rq->ch = &dch->dev.D;
4064 if (!try_module_get(THIS_MODULE))
4065 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4066 return 0;
4067 }
4068
4069 static int
4070 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4071 struct channel_req *rq)
4072 {
4073 struct bchannel *bch;
4074 int ch;
4075
4076 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4077 return -EINVAL;
4078 if (rq->protocol == ISDN_P_NONE)
4079 return -EINVAL;
4080 if (hc->ctype == HFC_TYPE_E1)
4081 ch = rq->adr.channel;
4082 else
4083 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4084 bch = hc->chan[ch].bch;
4085 if (!bch) {
4086 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4087 __func__, ch);
4088 return -EINVAL;
4089 }
4090 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4091 return -EBUSY; /* b-channel can be only open once */
4092 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
4093 bch->ch.protocol = rq->protocol;
4094 hc->chan[ch].rx_off = 0;
4095 rq->ch = &bch->ch;
4096 if (!try_module_get(THIS_MODULE))
4097 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4098 return 0;
4099 }
4100
4101 /*
4102 * device control function
4103 */
4104 static int
4105 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4106 {
4107 struct hfc_multi *hc = dch->hw;
4108 int ret = 0;
4109 int wd_mode, wd_cnt;
4110
4111 switch (cq->op) {
4112 case MISDN_CTRL_GETOP:
4113 cq->op = MISDN_CTRL_HFC_OP;
4114 break;
4115 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4116 wd_cnt = cq->p1 & 0xf;
4117 wd_mode = !!(cq->p1 >> 4);
4118 if (debug & DEBUG_HFCMULTI_MSG)
4119 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4120 ", counter 0x%x\n", __func__,
4121 wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4122 /* set the watchdog timer */
4123 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4124 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4125 if (hc->ctype == HFC_TYPE_XHFC)
4126 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4127 /* init the watchdog register and reset the counter */
4128 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4129 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4130 /* enable the watchdog output for Speech-Design */
4131 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4132 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
4133 HFC_outb(hc, R_GPIO_OUT1, 0);
4134 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4135 }
4136 break;
4137 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4138 if (debug & DEBUG_HFCMULTI_MSG)
4139 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4140 __func__);
4141 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4142 break;
4143 default:
4144 printk(KERN_WARNING "%s: unknown Op %x\n",
4145 __func__, cq->op);
4146 ret = -EINVAL;
4147 break;
4148 }
4149 return ret;
4150 }
4151
4152 static int
4153 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4154 {
4155 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4156 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4157 struct hfc_multi *hc = dch->hw;
4158 struct channel_req *rq;
4159 int err = 0;
4160 u_long flags;
4161
4162 if (dch->debug & DEBUG_HW)
4163 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4164 __func__, cmd, arg);
4165 switch (cmd) {
4166 case OPEN_CHANNEL:
4167 rq = arg;
4168 switch (rq->protocol) {
4169 case ISDN_P_TE_S0:
4170 case ISDN_P_NT_S0:
4171 if (hc->ctype == HFC_TYPE_E1) {
4172 err = -EINVAL;
4173 break;
4174 }
4175 err = open_dchannel(hc, dch, rq); /* locked there */
4176 break;
4177 case ISDN_P_TE_E1:
4178 case ISDN_P_NT_E1:
4179 if (hc->ctype != HFC_TYPE_E1) {
4180 err = -EINVAL;
4181 break;
4182 }
4183 err = open_dchannel(hc, dch, rq); /* locked there */
4184 break;
4185 default:
4186 spin_lock_irqsave(&hc->lock, flags);
4187 err = open_bchannel(hc, dch, rq);
4188 spin_unlock_irqrestore(&hc->lock, flags);
4189 }
4190 break;
4191 case CLOSE_CHANNEL:
4192 if (debug & DEBUG_HW_OPEN)
4193 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4194 __func__, dch->dev.id,
4195 __builtin_return_address(0));
4196 module_put(THIS_MODULE);
4197 break;
4198 case CONTROL_CHANNEL:
4199 spin_lock_irqsave(&hc->lock, flags);
4200 err = channel_dctrl(dch, arg);
4201 spin_unlock_irqrestore(&hc->lock, flags);
4202 break;
4203 default:
4204 if (dch->debug & DEBUG_HW)
4205 printk(KERN_DEBUG "%s: unknown command %x\n",
4206 __func__, cmd);
4207 err = -EINVAL;
4208 }
4209 return err;
4210 }
4211
4212 static int
4213 clockctl(void *priv, int enable)
4214 {
4215 struct hfc_multi *hc = priv;
4216
4217 hc->iclock_on = enable;
4218 return 0;
4219 }
4220
4221 /*
4222 * initialize the card
4223 */
4224
4225 /*
4226 * start timer irq, wait some time and check if we have interrupts.
4227 * if not, reset chip and try again.
4228 */
4229 static int
4230 init_card(struct hfc_multi *hc)
4231 {
4232 int err = -EIO;
4233 u_long flags;
4234 void __iomem *plx_acc;
4235 u_long plx_flags;
4236
4237 if (debug & DEBUG_HFCMULTI_INIT)
4238 printk(KERN_DEBUG "%s: entered\n", __func__);
4239
4240 spin_lock_irqsave(&hc->lock, flags);
4241 /* set interrupts but leave global interrupt disabled */
4242 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4243 disable_hwirq(hc);
4244 spin_unlock_irqrestore(&hc->lock, flags);
4245
4246 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4247 "HFC-multi", hc)) {
4248 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4249 hc->irq);
4250 hc->irq = 0;
4251 return -EIO;
4252 }
4253
4254 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4255 spin_lock_irqsave(&plx_lock, plx_flags);
4256 plx_acc = hc->plx_membase + PLX_INTCSR;
4257 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4258 plx_acc); /* enable PCI & LINT1 irq */
4259 spin_unlock_irqrestore(&plx_lock, plx_flags);
4260 }
4261
4262 if (debug & DEBUG_HFCMULTI_INIT)
4263 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4264 __func__, hc->irq, hc->irqcnt);
4265 err = init_chip(hc);
4266 if (err)
4267 goto error;
4268 /*
4269 * Finally enable IRQ output
4270 * this is only allowed, if an IRQ routine is allready
4271 * established for this HFC, so don't do that earlier
4272 */
4273 spin_lock_irqsave(&hc->lock, flags);
4274 enable_hwirq(hc);
4275 spin_unlock_irqrestore(&hc->lock, flags);
4276 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4277 set_current_state(TASK_UNINTERRUPTIBLE);
4278 schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4279 /* turn IRQ off until chip is completely initialized */
4280 spin_lock_irqsave(&hc->lock, flags);
4281 disable_hwirq(hc);
4282 spin_unlock_irqrestore(&hc->lock, flags);
4283 if (debug & DEBUG_HFCMULTI_INIT)
4284 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4285 __func__, hc->irq, hc->irqcnt);
4286 if (hc->irqcnt) {
4287 if (debug & DEBUG_HFCMULTI_INIT)
4288 printk(KERN_DEBUG "%s: done\n", __func__);
4289
4290 return 0;
4291 }
4292 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4293 printk(KERN_INFO "ignoring missing interrupts\n");
4294 return 0;
4295 }
4296
4297 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4298 hc->irq);
4299
4300 err = -EIO;
4301
4302 error:
4303 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4304 spin_lock_irqsave(&plx_lock, plx_flags);
4305 plx_acc = hc->plx_membase + PLX_INTCSR;
4306 writew(0x00, plx_acc); /*disable IRQs*/
4307 spin_unlock_irqrestore(&plx_lock, plx_flags);
4308 }
4309
4310 if (debug & DEBUG_HFCMULTI_INIT)
4311 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4312 if (hc->irq) {
4313 free_irq(hc->irq, hc);
4314 hc->irq = 0;
4315 }
4316
4317 if (debug & DEBUG_HFCMULTI_INIT)
4318 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4319 return err;
4320 }
4321
4322 /*
4323 * find pci device and set it up
4324 */
4325
4326 static int
4327 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4328 const struct pci_device_id *ent)
4329 {
4330 struct hm_map *m = (struct hm_map *)ent->driver_data;
4331
4332 printk(KERN_INFO
4333 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4334 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4335
4336 hc->pci_dev = pdev;
4337 if (m->clock2)
4338 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4339
4340 if (ent->device == 0xB410) {
4341 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4342 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4343 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4344 hc->slots = 32;
4345 }
4346
4347 if (hc->pci_dev->irq <= 0) {
4348 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4349 return -EIO;
4350 }
4351 if (pci_enable_device(hc->pci_dev)) {
4352 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4353 return -EIO;
4354 }
4355 hc->leds = m->leds;
4356 hc->ledstate = 0xAFFEAFFE;
4357 hc->opticalsupport = m->opticalsupport;
4358
4359 hc->pci_iobase = 0;
4360 hc->pci_membase = NULL;
4361 hc->plx_membase = NULL;
4362
4363 /* set memory access methods */
4364 if (m->io_mode) /* use mode from card config */
4365 hc->io_mode = m->io_mode;
4366 switch (hc->io_mode) {
4367 case HFC_IO_MODE_PLXSD:
4368 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4369 hc->slots = 128; /* required */
4370 hc->HFC_outb = HFC_outb_pcimem;
4371 hc->HFC_inb = HFC_inb_pcimem;
4372 hc->HFC_inw = HFC_inw_pcimem;
4373 hc->HFC_wait = HFC_wait_pcimem;
4374 hc->read_fifo = read_fifo_pcimem;
4375 hc->write_fifo = write_fifo_pcimem;
4376 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4377 /* MEMBASE 1 is PLX PCI Bridge */
4378
4379 if (!hc->plx_origmembase) {
4380 printk(KERN_WARNING
4381 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4382 pci_disable_device(hc->pci_dev);
4383 return -EIO;
4384 }
4385
4386 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4387 if (!hc->plx_membase) {
4388 printk(KERN_WARNING
4389 "HFC-multi: failed to remap plx address space. "
4390 "(internal error)\n");
4391 pci_disable_device(hc->pci_dev);
4392 return -EIO;
4393 }
4394 printk(KERN_INFO
4395 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4396 (u_long)hc->plx_membase, hc->plx_origmembase);
4397
4398 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4399 /* MEMBASE 1 is PLX PCI Bridge */
4400 if (!hc->pci_origmembase) {
4401 printk(KERN_WARNING
4402 "HFC-multi: No IO-Memory for PCI card found\n");
4403 pci_disable_device(hc->pci_dev);
4404 return -EIO;
4405 }
4406
4407 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4408 if (!hc->pci_membase) {
4409 printk(KERN_WARNING "HFC-multi: failed to remap io "
4410 "address space. (internal error)\n");
4411 pci_disable_device(hc->pci_dev);
4412 return -EIO;
4413 }
4414
4415 printk(KERN_INFO
4416 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4417 "leds-type %d\n",
4418 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4419 hc->pci_dev->irq, HZ, hc->leds);
4420 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4421 break;
4422 case HFC_IO_MODE_PCIMEM:
4423 hc->HFC_outb = HFC_outb_pcimem;
4424 hc->HFC_inb = HFC_inb_pcimem;
4425 hc->HFC_inw = HFC_inw_pcimem;
4426 hc->HFC_wait = HFC_wait_pcimem;
4427 hc->read_fifo = read_fifo_pcimem;
4428 hc->write_fifo = write_fifo_pcimem;
4429 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4430 if (!hc->pci_origmembase) {
4431 printk(KERN_WARNING
4432 "HFC-multi: No IO-Memory for PCI card found\n");
4433 pci_disable_device(hc->pci_dev);
4434 return -EIO;
4435 }
4436
4437 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4438 if (!hc->pci_membase) {
4439 printk(KERN_WARNING
4440 "HFC-multi: failed to remap io address space. "
4441 "(internal error)\n");
4442 pci_disable_device(hc->pci_dev);
4443 return -EIO;
4444 }
4445 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4446 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4447 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4448 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4449 break;
4450 case HFC_IO_MODE_REGIO:
4451 hc->HFC_outb = HFC_outb_regio;
4452 hc->HFC_inb = HFC_inb_regio;
4453 hc->HFC_inw = HFC_inw_regio;
4454 hc->HFC_wait = HFC_wait_regio;
4455 hc->read_fifo = read_fifo_regio;
4456 hc->write_fifo = write_fifo_regio;
4457 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4458 if (!hc->pci_iobase) {
4459 printk(KERN_WARNING
4460 "HFC-multi: No IO for PCI card found\n");
4461 pci_disable_device(hc->pci_dev);
4462 return -EIO;
4463 }
4464
4465 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4466 printk(KERN_WARNING "HFC-multi: failed to request "
4467 "address space at 0x%08lx (internal error)\n",
4468 hc->pci_iobase);
4469 pci_disable_device(hc->pci_dev);
4470 return -EIO;
4471 }
4472
4473 printk(KERN_INFO
4474 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4475 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4476 hc->pci_dev->irq, HZ, hc->leds);
4477 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4478 break;
4479 default:
4480 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4481 pci_disable_device(hc->pci_dev);
4482 return -EIO;
4483 }
4484
4485 pci_set_drvdata(hc->pci_dev, hc);
4486
4487 /* At this point the needed PCI config is done */
4488 /* fifos are still not enabled */
4489 return 0;
4490 }
4491
4492
4493 /*
4494 * remove port
4495 */
4496
4497 static void
4498 release_port(struct hfc_multi *hc, struct dchannel *dch)
4499 {
4500 int pt, ci, i = 0;
4501 u_long flags;
4502 struct bchannel *pb;
4503
4504 ci = dch->slot;
4505 pt = hc->chan[ci].port;
4506
4507 if (debug & DEBUG_HFCMULTI_INIT)
4508 printk(KERN_DEBUG "%s: entered for port %d\n",
4509 __func__, pt + 1);
4510
4511 if (pt >= hc->ports) {
4512 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4513 __func__, pt + 1);
4514 return;
4515 }
4516
4517 if (debug & DEBUG_HFCMULTI_INIT)
4518 printk(KERN_DEBUG "%s: releasing port=%d\n",
4519 __func__, pt + 1);
4520
4521 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4522 l1_event(dch->l1, CLOSE_CHANNEL);
4523
4524 hc->chan[ci].dch = NULL;
4525
4526 if (hc->created[pt]) {
4527 hc->created[pt] = 0;
4528 mISDN_unregister_device(&dch->dev);
4529 }
4530
4531 spin_lock_irqsave(&hc->lock, flags);
4532
4533 if (dch->timer.function) {
4534 del_timer(&dch->timer);
4535 dch->timer.function = NULL;
4536 }
4537
4538 if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4539 /* remove sync */
4540 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4541 hc->syncronized = 0;
4542 plxsd_checksync(hc, 1);
4543 }
4544 /* free channels */
4545 for (i = 0; i <= 31; i++) {
4546 if (hc->chan[i].bch) {
4547 if (debug & DEBUG_HFCMULTI_INIT)
4548 printk(KERN_DEBUG
4549 "%s: free port %d channel %d\n",
4550 __func__, hc->chan[i].port+1, i);
4551 pb = hc->chan[i].bch;
4552 hc->chan[i].bch = NULL;
4553 spin_unlock_irqrestore(&hc->lock, flags);
4554 mISDN_freebchannel(pb);
4555 kfree(pb);
4556 kfree(hc->chan[i].coeff);
4557 spin_lock_irqsave(&hc->lock, flags);
4558 }
4559 }
4560 } else {
4561 /* remove sync */
4562 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4563 hc->syncronized &=
4564 ~(1 << hc->chan[ci].port);
4565 plxsd_checksync(hc, 1);
4566 }
4567 /* free channels */
4568 if (hc->chan[ci - 2].bch) {
4569 if (debug & DEBUG_HFCMULTI_INIT)
4570 printk(KERN_DEBUG
4571 "%s: free port %d channel %d\n",
4572 __func__, hc->chan[ci - 2].port+1,
4573 ci - 2);
4574 pb = hc->chan[ci - 2].bch;
4575 hc->chan[ci - 2].bch = NULL;
4576 spin_unlock_irqrestore(&hc->lock, flags);
4577 mISDN_freebchannel(pb);
4578 kfree(pb);
4579 kfree(hc->chan[ci - 2].coeff);
4580 spin_lock_irqsave(&hc->lock, flags);
4581 }
4582 if (hc->chan[ci - 1].bch) {
4583 if (debug & DEBUG_HFCMULTI_INIT)
4584 printk(KERN_DEBUG
4585 "%s: free port %d channel %d\n",
4586 __func__, hc->chan[ci - 1].port+1,
4587 ci - 1);
4588 pb = hc->chan[ci - 1].bch;
4589 hc->chan[ci - 1].bch = NULL;
4590 spin_unlock_irqrestore(&hc->lock, flags);
4591 mISDN_freebchannel(pb);
4592 kfree(pb);
4593 kfree(hc->chan[ci - 1].coeff);
4594 spin_lock_irqsave(&hc->lock, flags);
4595 }
4596 }
4597
4598 spin_unlock_irqrestore(&hc->lock, flags);
4599
4600 if (debug & DEBUG_HFCMULTI_INIT)
4601 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4602 mISDN_freedchannel(dch);
4603 kfree(dch);
4604
4605 if (debug & DEBUG_HFCMULTI_INIT)
4606 printk(KERN_DEBUG "%s: done!\n", __func__);
4607 }
4608
4609 static void
4610 release_card(struct hfc_multi *hc)
4611 {
4612 u_long flags;
4613 int ch;
4614
4615 if (debug & DEBUG_HFCMULTI_INIT)
4616 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4617 __func__, hc->id);
4618
4619 /* unregister clock source */
4620 if (hc->iclock)
4621 mISDN_unregister_clock(hc->iclock);
4622
4623 /* disable irq */
4624 spin_lock_irqsave(&hc->lock, flags);
4625 disable_hwirq(hc);
4626 spin_unlock_irqrestore(&hc->lock, flags);
4627 udelay(1000);
4628
4629 /* dimm leds */
4630 if (hc->leds)
4631 hfcmulti_leds(hc);
4632
4633 /* disable D-channels & B-channels */
4634 if (debug & DEBUG_HFCMULTI_INIT)
4635 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4636 __func__);
4637 for (ch = 0; ch <= 31; ch++) {
4638 if (hc->chan[ch].dch)
4639 release_port(hc, hc->chan[ch].dch);
4640 }
4641
4642 /* release hardware & irq */
4643 if (hc->irq) {
4644 if (debug & DEBUG_HFCMULTI_INIT)
4645 printk(KERN_DEBUG "%s: free irq %d\n",
4646 __func__, hc->irq);
4647 free_irq(hc->irq, hc);
4648 hc->irq = 0;
4649
4650 }
4651 release_io_hfcmulti(hc);
4652
4653 if (debug & DEBUG_HFCMULTI_INIT)
4654 printk(KERN_DEBUG "%s: remove instance from list\n",
4655 __func__);
4656 list_del(&hc->list);
4657
4658 if (debug & DEBUG_HFCMULTI_INIT)
4659 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4660 if (hc == syncmaster)
4661 syncmaster = NULL;
4662 kfree(hc);
4663 if (debug & DEBUG_HFCMULTI_INIT)
4664 printk(KERN_DEBUG "%s: card successfully removed\n",
4665 __func__);
4666 }
4667
4668 static int
4669 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4670 {
4671 struct dchannel *dch;
4672 struct bchannel *bch;
4673 int ch, ret = 0;
4674 char name[MISDN_MAX_IDLEN];
4675
4676 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4677 if (!dch)
4678 return -ENOMEM;
4679 dch->debug = debug;
4680 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4681 dch->hw = hc;
4682 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4683 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4684 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4685 dch->dev.D.send = handle_dmsg;
4686 dch->dev.D.ctrl = hfcm_dctrl;
4687 dch->dev.nrbchan = (hc->dslot) ? 30 : 31;
4688 dch->slot = hc->dslot;
4689 hc->chan[hc->dslot].dch = dch;
4690 hc->chan[hc->dslot].port = 0;
4691 hc->chan[hc->dslot].nt_timer = -1;
4692 for (ch = 1; ch <= 31; ch++) {
4693 if (ch == hc->dslot) /* skip dchannel */
4694 continue;
4695 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4696 if (!bch) {
4697 printk(KERN_ERR "%s: no memory for bchannel\n",
4698 __func__);
4699 ret = -ENOMEM;
4700 goto free_chan;
4701 }
4702 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4703 if (!hc->chan[ch].coeff) {
4704 printk(KERN_ERR "%s: no memory for coeffs\n",
4705 __func__);
4706 ret = -ENOMEM;
4707 kfree(bch);
4708 goto free_chan;
4709 }
4710 bch->nr = ch;
4711 bch->slot = ch;
4712 bch->debug = debug;
4713 mISDN_initbchannel(bch, MAX_DATA_MEM);
4714 bch->hw = hc;
4715 bch->ch.send = handle_bmsg;
4716 bch->ch.ctrl = hfcm_bctrl;
4717 bch->ch.nr = ch;
4718 list_add(&bch->ch.list, &dch->dev.bchannels);
4719 hc->chan[ch].bch = bch;
4720 hc->chan[ch].port = 0;
4721 set_channelmap(bch->nr, dch->dev.channelmap);
4722 }
4723 /* set optical line type */
4724 if (port[Port_cnt] & 0x001) {
4725 if (!m->opticalsupport) {
4726 printk(KERN_INFO
4727 "This board has no optical "
4728 "support\n");
4729 } else {
4730 if (debug & DEBUG_HFCMULTI_INIT)
4731 printk(KERN_DEBUG
4732 "%s: PORT set optical "
4733 "interfacs: card(%d) "
4734 "port(%d)\n",
4735 __func__,
4736 HFC_cnt + 1, 1);
4737 test_and_set_bit(HFC_CFG_OPTICAL,
4738 &hc->chan[hc->dslot].cfg);
4739 }
4740 }
4741 /* set LOS report */
4742 if (port[Port_cnt] & 0x004) {
4743 if (debug & DEBUG_HFCMULTI_INIT)
4744 printk(KERN_DEBUG "%s: PORT set "
4745 "LOS report: card(%d) port(%d)\n",
4746 __func__, HFC_cnt + 1, 1);
4747 test_and_set_bit(HFC_CFG_REPORT_LOS,
4748 &hc->chan[hc->dslot].cfg);
4749 }
4750 /* set AIS report */
4751 if (port[Port_cnt] & 0x008) {
4752 if (debug & DEBUG_HFCMULTI_INIT)
4753 printk(KERN_DEBUG "%s: PORT set "
4754 "AIS report: card(%d) port(%d)\n",
4755 __func__, HFC_cnt + 1, 1);
4756 test_and_set_bit(HFC_CFG_REPORT_AIS,
4757 &hc->chan[hc->dslot].cfg);
4758 }
4759 /* set SLIP report */
4760 if (port[Port_cnt] & 0x010) {
4761 if (debug & DEBUG_HFCMULTI_INIT)
4762 printk(KERN_DEBUG
4763 "%s: PORT set SLIP report: "
4764 "card(%d) port(%d)\n",
4765 __func__, HFC_cnt + 1, 1);
4766 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4767 &hc->chan[hc->dslot].cfg);
4768 }
4769 /* set RDI report */
4770 if (port[Port_cnt] & 0x020) {
4771 if (debug & DEBUG_HFCMULTI_INIT)
4772 printk(KERN_DEBUG
4773 "%s: PORT set RDI report: "
4774 "card(%d) port(%d)\n",
4775 __func__, HFC_cnt + 1, 1);
4776 test_and_set_bit(HFC_CFG_REPORT_RDI,
4777 &hc->chan[hc->dslot].cfg);
4778 }
4779 /* set CRC-4 Mode */
4780 if (!(port[Port_cnt] & 0x100)) {
4781 if (debug & DEBUG_HFCMULTI_INIT)
4782 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4783 " card(%d) port(%d)\n",
4784 __func__, HFC_cnt + 1, 1);
4785 test_and_set_bit(HFC_CFG_CRC4,
4786 &hc->chan[hc->dslot].cfg);
4787 } else {
4788 if (debug & DEBUG_HFCMULTI_INIT)
4789 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4790 " report: card(%d) port(%d)\n",
4791 __func__, HFC_cnt + 1, 1);
4792 }
4793 /* set forced clock */
4794 if (port[Port_cnt] & 0x0200) {
4795 if (debug & DEBUG_HFCMULTI_INIT)
4796 printk(KERN_DEBUG "%s: PORT force getting clock from "
4797 "E1: card(%d) port(%d)\n",
4798 __func__, HFC_cnt + 1, 1);
4799 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4800 } else
4801 if (port[Port_cnt] & 0x0400) {
4802 if (debug & DEBUG_HFCMULTI_INIT)
4803 printk(KERN_DEBUG "%s: PORT force putting clock to "
4804 "E1: card(%d) port(%d)\n",
4805 __func__, HFC_cnt + 1, 1);
4806 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4807 }
4808 /* set JATT PLL */
4809 if (port[Port_cnt] & 0x0800) {
4810 if (debug & DEBUG_HFCMULTI_INIT)
4811 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4812 "E1: card(%d) port(%d)\n",
4813 __func__, HFC_cnt + 1, 1);
4814 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4815 }
4816 /* set elastic jitter buffer */
4817 if (port[Port_cnt] & 0x3000) {
4818 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4819 if (debug & DEBUG_HFCMULTI_INIT)
4820 printk(KERN_DEBUG
4821 "%s: PORT set elastic "
4822 "buffer to %d: card(%d) port(%d)\n",
4823 __func__, hc->chan[hc->dslot].jitter,
4824 HFC_cnt + 1, 1);
4825 } else
4826 hc->chan[hc->dslot].jitter = 2; /* default */
4827 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4828 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4829 if (ret)
4830 goto free_chan;
4831 hc->created[0] = 1;
4832 return ret;
4833 free_chan:
4834 release_port(hc, dch);
4835 return ret;
4836 }
4837
4838 static int
4839 init_multi_port(struct hfc_multi *hc, int pt)
4840 {
4841 struct dchannel *dch;
4842 struct bchannel *bch;
4843 int ch, i, ret = 0;
4844 char name[MISDN_MAX_IDLEN];
4845
4846 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4847 if (!dch)
4848 return -ENOMEM;
4849 dch->debug = debug;
4850 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4851 dch->hw = hc;
4852 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4853 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4854 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4855 dch->dev.D.send = handle_dmsg;
4856 dch->dev.D.ctrl = hfcm_dctrl;
4857 dch->dev.nrbchan = 2;
4858 i = pt << 2;
4859 dch->slot = i + 2;
4860 hc->chan[i + 2].dch = dch;
4861 hc->chan[i + 2].port = pt;
4862 hc->chan[i + 2].nt_timer = -1;
4863 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4864 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4865 if (!bch) {
4866 printk(KERN_ERR "%s: no memory for bchannel\n",
4867 __func__);
4868 ret = -ENOMEM;
4869 goto free_chan;
4870 }
4871 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4872 if (!hc->chan[i + ch].coeff) {
4873 printk(KERN_ERR "%s: no memory for coeffs\n",
4874 __func__);
4875 ret = -ENOMEM;
4876 kfree(bch);
4877 goto free_chan;
4878 }
4879 bch->nr = ch + 1;
4880 bch->slot = i + ch;
4881 bch->debug = debug;
4882 mISDN_initbchannel(bch, MAX_DATA_MEM);
4883 bch->hw = hc;
4884 bch->ch.send = handle_bmsg;
4885 bch->ch.ctrl = hfcm_bctrl;
4886 bch->ch.nr = ch + 1;
4887 list_add(&bch->ch.list, &dch->dev.bchannels);
4888 hc->chan[i + ch].bch = bch;
4889 hc->chan[i + ch].port = pt;
4890 set_channelmap(bch->nr, dch->dev.channelmap);
4891 }
4892 /* set master clock */
4893 if (port[Port_cnt] & 0x001) {
4894 if (debug & DEBUG_HFCMULTI_INIT)
4895 printk(KERN_DEBUG
4896 "%s: PROTOCOL set master clock: "
4897 "card(%d) port(%d)\n",
4898 __func__, HFC_cnt + 1, pt + 1);
4899 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4900 printk(KERN_ERR "Error: Master clock "
4901 "for port(%d) of card(%d) is only"
4902 " possible with TE-mode\n",
4903 pt + 1, HFC_cnt + 1);
4904 ret = -EINVAL;
4905 goto free_chan;
4906 }
4907 if (hc->masterclk >= 0) {
4908 printk(KERN_ERR "Error: Master clock "
4909 "for port(%d) of card(%d) already "
4910 "defined for port(%d)\n",
4911 pt + 1, HFC_cnt + 1, hc->masterclk+1);
4912 ret = -EINVAL;
4913 goto free_chan;
4914 }
4915 hc->masterclk = pt;
4916 }
4917 /* set transmitter line to non capacitive */
4918 if (port[Port_cnt] & 0x002) {
4919 if (debug & DEBUG_HFCMULTI_INIT)
4920 printk(KERN_DEBUG
4921 "%s: PROTOCOL set non capacitive "
4922 "transmitter: card(%d) port(%d)\n",
4923 __func__, HFC_cnt + 1, pt + 1);
4924 test_and_set_bit(HFC_CFG_NONCAP_TX,
4925 &hc->chan[i + 2].cfg);
4926 }
4927 /* disable E-channel */
4928 if (port[Port_cnt] & 0x004) {
4929 if (debug & DEBUG_HFCMULTI_INIT)
4930 printk(KERN_DEBUG
4931 "%s: PROTOCOL disable E-channel: "
4932 "card(%d) port(%d)\n",
4933 __func__, HFC_cnt + 1, pt + 1);
4934 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4935 &hc->chan[i + 2].cfg);
4936 }
4937 if (hc->ctype == HFC_TYPE_XHFC) {
4938 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4939 HFC_cnt + 1, pt + 1);
4940 ret = mISDN_register_device(&dch->dev, NULL, name);
4941 } else {
4942 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4943 hc->ctype, HFC_cnt + 1, pt + 1);
4944 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4945 }
4946 if (ret)
4947 goto free_chan;
4948 hc->created[pt] = 1;
4949 return ret;
4950 free_chan:
4951 release_port(hc, dch);
4952 return ret;
4953 }
4954
4955 static int
4956 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4957 const struct pci_device_id *ent)
4958 {
4959 int ret_err = 0;
4960 int pt;
4961 struct hfc_multi *hc;
4962 u_long flags;
4963 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4964 int i;
4965
4966 if (HFC_cnt >= MAX_CARDS) {
4967 printk(KERN_ERR "too many cards (max=%d).\n",
4968 MAX_CARDS);
4969 return -EINVAL;
4970 }
4971 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4972 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4973 "type[%d] %d was supplied as module parameter\n",
4974 m->vendor_name, m->card_name, m->type, HFC_cnt,
4975 type[HFC_cnt] & 0xff);
4976 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4977 "first, to see cards and their types.");
4978 return -EINVAL;
4979 }
4980 if (debug & DEBUG_HFCMULTI_INIT)
4981 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4982 __func__, m->vendor_name, m->card_name, m->type,
4983 type[HFC_cnt]);
4984
4985 /* allocate card+fifo structure */
4986 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4987 if (!hc) {
4988 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4989 return -ENOMEM;
4990 }
4991 spin_lock_init(&hc->lock);
4992 hc->mtyp = m;
4993 hc->ctype = m->type;
4994 hc->ports = m->ports;
4995 hc->id = HFC_cnt;
4996 hc->pcm = pcm[HFC_cnt];
4997 hc->io_mode = iomode[HFC_cnt];
4998 if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) {
4999 hc->dslot = 0;
5000 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
5001 "31 B-channels\n");
5002 }
5003 if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32
5004 && hc->ctype == HFC_TYPE_E1) {
5005 hc->dslot = dslot[HFC_cnt];
5006 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
5007 "time slot %d\n", dslot[HFC_cnt]);
5008 } else
5009 hc->dslot = 16;
5010
5011 /* set chip specific features */
5012 hc->masterclk = -1;
5013 if (type[HFC_cnt] & 0x100) {
5014 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5015 hc->silence = 0xff; /* ulaw silence */
5016 } else
5017 hc->silence = 0x2a; /* alaw silence */
5018 if ((poll >> 1) > sizeof(hc->silence_data)) {
5019 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5020 "please fix\n");
5021 return -EINVAL;
5022 }
5023 for (i = 0; i < (poll >> 1); i++)
5024 hc->silence_data[i] = hc->silence;
5025
5026 if (hc->ctype != HFC_TYPE_XHFC) {
5027 if (!(type[HFC_cnt] & 0x200))
5028 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5029 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5030 }
5031
5032 if (type[HFC_cnt] & 0x800)
5033 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5034 if (type[HFC_cnt] & 0x1000) {
5035 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5036 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5037 }
5038 if (type[HFC_cnt] & 0x4000)
5039 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5040 if (type[HFC_cnt] & 0x8000)
5041 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5042 hc->slots = 32;
5043 if (type[HFC_cnt] & 0x10000)
5044 hc->slots = 64;
5045 if (type[HFC_cnt] & 0x20000)
5046 hc->slots = 128;
5047 if (type[HFC_cnt] & 0x80000) {
5048 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5049 hc->wdcount = 0;
5050 hc->wdbyte = V_GPIO_OUT2;
5051 printk(KERN_NOTICE "Watchdog enabled\n");
5052 }
5053
5054 if (pdev && ent)
5055 /* setup pci, hc->slots may change due to PLXSD */
5056 ret_err = setup_pci(hc, pdev, ent);
5057 else
5058 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5059 ret_err = setup_embedded(hc, m);
5060 #else
5061 {
5062 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5063 ret_err = -EIO;
5064 }
5065 #endif
5066 if (ret_err) {
5067 if (hc == syncmaster)
5068 syncmaster = NULL;
5069 kfree(hc);
5070 return ret_err;
5071 }
5072
5073 hc->HFC_outb_nodebug = hc->HFC_outb;
5074 hc->HFC_inb_nodebug = hc->HFC_inb;
5075 hc->HFC_inw_nodebug = hc->HFC_inw;
5076 hc->HFC_wait_nodebug = hc->HFC_wait;
5077 #ifdef HFC_REGISTER_DEBUG
5078 hc->HFC_outb = HFC_outb_debug;
5079 hc->HFC_inb = HFC_inb_debug;
5080 hc->HFC_inw = HFC_inw_debug;
5081 hc->HFC_wait = HFC_wait_debug;
5082 #endif
5083 /* create channels */
5084 for (pt = 0; pt < hc->ports; pt++) {
5085 if (Port_cnt >= MAX_PORTS) {
5086 printk(KERN_ERR "too many ports (max=%d).\n",
5087 MAX_PORTS);
5088 ret_err = -EINVAL;
5089 goto free_card;
5090 }
5091 if (hc->ctype == HFC_TYPE_E1)
5092 ret_err = init_e1_port(hc, m);
5093 else
5094 ret_err = init_multi_port(hc, pt);
5095 if (debug & DEBUG_HFCMULTI_INIT)
5096 printk(KERN_DEBUG
5097 "%s: Registering D-channel, card(%d) port(%d)"
5098 "result %d\n",
5099 __func__, HFC_cnt + 1, pt, ret_err);
5100
5101 if (ret_err) {
5102 while (pt) { /* release already registered ports */
5103 pt--;
5104 release_port(hc, hc->chan[(pt << 2) + 2].dch);
5105 }
5106 goto free_card;
5107 }
5108 Port_cnt++;
5109 }
5110
5111 /* disp switches */
5112 switch (m->dip_type) {
5113 case DIP_4S:
5114 /*
5115 * Get DIP setting for beroNet 1S/2S/4S cards
5116 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5117 * GPI 19/23 (R_GPI_IN2))
5118 */
5119 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5120 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5121 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5122
5123 /* Port mode (TE/NT) jumpers */
5124 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5125
5126 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5127 pmj = ~pmj & 0xf;
5128
5129 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5130 m->vendor_name, m->card_name, dips, pmj);
5131 break;
5132 case DIP_8S:
5133 /*
5134 * Get DIP Setting for beroNet 8S0+ cards
5135 * Enable PCI auxbridge function
5136 */
5137 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5138 /* prepare access to auxport */
5139 outw(0x4000, hc->pci_iobase + 4);
5140 /*
5141 * some dummy reads are required to
5142 * read valid DIP switch data
5143 */
5144 dips = inb(hc->pci_iobase);
5145 dips = inb(hc->pci_iobase);
5146 dips = inb(hc->pci_iobase);
5147 dips = ~inb(hc->pci_iobase) & 0x3F;
5148 outw(0x0, hc->pci_iobase + 4);
5149 /* disable PCI auxbridge function */
5150 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5151 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5152 m->vendor_name, m->card_name, dips);
5153 break;
5154 case DIP_E1:
5155 /*
5156 * get DIP Setting for beroNet E1 cards
5157 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5158 */
5159 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
5160 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5161 m->vendor_name, m->card_name, dips);
5162 break;
5163 }
5164
5165 /* add to list */
5166 spin_lock_irqsave(&HFClock, flags);
5167 list_add_tail(&hc->list, &HFClist);
5168 spin_unlock_irqrestore(&HFClock, flags);
5169
5170 /* use as clock source */
5171 if (clock == HFC_cnt + 1)
5172 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5173
5174 /* initialize hardware */
5175 hc->irq = (m->irq) ? : hc->pci_dev->irq;
5176 ret_err = init_card(hc);
5177 if (ret_err) {
5178 printk(KERN_ERR "init card returns %d\n", ret_err);
5179 release_card(hc);
5180 return ret_err;
5181 }
5182
5183 /* start IRQ and return */
5184 spin_lock_irqsave(&hc->lock, flags);
5185 enable_hwirq(hc);
5186 spin_unlock_irqrestore(&hc->lock, flags);
5187 return 0;
5188
5189 free_card:
5190 release_io_hfcmulti(hc);
5191 if (hc == syncmaster)
5192 syncmaster = NULL;
5193 kfree(hc);
5194 return ret_err;
5195 }
5196
5197 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5198 {
5199 struct hfc_multi *card = pci_get_drvdata(pdev);
5200 u_long flags;
5201
5202 if (debug)
5203 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5204 "device:%x subvendor:%x subdevice:%x\n",
5205 pdev->vendor, pdev->device,
5206 pdev->subsystem_vendor, pdev->subsystem_device);
5207
5208 if (card) {
5209 spin_lock_irqsave(&HFClock, flags);
5210 release_card(card);
5211 spin_unlock_irqrestore(&HFClock, flags);
5212 } else {
5213 if (debug)
5214 printk(KERN_DEBUG "%s: drvdata allready removed\n",
5215 __func__);
5216 }
5217 }
5218
5219 #define VENDOR_CCD "Cologne Chip AG"
5220 #define VENDOR_BN "beroNet GmbH"
5221 #define VENDOR_DIG "Digium Inc."
5222 #define VENDOR_JH "Junghanns.NET GmbH"
5223 #define VENDOR_PRIM "PrimuX"
5224
5225 static const struct hm_map hfcm_map[] = {
5226 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5227 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5228 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5229 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5230 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5231 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5232 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5233 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5234 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5235 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5236 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5237 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5238
5239 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5240 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5241 HFC_IO_MODE_REGIO, 0},
5242 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5243 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5244
5245 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5246 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5247 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5248
5249 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5250 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5251 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5252 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5253
5254 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5255 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5256 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5257
5258 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5259 HFC_IO_MODE_PLXSD, 0},
5260 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5261 HFC_IO_MODE_PLXSD, 0},
5262 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5263 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5264 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5265 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5266 HFC_IO_MODE_EMBSD, XHFC_IRQ},
5267 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5268 };
5269
5270 #undef H
5271 #define H(x) ((unsigned long)&hfcm_map[x])
5272 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5273
5274 /* Cards with HFC-4S Chip */
5275 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5276 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5277 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5278 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5279 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5280 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5281 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5282 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5283 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5284 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5285 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5286 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5287 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5288 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5289 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5290 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5291 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5292 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5293 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5294 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5295 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5296 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5297 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5298 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5299 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5300 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5301 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5302 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5303
5304 /* Cards with HFC-8S Chip */
5305 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5306 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5307 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5308 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5309 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5310 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5311 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5312 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5313 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5314 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5315 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5316 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5317 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5318 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5319 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5320 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5321 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5322 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */
5323
5324
5325 /* Cards with HFC-E1 Chip */
5326 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5327 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5328 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5329 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5330 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5331 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5332 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5333 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5334
5335 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5336 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5337 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5338 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5339 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5340 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5341
5342 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5343 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5344 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5345 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5346
5347 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5348 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5349
5350 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5351 0, 0, 0},
5352 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5353 0, 0, 0},
5354 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5355 0, 0, 0},
5356 {0, }
5357 };
5358 #undef H
5359
5360 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5361
5362 static int
5363 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5364 {
5365 struct hm_map *m = (struct hm_map *)ent->driver_data;
5366 int ret;
5367
5368 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5369 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5370 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5371 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5372 printk(KERN_ERR
5373 "Unknown HFC multiport controller (vendor:%04x device:%04x "
5374 "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5375 pdev->device, pdev->subsystem_vendor,
5376 pdev->subsystem_device);
5377 printk(KERN_ERR
5378 "Please contact the driver maintainer for support.\n");
5379 return -ENODEV;
5380 }
5381 ret = hfcmulti_init(m, pdev, ent);
5382 if (ret)
5383 return ret;
5384 HFC_cnt++;
5385 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5386 return 0;
5387 }
5388
5389 static struct pci_driver hfcmultipci_driver = {
5390 .name = "hfc_multi",
5391 .probe = hfcmulti_probe,
5392 .remove = __devexit_p(hfc_remove_pci),
5393 .id_table = hfmultipci_ids,
5394 };
5395
5396 static void __exit
5397 HFCmulti_cleanup(void)
5398 {
5399 struct hfc_multi *card, *next;
5400
5401 /* get rid of all devices of this driver */
5402 list_for_each_entry_safe(card, next, &HFClist, list)
5403 release_card(card);
5404 pci_unregister_driver(&hfcmultipci_driver);
5405 }
5406
5407 static int __init
5408 HFCmulti_init(void)
5409 {
5410 int err;
5411 int i, xhfc = 0;
5412 struct hm_map m;
5413
5414 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5415
5416 #ifdef IRQ_DEBUG
5417 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5418 #endif
5419
5420 spin_lock_init(&HFClock);
5421 spin_lock_init(&plx_lock);
5422
5423 if (debug & DEBUG_HFCMULTI_INIT)
5424 printk(KERN_DEBUG "%s: init entered\n", __func__);
5425
5426 switch (poll) {
5427 case 0:
5428 poll_timer = 6;
5429 poll = 128;
5430 break;
5431 case 8:
5432 poll_timer = 2;
5433 break;
5434 case 16:
5435 poll_timer = 3;
5436 break;
5437 case 32:
5438 poll_timer = 4;
5439 break;
5440 case 64:
5441 poll_timer = 5;
5442 break;
5443 case 128:
5444 poll_timer = 6;
5445 break;
5446 case 256:
5447 poll_timer = 7;
5448 break;
5449 default:
5450 printk(KERN_ERR
5451 "%s: Wrong poll value (%d).\n", __func__, poll);
5452 err = -EINVAL;
5453 return err;
5454
5455 }
5456
5457 if (!clock)
5458 clock = 1;
5459
5460 /* Register the embedded devices.
5461 * This should be done before the PCI cards registration */
5462 switch (hwid) {
5463 case HWID_MINIP4:
5464 xhfc = 1;
5465 m = hfcm_map[31];
5466 break;
5467 case HWID_MINIP8:
5468 xhfc = 2;
5469 m = hfcm_map[31];
5470 break;
5471 case HWID_MINIP16:
5472 xhfc = 4;
5473 m = hfcm_map[31];
5474 break;
5475 default:
5476 xhfc = 0;
5477 }
5478
5479 for (i = 0; i < xhfc; ++i) {
5480 err = hfcmulti_init(&m, NULL, NULL);
5481 if (err) {
5482 printk(KERN_ERR "error registering embedded driver: "
5483 "%x\n", err);
5484 return err;
5485 }
5486 HFC_cnt++;
5487 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5488 }
5489
5490 /* Register the PCI cards */
5491 err = pci_register_driver(&hfcmultipci_driver);
5492 if (err < 0) {
5493 printk(KERN_ERR "error registering pci driver: %x\n", err);
5494 return err;
5495 }
5496
5497 return 0;
5498 }
5499
5500
5501 module_init(HFCmulti_init);
5502 module_exit(HFCmulti_cleanup);
kernel source for telekom puls (alcatel/mediatek)