2 * linux/arch/arm/common/vic.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/export.h>
23 #include <linux/init.h>
24 #include <linux/list.h>
26 #include <linux/irqdomain.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/device.h>
32 #include <linux/amba/bus.h>
33 #include <linux/irqchip/arm-vic.h>
35 #include <asm/exception.h>
36 #include <asm/mach/irq.h>
40 #define VIC_IRQ_STATUS 0x00
41 #define VIC_FIQ_STATUS 0x04
42 #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
43 #define VIC_INT_SOFT 0x18
44 #define VIC_INT_SOFT_CLEAR 0x1c
45 #define VIC_PROTECT 0x20
46 #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
47 #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
49 #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
50 #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
51 #define VIC_ITCR 0x300 /* VIC test control register */
53 #define VIC_VECT_CNTL_ENABLE (1 << 5)
55 #define VIC_PL192_VECT_ADDR 0xF00
58 * struct vic_device - VIC PM device
59 * @irq: The IRQ number for the base of the VIC.
60 * @base: The register base for the VIC.
61 * @valid_sources: A bitmask of valid interrupts
62 * @resume_sources: A bitmask of interrupts for resume.
63 * @resume_irqs: The IRQs enabled for resume.
64 * @int_select: Save for VIC_INT_SELECT.
65 * @int_enable: Save for VIC_INT_ENABLE.
66 * @soft_int: Save for VIC_INT_SOFT.
67 * @protect: Save for VIC_PROTECT.
68 * @domain: The IRQ domain for the VIC.
80 struct irq_domain
*domain
;
83 /* we cannot allocate memory when VICs are initially registered */
84 static struct vic_device vic_devices
[CONFIG_ARM_VIC_NR
];
88 static void vic_handle_irq(struct pt_regs
*regs
);
91 * vic_init2 - common initialisation code
92 * @base: Base of the VIC.
94 * Common initialisation code for registration
97 static void vic_init2(void __iomem
*base
)
101 for (i
= 0; i
< 16; i
++) {
102 void __iomem
*reg
= base
+ VIC_VECT_CNTL0
+ (i
* 4);
103 writel(VIC_VECT_CNTL_ENABLE
| i
, reg
);
106 writel(32, base
+ VIC_PL190_DEF_VECT_ADDR
);
110 static void resume_one_vic(struct vic_device
*vic
)
112 void __iomem
*base
= vic
->base
;
114 printk(KERN_DEBUG
"%s: resuming vic at %p\n", __func__
, base
);
116 /* re-initialise static settings */
119 writel(vic
->int_select
, base
+ VIC_INT_SELECT
);
120 writel(vic
->protect
, base
+ VIC_PROTECT
);
122 /* set the enabled ints and then clear the non-enabled */
123 writel(vic
->int_enable
, base
+ VIC_INT_ENABLE
);
124 writel(~vic
->int_enable
, base
+ VIC_INT_ENABLE_CLEAR
);
126 /* and the same for the soft-int register */
128 writel(vic
->soft_int
, base
+ VIC_INT_SOFT
);
129 writel(~vic
->soft_int
, base
+ VIC_INT_SOFT_CLEAR
);
132 static void vic_resume(void)
136 for (id
= vic_id
- 1; id
>= 0; id
--)
137 resume_one_vic(vic_devices
+ id
);
140 static void suspend_one_vic(struct vic_device
*vic
)
142 void __iomem
*base
= vic
->base
;
144 printk(KERN_DEBUG
"%s: suspending vic at %p\n", __func__
, base
);
146 vic
->int_select
= readl(base
+ VIC_INT_SELECT
);
147 vic
->int_enable
= readl(base
+ VIC_INT_ENABLE
);
148 vic
->soft_int
= readl(base
+ VIC_INT_SOFT
);
149 vic
->protect
= readl(base
+ VIC_PROTECT
);
151 /* set the interrupts (if any) that are used for
152 * resuming the system */
154 writel(vic
->resume_irqs
, base
+ VIC_INT_ENABLE
);
155 writel(~vic
->resume_irqs
, base
+ VIC_INT_ENABLE_CLEAR
);
158 static int vic_suspend(void)
162 for (id
= 0; id
< vic_id
; id
++)
163 suspend_one_vic(vic_devices
+ id
);
168 struct syscore_ops vic_syscore_ops
= {
169 .suspend
= vic_suspend
,
170 .resume
= vic_resume
,
174 * vic_pm_init - initicall to register VIC pm
176 * This is called via late_initcall() to register
177 * the resources for the VICs due to the early
178 * nature of the VIC's registration.
180 static int __init
vic_pm_init(void)
183 register_syscore_ops(&vic_syscore_ops
);
187 late_initcall(vic_pm_init
);
188 #endif /* CONFIG_PM */
190 static struct irq_chip vic_chip
;
192 static int vic_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
193 irq_hw_number_t hwirq
)
195 struct vic_device
*v
= d
->host_data
;
197 /* Skip invalid IRQs, only register handlers for the real ones */
198 if (!(v
->valid_sources
& (1 << hwirq
)))
200 irq_set_chip_and_handler(irq
, &vic_chip
, handle_level_irq
);
201 irq_set_chip_data(irq
, v
->base
);
202 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
207 * Handle each interrupt in a single VIC. Returns non-zero if we've
208 * handled at least one interrupt. This reads the status register
209 * before handling each interrupt, which is necessary given that
210 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
212 static int handle_one_vic(struct vic_device
*vic
, struct pt_regs
*regs
)
217 while ((stat
= readl_relaxed(vic
->base
+ VIC_IRQ_STATUS
))) {
219 handle_IRQ(irq_find_mapping(vic
->domain
, irq
), regs
);
227 * Keep iterating over all registered VIC's until there are no pending
230 static asmlinkage
void __exception_irq_entry
vic_handle_irq(struct pt_regs
*regs
)
235 for (i
= 0, handled
= 0; i
< vic_id
; ++i
)
236 handled
|= handle_one_vic(&vic_devices
[i
], regs
);
240 static struct irq_domain_ops vic_irqdomain_ops
= {
241 .map
= vic_irqdomain_map
,
242 .xlate
= irq_domain_xlate_onetwocell
,
246 * vic_register() - Register a VIC.
247 * @base: The base address of the VIC.
248 * @irq: The base IRQ for the VIC.
249 * @valid_sources: bitmask of valid interrupts
250 * @resume_sources: bitmask of interrupts allowed for resume sources.
251 * @node: The device tree node associated with the VIC.
253 * Register the VIC with the system device tree so that it can be notified
254 * of suspend and resume requests and ensure that the correct actions are
255 * taken to re-instate the settings on resume.
257 * This also configures the IRQ domain for the VIC.
259 static void __init
vic_register(void __iomem
*base
, unsigned int irq
,
260 u32 valid_sources
, u32 resume_sources
,
261 struct device_node
*node
)
263 struct vic_device
*v
;
266 if (vic_id
>= ARRAY_SIZE(vic_devices
)) {
267 printk(KERN_ERR
"%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__
);
271 v
= &vic_devices
[vic_id
];
273 v
->valid_sources
= valid_sources
;
274 v
->resume_sources
= resume_sources
;
276 set_handle_irq(vic_handle_irq
);
278 v
->domain
= irq_domain_add_simple(node
, fls(valid_sources
), irq
,
279 &vic_irqdomain_ops
, v
);
280 /* create an IRQ mapping for each valid IRQ */
281 for (i
= 0; i
< fls(valid_sources
); i
++)
282 if (valid_sources
& (1 << i
))
283 irq_create_mapping(v
->domain
, i
);
286 static void vic_ack_irq(struct irq_data
*d
)
288 void __iomem
*base
= irq_data_get_irq_chip_data(d
);
289 unsigned int irq
= d
->hwirq
;
290 writel(1 << irq
, base
+ VIC_INT_ENABLE_CLEAR
);
291 /* moreover, clear the soft-triggered, in case it was the reason */
292 writel(1 << irq
, base
+ VIC_INT_SOFT_CLEAR
);
295 static void vic_mask_irq(struct irq_data
*d
)
297 void __iomem
*base
= irq_data_get_irq_chip_data(d
);
298 unsigned int irq
= d
->hwirq
;
299 writel(1 << irq
, base
+ VIC_INT_ENABLE_CLEAR
);
302 static void vic_unmask_irq(struct irq_data
*d
)
304 void __iomem
*base
= irq_data_get_irq_chip_data(d
);
305 unsigned int irq
= d
->hwirq
;
306 writel(1 << irq
, base
+ VIC_INT_ENABLE
);
309 #if defined(CONFIG_PM)
310 static struct vic_device
*vic_from_irq(unsigned int irq
)
312 struct vic_device
*v
= vic_devices
;
313 unsigned int base_irq
= irq
& ~31;
316 for (id
= 0; id
< vic_id
; id
++, v
++) {
317 if (v
->irq
== base_irq
)
324 static int vic_set_wake(struct irq_data
*d
, unsigned int on
)
326 struct vic_device
*v
= vic_from_irq(d
->irq
);
327 unsigned int off
= d
->hwirq
;
333 if (!(bit
& v
->resume_sources
))
337 v
->resume_irqs
|= bit
;
339 v
->resume_irqs
&= ~bit
;
344 #define vic_set_wake NULL
345 #endif /* CONFIG_PM */
347 static struct irq_chip vic_chip
= {
349 .irq_ack
= vic_ack_irq
,
350 .irq_mask
= vic_mask_irq
,
351 .irq_unmask
= vic_unmask_irq
,
352 .irq_set_wake
= vic_set_wake
,
355 static void __init
vic_disable(void __iomem
*base
)
357 writel(0, base
+ VIC_INT_SELECT
);
358 writel(0, base
+ VIC_INT_ENABLE
);
359 writel(~0, base
+ VIC_INT_ENABLE_CLEAR
);
360 writel(0, base
+ VIC_ITCR
);
361 writel(~0, base
+ VIC_INT_SOFT_CLEAR
);
364 static void __init
vic_clear_interrupts(void __iomem
*base
)
368 writel(0, base
+ VIC_PL190_VECT_ADDR
);
369 for (i
= 0; i
< 19; i
++) {
372 value
= readl(base
+ VIC_PL190_VECT_ADDR
);
373 writel(value
, base
+ VIC_PL190_VECT_ADDR
);
378 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
379 * The original cell has 32 interrupts, while the modified one has 64,
380 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
381 * the probe function is called twice, with base set to offset 000
382 * and 020 within the page. We call this "second block".
384 static void __init
vic_init_st(void __iomem
*base
, unsigned int irq_start
,
385 u32 vic_sources
, struct device_node
*node
)
388 int vic_2nd_block
= ((unsigned long)base
& ~PAGE_MASK
) != 0;
390 /* Disable all interrupts initially. */
394 * Make sure we clear all existing interrupts. The vector registers
395 * in this cell are after the second block of general registers,
396 * so we can address them using standard offsets, but only from
397 * the second base address, which is 0x20 in the page
400 vic_clear_interrupts(base
);
402 /* ST has 16 vectors as well, but we don't enable them by now */
403 for (i
= 0; i
< 16; i
++) {
404 void __iomem
*reg
= base
+ VIC_VECT_CNTL0
+ (i
* 4);
408 writel(32, base
+ VIC_PL190_DEF_VECT_ADDR
);
411 vic_register(base
, irq_start
, vic_sources
, 0, node
);
414 void __init
__vic_init(void __iomem
*base
, int irq_start
,
415 u32 vic_sources
, u32 resume_sources
,
416 struct device_node
*node
)
420 enum amba_vendor vendor
;
422 /* Identify which VIC cell this one is, by reading the ID */
423 for (i
= 0; i
< 4; i
++) {
425 addr
= (void __iomem
*)((u32
)base
& PAGE_MASK
) + 0xfe0 + (i
* 4);
426 cellid
|= (readl(addr
) & 0xff) << (8 * i
);
428 vendor
= (cellid
>> 12) & 0xff;
429 printk(KERN_INFO
"VIC @%p: id 0x%08x, vendor 0x%02x\n",
430 base
, cellid
, vendor
);
434 vic_init_st(base
, irq_start
, vic_sources
, node
);
437 printk(KERN_WARNING
"VIC: unknown vendor, continuing anyways\n");
439 case AMBA_VENDOR_ARM
:
443 /* Disable all interrupts initially. */
446 /* Make sure we clear all existing interrupts */
447 vic_clear_interrupts(base
);
451 vic_register(base
, irq_start
, vic_sources
, resume_sources
, node
);
455 * vic_init() - initialise a vectored interrupt controller
456 * @base: iomem base address
457 * @irq_start: starting interrupt number, must be muliple of 32
458 * @vic_sources: bitmask of interrupt sources to allow
459 * @resume_sources: bitmask of interrupt sources to allow for resume
461 void __init
vic_init(void __iomem
*base
, unsigned int irq_start
,
462 u32 vic_sources
, u32 resume_sources
)
464 __vic_init(base
, irq_start
, vic_sources
, resume_sources
, NULL
);
468 int __init
vic_of_init(struct device_node
*node
, struct device_node
*parent
)
472 if (WARN(parent
, "non-root VICs are not supported"))
475 regs
= of_iomap(node
, 0);
480 * Passing 0 as first IRQ makes the simple domain allocate descriptors
482 __vic_init(regs
, 0, ~0, ~0, node
);
486 IRQCHIP_DECLARE(arm_pl190_vic
, "arm,pl190-vic", vic_of_init
);
487 IRQCHIP_DECLARE(arm_pl192_vic
, "arm,pl192-vic", vic_of_init
);
488 IRQCHIP_DECLARE(arm_versatile_vic
, "arm,versatile-vic", vic_of_init
);
489 #endif /* CONFIG OF */