drivers/iommu/omap-iommu2.c

   1 /*
   2  * omap iommu: omap2/3 architecture specific functions
   3  *
   4  * Copyright (C) 2008-2009 Nokia Corporation
   5  *
   6  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
   7  *              Paul Mundt and Toshihiro Kobayashi
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/err.h>
  15 #include <linux/device.h>
  16 #include <linux/io.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/module.h>
  19 #include <linux/omap-iommu.h>
  20 #include <linux/slab.h>
  21 #include <linux/stringify.h>
  22
  23 #include <plat/iommu.h>
  24 #include "omap-iommu.h"
  25
  26 /*
  27  * omap2 architecture specific register bit definitions
  28  */
  29 #define IOMMU_ARCH_VERSION      0x00000011
  30
  31 /* SYSCONF */
  32 #define MMU_SYS_IDLE_SHIFT      3
  33 #define MMU_SYS_IDLE_FORCE      (0 << MMU_SYS_IDLE_SHIFT)
  34 #define MMU_SYS_IDLE_NONE       (1 << MMU_SYS_IDLE_SHIFT)
  35 #define MMU_SYS_IDLE_SMART      (2 << MMU_SYS_IDLE_SHIFT)
  36 #define MMU_SYS_IDLE_MASK       (3 << MMU_SYS_IDLE_SHIFT)
  37
  38 #define MMU_SYS_SOFTRESET       (1 << 1)
  39 #define MMU_SYS_AUTOIDLE        1
  40
  41 /* SYSSTATUS */
  42 #define MMU_SYS_RESETDONE       1
  43
  44 /* IRQSTATUS & IRQENABLE */
  45 #define MMU_IRQ_MULTIHITFAULT   (1 << 4)
  46 #define MMU_IRQ_TABLEWALKFAULT  (1 << 3)
  47 #define MMU_IRQ_EMUMISS         (1 << 2)
  48 #define MMU_IRQ_TRANSLATIONFAULT        (1 << 1)
  49 #define MMU_IRQ_TLBMISS         (1 << 0)
  50
  51 #define __MMU_IRQ_FAULT         \
  52         (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
  53 #define MMU_IRQ_MASK            \
  54         (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
  55 #define MMU_IRQ_TWL_MASK        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
  56 #define MMU_IRQ_TLB_MISS_MASK   (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
  57
  58 /* MMU_CNTL */
  59 #define MMU_CNTL_SHIFT          1
  60 #define MMU_CNTL_MASK           (7 << MMU_CNTL_SHIFT)
  61 #define MMU_CNTL_EML_TLB        (1 << 3)
  62 #define MMU_CNTL_TWL_EN         (1 << 2)
  63 #define MMU_CNTL_MMU_EN         (1 << 1)
  64
  65 #define get_cam_va_mask(pgsz)                           \
  66         (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
  67          ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
  68          ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
  69          ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
  70
  71 /* IOMMU errors */
  72 #define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
  73 #define OMAP_IOMMU_ERR_TRANS_FAULT      (1 << 1)
  74 #define OMAP_IOMMU_ERR_EMU_MISS         (1 << 2)
  75 #define OMAP_IOMMU_ERR_TBLWALK_FAULT    (1 << 3)
  76 #define OMAP_IOMMU_ERR_MULTIHIT_FAULT   (1 << 4)
  77
  78 static void __iommu_set_twl(struct omap_iommu *obj, bool on)
  79 {
  80         u32 l = iommu_read_reg(obj, MMU_CNTL);
  81
  82         if (on)
  83                 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
  84         else
  85                 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
  86
  87         l &= ~MMU_CNTL_MASK;
  88         if (on)
  89                 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
  90         else
  91                 l |= (MMU_CNTL_MMU_EN);
  92
  93         iommu_write_reg(obj, l, MMU_CNTL);
  94 }
  95
  96
  97 static int omap2_iommu_enable(struct omap_iommu *obj)
  98 {
  99         u32 l, pa;
 100         unsigned long timeout;
 101
 102         if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
 103                 return -EINVAL;
 104
 105         pa = virt_to_phys(obj->iopgd);
 106         if (!IS_ALIGNED(pa, SZ_16K))
 107                 return -EINVAL;
 108
 109         iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
 110
 111         timeout = jiffies + msecs_to_jiffies(20);
 112         do {
 113                 l = iommu_read_reg(obj, MMU_SYSSTATUS);
 114                 if (l & MMU_SYS_RESETDONE)
 115                         break;
 116         } while (!time_after(jiffies, timeout));
 117
 118         if (!(l & MMU_SYS_RESETDONE)) {
 119                 dev_err(obj->dev, "can't take mmu out of reset\n");
 120                 return -ENODEV;
 121         }
 122
 123         l = iommu_read_reg(obj, MMU_REVISION);
 124         dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
 125                  (l >> 4) & 0xf, l & 0xf);
 126
 127         l = iommu_read_reg(obj, MMU_SYSCONFIG);
 128         l &= ~MMU_SYS_IDLE_MASK;
 129         l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
 130         iommu_write_reg(obj, l, MMU_SYSCONFIG);
 131
 132         iommu_write_reg(obj, pa, MMU_TTB);
 133
 134         __iommu_set_twl(obj, true);
 135
 136         return 0;
 137 }
 138
 139 static void omap2_iommu_disable(struct omap_iommu *obj)
 140 {
 141         u32 l = iommu_read_reg(obj, MMU_CNTL);
 142
 143         l &= ~MMU_CNTL_MASK;
 144         iommu_write_reg(obj, l, MMU_CNTL);
 145         iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
 146
 147         dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 148 }
 149
 150 static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
 151 {
 152         __iommu_set_twl(obj, false);
 153 }
 154
 155 static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
 156 {
 157         u32 stat, da;
 158         u32 errs = 0;
 159
 160         stat = iommu_read_reg(obj, MMU_IRQSTATUS);
 161         stat &= MMU_IRQ_MASK;
 162         if (!stat) {
 163                 *ra = 0;
 164                 return 0;
 165         }
 166
 167         da = iommu_read_reg(obj, MMU_FAULT_AD);
 168         *ra = da;
 169
 170         if (stat & MMU_IRQ_TLBMISS)
 171                 errs |= OMAP_IOMMU_ERR_TLB_MISS;
 172         if (stat & MMU_IRQ_TRANSLATIONFAULT)
 173                 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
 174         if (stat & MMU_IRQ_EMUMISS)
 175                 errs |= OMAP_IOMMU_ERR_EMU_MISS;
 176         if (stat & MMU_IRQ_TABLEWALKFAULT)
 177                 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
 178         if (stat & MMU_IRQ_MULTIHITFAULT)
 179                 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
 180         iommu_write_reg(obj, stat, MMU_IRQSTATUS);
 181
 182         return errs;
 183 }
 184
 185 static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
 186 {
 187         cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
 188         cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
 189 }
 190
 191 static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
 192 {
 193         iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
 194         iommu_write_reg(obj, cr->ram, MMU_RAM);
 195 }
 196
 197 static u32 omap2_cr_to_virt(struct cr_regs *cr)
 198 {
 199         u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
 200         u32 mask = get_cam_va_mask(cr->cam & page_size);
 201
 202         return cr->cam & mask;
 203 }
 204
 205 static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
 206                                                 struct iotlb_entry *e)
 207 {
 208         struct cr_regs *cr;
 209
 210         if (e->da & ~(get_cam_va_mask(e->pgsz))) {
 211                 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
 212                         e->da);
 213                 return ERR_PTR(-EINVAL);
 214         }
 215
 216         cr = kmalloc(sizeof(*cr), GFP_KERNEL);
 217         if (!cr)
 218                 return ERR_PTR(-ENOMEM);
 219
 220         cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
 221         cr->ram = e->pa | e->endian | e->elsz | e->mixed;
 222
 223         return cr;
 224 }
 225
 226 static inline int omap2_cr_valid(struct cr_regs *cr)
 227 {
 228         return cr->cam & MMU_CAM_V;
 229 }
 230
 231 static u32 omap2_get_pte_attr(struct iotlb_entry *e)
 232 {
 233         u32 attr;
 234
 235         attr = e->mixed << 5;
 236         attr |= e->endian;
 237         attr |= e->elsz >> 3;
 238         attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
 239                         (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
 240         return attr;
 241 }
 242
 243 static ssize_t
 244 omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
 245 {
 246         char *p = buf;
 247
 248         /* FIXME: Need more detail analysis of cam/ram */
 249         p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
 250                                         (cr->cam & MMU_CAM_P) ? 1 : 0);
 251
 252         return p - buf;
 253 }
 254
 255 #define pr_reg(name)                                                    \
 256         do {                                                            \
 257                 ssize_t bytes;                                          \
 258                 const char *str = "%20s: %08x\n";                       \
 259                 const int maxcol = 32;                                  \
 260                 bytes = snprintf(p, maxcol, str, __stringify(name),     \
 261                                  iommu_read_reg(obj, MMU_##name));      \
 262                 p += bytes;                                             \
 263                 len -= bytes;                                           \
 264                 if (len < maxcol)                                       \
 265                         goto out;                                       \
 266         } while (0)
 267
 268 static ssize_t
 269 omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
 270 {
 271         char *p = buf;
 272
 273         pr_reg(REVISION);
 274         pr_reg(SYSCONFIG);
 275         pr_reg(SYSSTATUS);
 276         pr_reg(IRQSTATUS);
 277         pr_reg(IRQENABLE);
 278         pr_reg(WALKING_ST);
 279         pr_reg(CNTL);
 280         pr_reg(FAULT_AD);
 281         pr_reg(TTB);
 282         pr_reg(LOCK);
 283         pr_reg(LD_TLB);
 284         pr_reg(CAM);
 285         pr_reg(RAM);
 286         pr_reg(GFLUSH);
 287         pr_reg(FLUSH_ENTRY);
 288         pr_reg(READ_CAM);
 289         pr_reg(READ_RAM);
 290         pr_reg(EMU_FAULT_AD);
 291 out:
 292         return p - buf;
 293 }
 294
 295 static void omap2_iommu_save_ctx(struct omap_iommu *obj)
 296 {
 297         int i;
 298         u32 *p = obj->ctx;
 299
 300         for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
 301                 p[i] = iommu_read_reg(obj, i * sizeof(u32));
 302                 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
 303         }
 304
 305         BUG_ON(p[0] != IOMMU_ARCH_VERSION);
 306 }
 307
 308 static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
 309 {
 310         int i;
 311         u32 *p = obj->ctx;
 312
 313         for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
 314                 iommu_write_reg(obj, p[i], i * sizeof(u32));
 315                 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
 316         }
 317
 318         BUG_ON(p[0] != IOMMU_ARCH_VERSION);
 319 }
 320
 321 static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
 322 {
 323         e->da           = cr->cam & MMU_CAM_VATAG_MASK;
 324         e->pa           = cr->ram & MMU_RAM_PADDR_MASK;
 325         e->valid        = cr->cam & MMU_CAM_V;
 326         e->pgsz         = cr->cam & MMU_CAM_PGSZ_MASK;
 327         e->endian       = cr->ram & MMU_RAM_ENDIAN_MASK;
 328         e->elsz         = cr->ram & MMU_RAM_ELSZ_MASK;
 329         e->mixed        = cr->ram & MMU_RAM_MIXED;
 330 }
 331
 332 static const struct iommu_functions omap2_iommu_ops = {
 333         .version        = IOMMU_ARCH_VERSION,
 334
 335         .enable         = omap2_iommu_enable,
 336         .disable        = omap2_iommu_disable,
 337         .set_twl        = omap2_iommu_set_twl,
 338         .fault_isr      = omap2_iommu_fault_isr,
 339
 340         .tlb_read_cr    = omap2_tlb_read_cr,
 341         .tlb_load_cr    = omap2_tlb_load_cr,
 342
 343         .cr_to_e        = omap2_cr_to_e,
 344         .cr_to_virt     = omap2_cr_to_virt,
 345         .alloc_cr       = omap2_alloc_cr,
 346         .cr_valid       = omap2_cr_valid,
 347         .dump_cr        = omap2_dump_cr,
 348
 349         .get_pte_attr   = omap2_get_pte_attr,
 350
 351         .save_ctx       = omap2_iommu_save_ctx,
 352         .restore_ctx    = omap2_iommu_restore_ctx,
 353         .dump_ctx       = omap2_iommu_dump_ctx,
 354 };
 355
 356 static int __init omap2_iommu_init(void)
 357 {
 358         return omap_install_iommu_arch(&omap2_iommu_ops);
 359 }
 360 module_init(omap2_iommu_init);
 361
 362 static void __exit omap2_iommu_exit(void)
 363 {
 364         omap_uninstall_iommu_arch(&omap2_iommu_ops);
 365 }
 366 module_exit(omap2_iommu_exit);
 367
 368 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
 369 MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
 370 MODULE_LICENSE("GPL v2");