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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / input / touchscreen / mediatek / GT9XX_hotknot / gt9xx_update.c
1 /* drivers/input/touchscreen/gt9xx_update.c
2 *
3 * 2010 - 2012 Goodix Technology.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be a reference
11 * to you, when you are integrating the GOODiX's CTP IC into your system,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * Version: 2.0
17 * Revision Record:
18 * V1.0: first release. by Andrew, 2012/08/27.
19 * V1.2: modify gt9110p pid map, by Andrew, 2012/10/15
20 * V1.4:
21 * 1. modify gup_enter_update_mode,
22 * 2. rewrite i2c read/write func
23 * 3. check update file checksum
24 * by Andrew, 2012/12/12
25 * v1.6:
26 * 1. delete GTP_FW_DOWNLOAD related things.
27 * 2. add GTP_HEADER_FW_UPDATE switch to update fw by gtp_default_fw in *.h directly
28 * by Meta, 2013/04/18
29 * V2.0:
30 * 1. GT9XXF main clock calibration
31 * 2. header fw update no fs related
32 * 3. update file searching optimization
33 * 4. config update as module, switchable
34 * by Meta, 2013/08/28
35 */
36 #include "tpd.h"
37 #include <linux/interrupt.h>
38 #include <cust_eint.h>
39 #include <linux/i2c.h>
40 #include <linux/sched.h>
41 #include <linux/kthread.h>
42 #include <linux/rtpm_prio.h>
43 #include <linux/wait.h>
44 #include <linux/time.h>
45 #include <linux/delay.h>
46 #include <linux/namei.h>
47 #include <linux/mount.h>
48 #include "cust_gpio_usage.h"
49 #include <asm/uaccess.h>
50 #define GUP_FW_INFO
51 #include "tpd_custom_gt9xx.h"
52
53 #if ( (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE) || GTP_COMPATIBLE_MODE )
54 #include "gt9xx_firmware.h"
55 #endif
56
57
58 #define GUP_REG_HW_INFO 0x4220
59 #define GUP_REG_FW_MSG 0x41E4
60 #define GUP_REG_PID_VID 0x8140
61
62 #define GUP_SEARCH_FILE_TIMES 50
63 #define UPDATE_FILE_PATH_1 "/data/_goodix_update_.bin"
64 #define UPDATE_FILE_PATH_2 "/sdcard/_goodix_update_.bin"
65
66 #define CONFIG_FILE_PATH_1 "/data/_goodix_config_.cfg"
67 #define CONFIG_FILE_PATH_2 "/sdcard/_goodix_config_.cfg"
68
69 #define FW_HEAD_LENGTH 14
70 #define FW_DOWNLOAD_LENGTH 0x4000
71 #define FW_SECTION_LENGTH 0x2000
72 #define FW_DSP_ISP_LENGTH 0x1000
73 #define FW_DSP_LENGTH 0x1000
74 #define FW_BOOT_LENGTH 0x800
75 #define FW_SS51_LENGTH (4 * FW_SECTION_LENGTH)
76 #define FW_BOOT_ISP_LENGTH 0x800 // 2k
77 #define FW_LINK_LENGTH 0x3000 // 12k
78 #define FW_APP_CODE_LENGTH (4 * FW_SECTION_LENGTH) // 32k
79
80 #define FIRMWARE_LENGTH (FW_SS51_LENGTH + FW_DSP_LENGTH + FW_BOOT_LENGTH + FW_DSP_ISP_LENGTH + FW_BOOT_ISP_LENGTH + FW_APP_CODE_LENGTH)
81
82 #define FW_HOTKNOT_LENGTH 0x3000
83 #define PACK_SIZE 256
84 #define MAX_FRAME_CHECK_TIME 5
85
86
87 #define _bRW_MISCTL__SRAM_BANK 0x4048
88 #define _bRW_MISCTL__MEM_CD_EN 0x4049
89 #define _bRW_MISCTL__CACHE_EN 0x404B
90 #define _bRW_MISCTL__TMR0_EN 0x40B0
91 #define _rRW_MISCTL__SWRST_B0_ 0x4180
92 #define _bWO_MISCTL__CPU_SWRST_PULSE 0x4184
93 #define _rRW_MISCTL__BOOTCTL_B0_ 0x4190
94 #define _rRW_MISCTL__BOOT_OPT_B0_ 0x4218
95 #define _rRW_MISCTL__BOOT_CTL_ 0x5094
96
97 #define AUTO_SEARCH_BIN 0x01
98 #define AUTO_SEARCH_CFG 0x02
99 #define BIN_FILE_READY 0x80
100 #define CFG_FILE_READY 0x08
101 #define HEADER_FW_READY 0x01
102
103 #define FAIL 0
104 #define SUCCESS 1
105
106 #define MAIN_SYSTEM_PATH "/sdcard/goodix/_main_.bin"
107 #define HOTKNOT_SYSTEM_PATH "/sdcard/goodix/_hotknot_.bin"
108 #define FX_SYSTEM_PATH "/sdcard/goodix/_authorization_.bin"
109
110 #define GTP_FORCE_UPDATE_FW 0
111 #define GT917S_UPDATE_RULE 1
112
113 #pragma pack(1)
114 typedef struct
115 {
116 u8 hw_info[4]; //hardware info//
117 u8 pid[8]; //product id //
118 u16 vid; //version id //
119 } st_fw_head;
120 #pragma pack()
121
122 typedef struct
123 {
124 u8 force_update;
125 u8 fw_flag;
126 struct file *file;
127 struct file *cfg_file;
128 st_fw_head ic_fw_msg;
129 mm_segment_t old_fs;
130 u32 fw_total_len;
131 u32 fw_burned_len;
132 } st_update_msg;
133
134 st_update_msg update_msg;
135 extern struct i2c_client *i2c_client_point;
136 extern unsigned int touch_irq;
137 u16 show_len;
138 u16 total_len;
139 extern u8 fw_updating;
140 extern u8 cfg_len;
141 extern struct mutex i2c_access;
142 u8 searching_file = 0;
143 u8 got_file_flag = 0;
144 u8 load_fw_process = 0;
145
146 #if GTP_ESD_PROTECT
147 extern void gtp_esd_switch(struct i2c_client *client, s32 on);
148 #endif
149
150 #if (GTP_ESD_PROTECT || GTP_COMPATIBLE_MODE)
151 extern u8 is_reseting;
152 #endif
153
154
155 #if GTP_COMPATIBLE_MODE
156 extern CHIP_TYPE_T gtp_chip_type;
157 extern u8 rqst_processing;
158 extern u8 gtp_fw_startup(struct i2c_client *client);
159 static u8 gup_check_and_repair(struct i2c_client *, s32 , u8 *, u32 );
160 s32 gup_recovery_main_system(void);
161 s32 gup_load_main_system(char *filepath);
162 s32 gup_fw_download_proc(void *dir, u8 dwn_mode);
163 char * gup_load_fw_from_file(char *filepath);
164 s32 gup_load_system(char *firmware, s32 length, u8 need_check);
165 #endif
166
167 #define _CLOSE_FILE(p_file) if (p_file && !IS_ERR(p_file)) \
168 { \
169 filp_close(p_file, NULL); \
170 }
171
172
173 static u8 gup_burn_fw_app_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd );
174
175 static s32 gup_i2c_read(struct i2c_client *client, u8 *buf, s32 len)
176 {
177 s32 ret = -1;
178 u16 addr = (buf[0] << 8) + buf[1];
179
180 ret = i2c_read_bytes(client, addr, &buf[2], len - 2);
181
182 if (!ret)
183 {
184 return 2;
185 }
186 else
187 {
188 return ret;
189 }
190 }
191
192 static s32 gup_i2c_write(struct i2c_client *client, u8 *buf, s32 len)
193 {
194 s32 ret = -1;
195 u16 addr = (buf[0] << 8) + buf[1];
196
197 ret = i2c_write_bytes(client, addr, &buf[2], len - 2);
198
199 if (!ret)
200 {
201 return 1;
202 }
203 else
204 {
205 return ret;
206 }
207 }
208
209 static u8 gup_get_ic_msg(struct i2c_client *client, u16 addr, u8 *msg, s32 len)
210 {
211 s32 i = 0;
212
213 msg[0] = (addr >> 8) & 0xff;
214 msg[1] = addr & 0xff;
215
216 for (i = 0; i < 5; i++)
217 {
218 if (gup_i2c_read(client, msg, GTP_ADDR_LENGTH + len) > 0)
219 {
220 break;
221 }
222 }
223
224 if (i >= 5)
225 {
226 GTP_ERROR("Read data from 0x%02x%02x failed!", msg[0], msg[1]);
227 return FAIL;
228 }
229
230 return SUCCESS;
231 }
232
233 static u8 gup_set_ic_msg(struct i2c_client *client, u16 addr, u8 val)
234 {
235 s32 i = 0;
236 u8 msg[3];
237
238 msg[0] = (addr >> 8) & 0xff;
239 msg[1] = addr & 0xff;
240 msg[2] = val;
241
242 for (i = 0; i < 5; i++)
243 {
244 if (gup_i2c_write(client, msg, GTP_ADDR_LENGTH + 1) > 0)
245 {
246 break;
247 }
248 }
249
250 if (i >= 5)
251 {
252 GTP_ERROR("Set data to 0x%02x%02x failed!", msg[0], msg[1]);
253 return FAIL;
254 }
255
256 return SUCCESS;
257 }
258
259 static u8 gup_get_ic_fw_msg(struct i2c_client *client)
260 {
261 s32 ret = -1;
262 u8 retry = 0;
263 u8 buf[16];
264 u8 i;
265
266 //step1:get hardware info
267 ret = gtp_i2c_read_dbl_check(client, GUP_REG_HW_INFO, &buf[GTP_ADDR_LENGTH], 4);
268 if (FAIL == ret)
269 {
270 GTP_ERROR("[get_ic_fw_msg]get hw_info failed,exit");
271 return FAIL;
272 }
273
274 // buf[2~5]: 00 06 90 00
275 // hw_info: 00 90 06 00
276 for (i = 0; i < 4; i++)
277 {
278 update_msg.ic_fw_msg.hw_info[i] = buf[GTP_ADDR_LENGTH + 3 - i];
279 }
280
281 GTP_INFO("IC Hardware info:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
282 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
283
284 //step2:get firmware message
285 for (retry = 0; retry < 2; retry++)
286 {
287 ret = gup_get_ic_msg(client, GUP_REG_FW_MSG, buf, 1);
288
289 if (FAIL == ret)
290 {
291 GTP_ERROR("Read firmware message fail.");
292 return ret;
293 }
294
295 update_msg.force_update = buf[GTP_ADDR_LENGTH];
296
297 if ((0xBE != update_msg.force_update) && (!retry))
298 {
299 GTP_INFO("The check sum in ic is error.");
300 GTP_INFO("The IC will be updated by force.");
301 continue;
302 }
303 break;
304 }
305
306 GTP_INFO("IC force update flag:0x%x", update_msg.force_update);
307
308 //step3:get pid & vid
309 ret = gtp_i2c_read_dbl_check(client, GUP_REG_PID_VID, &buf[GTP_ADDR_LENGTH], 6);
310 if (FAIL == ret)
311 {
312 GTP_ERROR("[get_ic_fw_msg]get pid & vid failed,exit");
313 return FAIL;
314 }
315
316 memset(update_msg.ic_fw_msg.pid, 0, sizeof(update_msg.ic_fw_msg.pid));
317 memcpy(update_msg.ic_fw_msg.pid, &buf[GTP_ADDR_LENGTH], 4);
318
319
320 //GT9XX PID MAPPING
321 /*|-----FLASH-----RAM-----|
322 |------918------918-----|
323 |------968------968-----|
324 |------913------913-----|
325 |------913P-----913P----|
326 |------927------927-----|
327 |------927P-----927P----|
328 |------9110-----9110----|
329 |------9110P----9111----|*/
330 if(update_msg.ic_fw_msg.pid[0] != 0)
331 {
332 if (!memcmp(update_msg.ic_fw_msg.pid, "9111", 4))
333 {
334 GTP_INFO("IC Mapping Product id:%s", update_msg.ic_fw_msg.pid);
335 memcpy(update_msg.ic_fw_msg.pid, "9110P", 5);
336 }
337 }
338
339 update_msg.ic_fw_msg.vid = buf[GTP_ADDR_LENGTH + 4] + (buf[GTP_ADDR_LENGTH + 5] << 8);
340 return SUCCESS;
341 }
342
343 s32 gup_enter_update_mode(struct i2c_client *client)
344 {
345 s32 ret = -1;
346 s32 retry = 0;
347 u8 rd_buf[3];
348
349 //step1:RST output low last at least 2ms
350 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
351 msleep(2);
352
353 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
354 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
355 msleep(2);
356
357 //step3:RST output high reset guitar
358 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
359
360 //20121211 modify start
361 msleep(5);
362 while(retry++ < 200)
363 {
364 //step4:Hold ss51 & dsp
365 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
366 if(ret <= 0)
367 {
368 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
369 continue;
370 }
371
372 //step5:Confirm hold
373 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
374 if(ret <= 0)
375 {
376 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
377 continue;
378 }
379 if(0x0C == rd_buf[GTP_ADDR_LENGTH])
380 {
381 GTP_DEBUG("Hold ss51 & dsp confirm SUCCESS");
382 break;
383 }
384 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
385 }
386 if(retry >= 200)
387 {
388 GTP_ERROR("Enter update Hold ss51 failed.");
389 return FAIL;
390 }
391
392 //step6:DSP_CK and DSP_ALU_CK PowerOn
393 ret = gup_set_ic_msg(client, 0x4010, 0x00);
394
395 //20121211 modify end
396 return ret;
397 }
398
399 void gup_leave_update_mode(void)
400 {
401 GTP_GPIO_AS_INT(GTP_INT_PORT);
402
403 GTP_DEBUG("[leave_update_mode]reset chip.");
404 #if GTP_COMPATIBLE_MODE
405 if (CHIP_TYPE_GT9F == gtp_chip_type)
406 {
407 force_reset_guitar();
408 GTP_INFO("User layer reset GT9XXF.");
409 return;
410 }
411 #endif
412 gtp_reset_guitar(i2c_client_point, 20);
413 }
414
415 static u8 gup_enter_update_judge(st_fw_head *fw_head)
416 {
417 u16 u16_tmp;
418 s32 i = 0;
419 u32 fw_len = 0;
420 s32 pid_cmp_len = 0;
421
422 //Get the correct nvram data
423 //The correct conditions:
424 //1. the hardware info is the same
425 //2. the product id is the same
426 //3. the firmware version in update file is greater than the firmware version in ic
427 //or the check sum in ic is wrong
428
429 u16_tmp = fw_head->vid;
430 fw_head->vid = (u16)(u16_tmp >> 8) + (u16)(u16_tmp << 8);
431
432 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
433 GTP_INFO("FILE PID:%s", fw_head->pid);
434 GTP_INFO("FILE VID:%04x", fw_head->vid);
435 GTP_INFO("IC HARDWARE INFO:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
436 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
437 GTP_INFO("IC PID:%s", update_msg.ic_fw_msg.pid);
438 GTP_INFO("IC VID:%04x", update_msg.ic_fw_msg.vid);
439
440 if (!memcmp(fw_head->hw_info, update_msg.ic_fw_msg.hw_info, sizeof(update_msg.ic_fw_msg.hw_info)))
441 {
442 fw_len = 42 * 1024;
443 }
444 else
445 {
446 fw_len = fw_head->hw_info[3];
447 fw_len += (((u32)fw_head->hw_info[2]) << 8);
448 fw_len += (((u32)fw_head->hw_info[1]) << 16);
449 fw_len += (((u32)fw_head->hw_info[0]) << 24);
450 }
451 if (update_msg.fw_total_len != fw_len)
452 {
453 //GTP_ERROR("Inconsistent firmware size, Update aborted! Default size: %d(%dK), actual size: %d(%dK)", fw_len, fw_len/1024, update_msg.fw_total_len, update_msg.fw_total_len/1024);
454 return FAIL;
455 }
456 if ((update_msg.fw_total_len < 36*1024) || (update_msg.fw_total_len > 128*1024))
457 {
458 GTP_ERROR("Invalid firmware length(%d), update aborted!", update_msg.fw_total_len);
459 return FAIL;
460 }
461 GTP_INFO("Firmware length:%d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
462
463 if (update_msg.force_update != 0xBE)
464 {
465 GTP_INFO("FW chksum error,need enter update.");
466 return SUCCESS;
467 }
468
469 // 20130523 start
470 if (strlen(update_msg.ic_fw_msg.pid) < 3)
471 {
472 GTP_INFO("Illegal IC pid, need enter update");
473 return SUCCESS;
474 }
475 else
476 {
477 for (i = 0; i < 3; i++)
478 {
479 if ((update_msg.ic_fw_msg.pid[i] < 0x30) || (update_msg.ic_fw_msg.pid[i] > 0x39))
480 {
481 GTP_INFO("Illegal IC pid, out of bound, need enter update");
482 return SUCCESS;
483 }
484 }
485 }
486 // 20130523 end
487
488 pid_cmp_len = strlen(fw_head->pid);
489 if (pid_cmp_len < strlen(update_msg.ic_fw_msg.pid))
490 {
491 pid_cmp_len = strlen(update_msg.ic_fw_msg.pid);
492 }
493
494 if ((!memcmp(fw_head->pid, update_msg.ic_fw_msg.pid, pid_cmp_len)) ||
495 (!memcmp(update_msg.ic_fw_msg.pid, "91XX", 4))||
496 (!memcmp(fw_head->pid, "91XX", 4)))
497 {
498 if(!memcmp(fw_head->pid, "91XX", 4))
499 {
500 GTP_DEBUG("Force none same pid update mode.");
501 }
502 else
503 {
504 GTP_DEBUG("Get the same pid.");
505 }
506
507 //The third condition
508 if (fw_head->vid > update_msg.ic_fw_msg.vid)
509 {
510
511 GTP_INFO("Need enter update.");
512 return SUCCESS;
513 }
514
515 GTP_INFO("Don't meet the third condition.");
516 GTP_ERROR("File VID <= IC VID, update aborted!");
517 }
518 else
519 {
520 GTP_ERROR("File PID != IC PID, update aborted!");
521 }
522
523 return FAIL;
524 }
525
526 #if GTP_AUTO_UPDATE_CFG
527 static u8 ascii2hex(u8 a)
528 {
529 s8 value = 0;
530
531 if(a >= '0' && a <= '9')
532 {
533 value = a - '0';
534 }
535 else if(a >= 'A' && a <= 'F')
536 {
537 value = a - 'A' + 0x0A;
538 }
539 else if(a >= 'a' && a <= 'f')
540 {
541 value = a - 'a' + 0x0A;
542 }
543 else
544 {
545 value = 0xff;
546 }
547
548 return value;
549 }
550 static s8 gup_update_config(struct i2c_client *client)
551 {
552 s32 file_len = 0;
553 s32 ret = 0;
554 s32 i = 0;
555 s32 file_cfg_len = 0;
556 s32 chip_cfg_len = 0;
557 s32 count = 0;
558 u8 *buf;
559 u8 *pre_buf;
560 u8 *file_config;
561 //u8 checksum = 0;
562
563 if(NULL == update_msg.cfg_file)
564 {
565 GTP_ERROR("[update_cfg]No need to upgrade config!");
566 return FAIL;
567 }
568 file_len = update_msg.cfg_file->f_op->llseek(update_msg.cfg_file, 0, SEEK_END);
569
570 chip_cfg_len = cfg_len;
571
572 GTP_DEBUG("[update_cfg]config file len:%d", file_len);
573 GTP_DEBUG("[update_cfg]need config len:%d",chip_cfg_len);
574 if((file_len+5) < chip_cfg_len*5)
575 {
576 GTP_ERROR("Config length error");
577 return -1;
578 }
579
580 buf = (u8*)kzalloc(file_len, GFP_KERNEL);
581 pre_buf = (u8*)kzalloc(file_len, GFP_KERNEL);
582 file_config = (u8*)kzalloc(chip_cfg_len + GTP_ADDR_LENGTH, GFP_KERNEL);
583 update_msg.cfg_file->f_op->llseek(update_msg.cfg_file, 0, SEEK_SET);
584
585 GTP_DEBUG("[update_cfg]Read config from file.");
586 ret = update_msg.cfg_file->f_op->read(update_msg.cfg_file, (char*)pre_buf, file_len, &update_msg.cfg_file->f_pos);
587 if(ret<0)
588 {
589 GTP_ERROR("[update_cfg]Read config file failed.");
590 goto update_cfg_file_failed;
591 }
592
593 GTP_DEBUG("[update_cfg]Delete illgal charactor.");
594 for(i=0,count=0; i<file_len; i++)
595 {
596 if (pre_buf[i] == ' ' || pre_buf[i] == '\r' || pre_buf[i] == '\n')
597 {
598 continue;
599 }
600 buf[count++] = pre_buf[i];
601 }
602
603 GTP_DEBUG("[update_cfg]Ascii to hex.");
604 file_config[0] = GTP_REG_CONFIG_DATA >> 8;
605 file_config[1] = GTP_REG_CONFIG_DATA & 0xff;
606 for(i=0,file_cfg_len=GTP_ADDR_LENGTH; i<count; i+=5)
607 {
608 if((buf[i]=='0') && ((buf[i+1]=='x') || (buf[i+1]=='X')))
609 {
610 u8 high,low;
611 high = ascii2hex(buf[i+2]);
612 low = ascii2hex(buf[i+3]);
613
614 if((high == 0xFF) || (low == 0xFF))
615 {
616 ret = 0;
617 GTP_ERROR("[update_cfg]Illegal config file.");
618 goto update_cfg_file_failed;
619 }
620 file_config[file_cfg_len++] = (high<<4) + low;
621 }
622 else
623 {
624 ret = 0;
625 GTP_ERROR("[update_cfg]Illegal config file.");
626 goto update_cfg_file_failed;
627 }
628 }
629
630
631 GTP_DEBUG("config:");
632 GTP_DEBUG_ARRAY(file_config+2, file_cfg_len);
633
634 i = 0;
635 while(i++ < 5)
636 {
637 ret = gup_i2c_write(client, file_config, file_cfg_len);
638 if(ret > 0)
639 {
640 GTP_INFO("[update_cfg]Send config SUCCESS.");
641 break;
642 }
643 GTP_ERROR("[update_cfg]Send config i2c error.");
644 }
645
646 update_cfg_file_failed:
647 kfree(pre_buf);
648 kfree(buf);
649 kfree(file_config);
650 return ret;
651 }
652 #endif
653
654 #if (GTP_AUTO_UPDATE && (!GTP_HEADER_FW_UPDATE || GTP_AUTO_UPDATE_CFG))
655 static void gup_search_file(s32 search_type)
656 {
657 s32 i = 0;
658 struct file *pfile = NULL;
659
660 got_file_flag = 0x00;
661
662 searching_file = 1;
663 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
664 {
665 if (0 == searching_file)
666 {
667 GTP_INFO("Force exiting file searching");
668 got_file_flag = 0x00;
669 return;
670 }
671
672 if (search_type & AUTO_SEARCH_BIN)
673 {
674 GTP_DEBUG("Search for %s, %s for fw update.(%d/%d)", UPDATE_FILE_PATH_1, UPDATE_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
675 pfile = filp_open(UPDATE_FILE_PATH_1, O_RDONLY, 0);
676 if (IS_ERR(pfile))
677 {
678 pfile = filp_open(UPDATE_FILE_PATH_2, O_RDONLY, 0);
679 if (!IS_ERR(pfile))
680 {
681 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_2);
682 got_file_flag |= BIN_FILE_READY;
683 update_msg.file = pfile;
684 }
685 }
686 else
687 {
688 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_1);
689 got_file_flag |= BIN_FILE_READY;
690 update_msg.file = pfile;
691 }
692 if (got_file_flag & BIN_FILE_READY)
693 {
694 #if GTP_AUTO_UPDATE_CFG
695 if (search_type & AUTO_SEARCH_CFG)
696 {
697 i = GUP_SEARCH_FILE_TIMES; // Bin & Cfg File required to be in the same directory
698 }
699 else
700 #endif
701 {
702 searching_file = 0;
703 return;
704 }
705 }
706 }
707
708 #if GTP_AUTO_UPDATE_CFG
709 if ( (search_type & AUTO_SEARCH_CFG) && !(got_file_flag & CFG_FILE_READY) )
710 {
711 GTP_DEBUG("Search for %s, %s for config update.(%d/%d)", CONFIG_FILE_PATH_1, CONFIG_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
712 pfile = filp_open(CONFIG_FILE_PATH_1, O_RDONLY, 0);
713 if (IS_ERR(pfile))
714 {
715 pfile = filp_open(CONFIG_FILE_PATH_2, O_RDONLY, 0);
716 if (!IS_ERR(pfile))
717 {
718 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_2);
719 got_file_flag |= CFG_FILE_READY;
720 update_msg.cfg_file = pfile;
721 }
722 }
723 else
724 {
725 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_1);
726 got_file_flag |= CFG_FILE_READY;
727 update_msg.cfg_file = pfile;
728 }
729 if (got_file_flag & CFG_FILE_READY)
730 {
731 searching_file = 0;
732 return;
733 }
734 }
735 #endif
736 msleep(3000);
737 }
738 searching_file = 0;
739 }
740 #endif
741
742 static u8 gup_check_update_file(struct i2c_client *client, st_fw_head *fw_head, u8 *path)
743 {
744 s32 ret = 0;
745 s32 i = 0;
746 s32 fw_checksum = 0;
747 u8 buf[FW_HEAD_LENGTH];
748
749 got_file_flag = 0x00;
750 if (path)
751 {
752 GTP_DEBUG("Update File path:%s, %zu", path, strlen(path));
753 update_msg.file = filp_open(path, O_RDONLY, 0);
754
755 if (IS_ERR(update_msg.file))
756 {
757 GTP_ERROR("Open update file(%s) error!", path);
758 return FAIL;
759 }
760 got_file_flag = BIN_FILE_READY;
761 }
762 else
763 {
764 #if GTP_AUTO_UPDATE
765 #if GTP_HEADER_FW_UPDATE
766 GTP_INFO("Update by default firmware array");
767 update_msg.fw_total_len = sizeof(gtp_default_FW) - FW_HEAD_LENGTH;
768 if (sizeof(gtp_default_FW) < (FW_HEAD_LENGTH + FW_SECTION_LENGTH*4+FW_DSP_ISP_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH))
769 {
770 GTP_INFO("[check_update_file]default firmware array is INVALID!");
771 return FAIL;
772 }
773 GTP_DEBUG("Firmware actual size: %d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
774 memcpy(fw_head, &gtp_default_FW[0], FW_HEAD_LENGTH);
775
776 //check firmware legality
777 fw_checksum = 0;
778 for (i = 0; i < update_msg.fw_total_len; i += 2)
779 {
780 fw_checksum += (gtp_default_FW[FW_HEAD_LENGTH + i] << 8) + gtp_default_FW[FW_HEAD_LENGTH + i + 1];
781 }
782 if(fw_checksum&0xFFFF)
783 {
784 GTP_ERROR("Illegal firmware with checksum(0x%04X)", fw_checksum & 0xFFFF);
785 return FAIL;
786 }
787 got_file_flag = HEADER_FW_READY;
788 return SUCCESS;
789
790 #else
791 #if GTP_AUTO_UPDATE_CFG
792 gup_search_file(AUTO_SEARCH_BIN | AUTO_SEARCH_CFG);
793 if (got_file_flag & CFG_FILE_READY)
794 {
795 ret = gup_update_config(client);
796 if(ret <= 0)
797 {
798 GTP_ERROR("Update config failed!");
799 }
800 _CLOSE_FILE(update_msg.cfg_file);
801 msleep(500); //waiting config to be stored in FLASH.
802 }
803 #else
804 gup_search_file(AUTO_SEARCH_BIN);
805 #endif
806
807 if (!(got_file_flag & BIN_FILE_READY))
808 {
809 GTP_ERROR("No bin file for fw Update");
810 return FAIL;
811 }
812 #endif
813 #else
814 {
815 GTP_ERROR("NULL file for fw update!");
816 return FAIL;
817 }
818 #endif
819 }
820
821 update_msg.old_fs = get_fs();
822 set_fs(KERNEL_DS);
823
824 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
825 update_msg.fw_total_len = update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_END);
826
827 update_msg.fw_total_len -= FW_HEAD_LENGTH;
828
829 GTP_DEBUG("Bin firmware actual size: %d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
830
831 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
832 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, FW_HEAD_LENGTH, &update_msg.file->f_pos);
833
834 if (ret < 0)
835 {
836 GTP_ERROR("Read firmware head in update file error.");
837 goto load_failed;
838 }
839
840 memcpy(fw_head, buf, FW_HEAD_LENGTH);
841
842 //check firmware legality
843 fw_checksum = 0;
844 for(i=0; i < update_msg.fw_total_len; i+=2)
845 {
846 u16 temp;
847 ret = update_msg.file->f_op->read(update_msg.file, (char*)buf, 2, &update_msg.file->f_pos);
848 if (ret < 0)
849 {
850 GTP_ERROR("Read firmware file error.");
851 goto load_failed;
852 }
853 //GTP_DEBUG("BUF[0]:%x", buf[0]);
854 temp = (buf[0]<<8) + buf[1];
855 fw_checksum += temp;
856 }
857
858 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
859 if(fw_checksum&0xFFFF)
860 {
861 GTP_ERROR("Illegal firmware file.");
862 goto load_failed;
863 }
864
865 return SUCCESS;
866
867 load_failed:
868 set_fs(update_msg.old_fs);
869 _CLOSE_FILE(update_msg.file);
870 return FAIL;
871 }
872
873 static u8 gup_burn_proc(struct i2c_client *client, u8 *burn_buf, u16 start_addr, u16 total_length)
874 {
875 s32 ret = 0;
876 u16 burn_addr = start_addr;
877 u16 frame_length = 0;
878 u16 burn_length = 0;
879 u8 wr_buf[PACK_SIZE + GTP_ADDR_LENGTH];
880 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
881 u8 retry = 0;
882
883 GTP_DEBUG("Begin burn %dk data to addr 0x%x", (total_length / 1024), start_addr);
884
885 while (burn_length < total_length)
886 {
887 GTP_DEBUG("B/T:%04d/%04d", burn_length, total_length);
888 frame_length = ((total_length - burn_length) > PACK_SIZE) ? PACK_SIZE : (total_length - burn_length);
889 wr_buf[0] = (u8)(burn_addr >> 8);
890 rd_buf[0] = wr_buf[0];
891 wr_buf[1] = (u8)burn_addr;
892 rd_buf[1] = wr_buf[1];
893 memcpy(&wr_buf[GTP_ADDR_LENGTH], &burn_buf[burn_length], frame_length);
894
895 for (retry = 0; retry < MAX_FRAME_CHECK_TIME; retry++)
896 {
897 ret = gup_i2c_write(client, wr_buf, GTP_ADDR_LENGTH + frame_length);
898
899 if (ret <= 0)
900 {
901 GTP_ERROR("Write frame data i2c error.");
902 continue;
903 }
904
905 ret = gup_i2c_read(client, rd_buf, GTP_ADDR_LENGTH + frame_length);
906
907 if (ret <= 0)
908 {
909 GTP_ERROR("Read back frame data i2c error.");
910 continue;
911 }
912
913 if (memcmp(&wr_buf[GTP_ADDR_LENGTH], &rd_buf[GTP_ADDR_LENGTH], frame_length))
914 {
915 GTP_ERROR("Check frame data fail,not equal.");
916 GTP_DEBUG("write array:");
917 GTP_DEBUG_ARRAY(&wr_buf[GTP_ADDR_LENGTH], frame_length);
918 GTP_DEBUG("read array:");
919 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
920 continue;
921 }
922 else
923 {
924 //GTP_DEBUG("Check frame data success.");
925 break;
926 }
927 }
928
929 if (retry > MAX_FRAME_CHECK_TIME)
930 {
931 GTP_ERROR("Burn frame data time out,exit.");
932 return FAIL;
933 }
934
935 burn_length += frame_length;
936 burn_addr += frame_length;
937 }
938
939 return SUCCESS;
940 }
941
942 static u8 gup_load_section_file(u8 *buf, u32 offset, u16 length, u8 set_or_end)
943 {
944 #if (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE)
945 if (HEADER_FW_READY == got_file_flag)
946 {
947 if(SEEK_SET == set_or_end)
948 {
949 memcpy(buf, &gtp_default_FW[FW_HEAD_LENGTH + offset], length);
950 }
951 else //seek end
952 {
953 memcpy(buf, &gtp_default_FW[update_msg.fw_total_len + FW_HEAD_LENGTH - offset], length);
954 }
955 return SUCCESS;
956 }
957 #endif
958 {
959 s32 ret = 0;
960
961 if ( (update_msg.file == NULL) || IS_ERR(update_msg.file))
962 {
963 GTP_ERROR("cannot find update file,load section file fail.");
964 return FAIL;
965 }
966
967 if(SEEK_SET == set_or_end)
968 {
969 update_msg.file->f_pos = FW_HEAD_LENGTH + offset;
970 }
971 else //seek end
972 {
973 update_msg.file->f_pos = update_msg.fw_total_len + FW_HEAD_LENGTH - offset;
974 }
975
976 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, length, &update_msg.file->f_pos);
977
978 if (ret < 0)
979 {
980 GTP_ERROR("Read update file fail.");
981 return FAIL;
982 }
983
984 return SUCCESS;
985 }
986 }
987
988 static u8 gup_recall_check(struct i2c_client *client, u8 *chk_src, u16 start_rd_addr, u16 chk_length)
989 {
990 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
991 s32 ret = 0;
992 u16 recall_addr = start_rd_addr;
993 u16 recall_length = 0;
994 u16 frame_length = 0;
995
996 while (recall_length < chk_length)
997 {
998 frame_length = ((chk_length - recall_length) > PACK_SIZE) ? PACK_SIZE : (chk_length - recall_length);
999 ret = gup_get_ic_msg(client, recall_addr, rd_buf, frame_length);
1000
1001 if (ret <= 0)
1002 {
1003 GTP_ERROR("recall i2c error,exit");
1004 return FAIL;
1005 }
1006
1007 if (memcmp(&rd_buf[GTP_ADDR_LENGTH], &chk_src[recall_length], frame_length))
1008 {
1009 GTP_ERROR("Recall frame data fail,not equal.");
1010 GTP_DEBUG("chk_src array:");
1011 GTP_DEBUG_ARRAY(&chk_src[recall_length], frame_length);
1012 GTP_DEBUG("recall array:");
1013 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
1014 return FAIL;
1015 }
1016
1017 recall_length += frame_length;
1018 recall_addr += frame_length;
1019 }
1020
1021 GTP_DEBUG("Recall check %dk firmware success.", (chk_length / 1024));
1022
1023 return SUCCESS;
1024 }
1025
1026 static u8 gup_burn_fw_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u8 bank_cmd)
1027 {
1028 s32 ret = 0;
1029 u8 rd_buf[5];
1030
1031 //step1:hold ss51 & dsp
1032 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1033
1034 if (ret <= 0)
1035 {
1036 GTP_ERROR("[burn_fw_section]hold ss51 & dsp fail.");
1037 return FAIL;
1038 }
1039
1040 //step2:set scramble
1041 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1042
1043 if (ret <= 0)
1044 {
1045 GTP_ERROR("[burn_fw_section]set scramble fail.");
1046 return FAIL;
1047 }
1048
1049 //step3:select bank
1050 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
1051
1052 if (ret <= 0)
1053 {
1054 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
1055 return FAIL;
1056 }
1057
1058 //step4:enable accessing code
1059 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1060
1061 if (ret <= 0)
1062 {
1063 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
1064 return FAIL;
1065 }
1066
1067 //step5:burn 8k fw section
1068 ret = gup_burn_proc(client, fw_section, start_addr, FW_SECTION_LENGTH);
1069
1070 if (FAIL == ret)
1071 {
1072 GTP_ERROR("[burn_fw_section]burn fw_section fail.");
1073 return FAIL;
1074 }
1075
1076 //step6:hold ss51 & release dsp
1077 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
1078
1079 if (ret <= 0)
1080 {
1081 GTP_ERROR("[burn_fw_section]hold ss51 & release dsp fail.");
1082 return FAIL;
1083 }
1084
1085 //must delay
1086 msleep(1);
1087
1088 //step7:send burn cmd to move data to flash from sram
1089 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd & 0x0f);
1090
1091 if (ret <= 0)
1092 {
1093 GTP_ERROR("[burn_fw_section]send burn cmd fail.");
1094 return FAIL;
1095 }
1096
1097 GTP_DEBUG("[burn_fw_section]Wait for the burn is complete......");
1098
1099 do
1100 {
1101 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1102
1103 if (ret <= 0)
1104 {
1105 GTP_ERROR("[burn_fw_section]Get burn state fail");
1106 return FAIL;
1107 }
1108
1109 msleep(10);
1110 //GTP_DEBUG("[burn_fw_section]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1111 }
1112 while (rd_buf[GTP_ADDR_LENGTH]);
1113
1114 //step8:select bank
1115 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
1116
1117 if (ret <= 0)
1118 {
1119 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
1120 return FAIL;
1121 }
1122
1123 //step9:enable accessing code
1124 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1125
1126 if (ret <= 0)
1127 {
1128 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
1129 return FAIL;
1130 }
1131
1132 //step10:recall 8k fw section
1133 ret = gup_recall_check(client, fw_section, start_addr, FW_SECTION_LENGTH);
1134
1135 if (FAIL == ret)
1136 {
1137 GTP_ERROR("[burn_fw_section]recall check %dk firmware fail.", FW_SECTION_LENGTH/1024);
1138 return FAIL;
1139 }
1140
1141 //step11:disable accessing code
1142 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x00);
1143
1144 if (ret <= 0)
1145 {
1146 GTP_ERROR("[burn_fw_section]disable accessing code fail.");
1147 return FAIL;
1148 }
1149
1150 return SUCCESS;
1151 }
1152
1153 static u8 gup_burn_dsp_isp(struct i2c_client *client)
1154 {
1155 s32 ret = 0;
1156 u8 *fw_dsp_isp = NULL;
1157 u8 retry = 0;
1158 //u32 offset;
1159
1160 GTP_INFO("[burn_dsp_isp]Begin burn dsp isp---->>");
1161
1162 //step1:alloc memory
1163 GTP_DEBUG("[burn_dsp_isp]step1:alloc memory");
1164
1165 while (retry++ < 5)
1166 {
1167 fw_dsp_isp = (u8 *)kzalloc(FW_DSP_ISP_LENGTH, GFP_KERNEL);
1168
1169 if (fw_dsp_isp == NULL)
1170 {
1171 continue;
1172 }
1173 else
1174 {
1175 GTP_INFO("[burn_dsp_isp]Alloc %dk byte memory success.", (FW_DSP_ISP_LENGTH / 1024));
1176 break;
1177 }
1178 }
1179
1180 if (retry >= 5)
1181 {
1182 GTP_ERROR("[burn_dsp_isp]Alloc memory fail,exit.");
1183 return FAIL;
1184 }
1185
1186 //step2:load dsp isp file data
1187 GTP_DEBUG("[burn_dsp_isp]step2:load dsp isp file data");
1188 ret = gup_load_section_file(fw_dsp_isp, FW_DSP_ISP_LENGTH, FW_DSP_ISP_LENGTH, SEEK_END);
1189
1190 if (FAIL == ret)
1191 {
1192 GTP_ERROR("[burn_dsp_isp]load firmware dsp_isp fail.");
1193 goto exit_burn_dsp_isp;
1194 }
1195
1196 //step3:disable wdt,clear cache enable
1197 GTP_DEBUG("[burn_dsp_isp]step3:disable wdt,clear cache enable");
1198 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
1199
1200 if (ret <= 0)
1201 {
1202 GTP_ERROR("[burn_dsp_isp]disable wdt fail.");
1203 ret = FAIL;
1204 goto exit_burn_dsp_isp;
1205 }
1206
1207 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
1208
1209 if (ret <= 0)
1210 {
1211 GTP_ERROR("[burn_dsp_isp]clear cache enable fail.");
1212 ret = FAIL;
1213 goto exit_burn_dsp_isp;
1214 }
1215
1216 //step4:hold ss51 & dsp
1217 GTP_DEBUG("[burn_dsp_isp]step4:hold ss51 & dsp");
1218 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1219
1220 if (ret <= 0)
1221 {
1222 GTP_ERROR("[burn_dsp_isp]hold ss51 & dsp fail.");
1223 ret = FAIL;
1224 goto exit_burn_dsp_isp;
1225 }
1226
1227 //step5:set boot from sram
1228 GTP_DEBUG("[burn_dsp_isp]step5:set boot from sram");
1229 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
1230
1231 if (ret <= 0)
1232 {
1233 GTP_ERROR("[burn_dsp_isp]set boot from sram fail.");
1234 ret = FAIL;
1235 goto exit_burn_dsp_isp;
1236 }
1237
1238 //step6:software reboot
1239 GTP_DEBUG("[burn_dsp_isp]step6:software reboot");
1240 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
1241
1242 if (ret <= 0)
1243 {
1244 GTP_ERROR("[burn_dsp_isp]software reboot fail.");
1245 ret = FAIL;
1246 goto exit_burn_dsp_isp;
1247 }
1248
1249 //step7:select bank2
1250 GTP_DEBUG("[burn_dsp_isp]step7:select bank2");
1251 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
1252
1253 if (ret <= 0)
1254 {
1255 GTP_ERROR("[burn_dsp_isp]select bank2 fail.");
1256 ret = FAIL;
1257 goto exit_burn_dsp_isp;
1258 }
1259
1260 //step8:enable accessing code
1261 GTP_DEBUG("[burn_dsp_isp]step8:enable accessing code");
1262 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1263
1264 if (ret <= 0)
1265 {
1266 GTP_ERROR("[burn_dsp_isp]enable accessing code fail.");
1267 ret = FAIL;
1268 goto exit_burn_dsp_isp;
1269 }
1270
1271 //step9:burn 4k dsp_isp
1272 GTP_DEBUG("[burn_dsp_isp]step9:burn 4k dsp_isp");
1273 ret = gup_burn_proc(client, fw_dsp_isp, 0xC000, FW_DSP_ISP_LENGTH);
1274
1275 if (FAIL == ret)
1276 {
1277 GTP_ERROR("[burn_dsp_isp]burn dsp_isp fail.");
1278 goto exit_burn_dsp_isp;
1279 }
1280
1281 //step10:set scramble
1282 GTP_DEBUG("[burn_dsp_isp]step10:set scramble");
1283 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1284
1285 if (ret <= 0)
1286 {
1287 GTP_ERROR("[burn_dsp_isp]set scramble fail.");
1288 ret = FAIL;
1289 goto exit_burn_dsp_isp;
1290 }
1291
1292 update_msg.fw_burned_len += FW_DSP_ISP_LENGTH;
1293 GTP_DEBUG("[burn_dsp_isp]Burned length:%d", update_msg.fw_burned_len);
1294 ret = SUCCESS;
1295
1296 exit_burn_dsp_isp:
1297 kfree(fw_dsp_isp);
1298 return ret;
1299 }
1300
1301 static u8 gup_burn_fw_ss51(struct i2c_client *client)
1302 {
1303 u8 *fw_ss51 = NULL;
1304 u8 retry = 0;
1305 s32 ret = 0;
1306
1307 GTP_INFO("[burn_fw_ss51]Begin burn ss51 firmware---->>");
1308
1309 //step1:alloc memory
1310 GTP_DEBUG("[burn_fw_ss51]step1:alloc memory");
1311
1312 while (retry++ < 5)
1313 {
1314 fw_ss51 = (u8 *)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
1315
1316 if (fw_ss51 == NULL)
1317 {
1318 continue;
1319 }
1320 else
1321 {
1322 GTP_INFO("[burn_fw_ss51]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1323 break;
1324 }
1325 }
1326
1327 if (retry >= 5)
1328 {
1329 GTP_ERROR("[burn_fw_ss51]Alloc memory fail,exit.");
1330 return FAIL;
1331 }
1332
1333 //step2:load ss51 firmware section 1 file data
1334 //GTP_DEBUG("[burn_fw_ss51]step2:load ss51 firmware section 1 file data");
1335 //ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
1336 //
1337 // if (FAIL == ret)
1338 // {
1339 // GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 1 fail.");
1340 // goto exit_burn_fw_ss51;
1341 // }
1342 GTP_INFO("[burn_fw_ss51]Reset first 8K of ss51 to 0xFF.");
1343 GTP_DEBUG("[burn_fw_ss51]step2: reset bank0 0xC000~0xD000");
1344 memset(fw_ss51, 0xFF, FW_SECTION_LENGTH);
1345
1346 //step3:clear control flag
1347 GTP_DEBUG("[burn_fw_ss51]step3:clear control flag");
1348 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
1349
1350 if (ret <= 0)
1351 {
1352 GTP_ERROR("[burn_fw_ss51]clear control flag fail.");
1353 ret = FAIL;
1354 goto exit_burn_fw_ss51;
1355 }
1356
1357 //step4:burn ss51 firmware section 1
1358 GTP_DEBUG("[burn_fw_ss51]step4:burn ss51 firmware section 1");
1359 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
1360
1361 if (FAIL == ret)
1362 {
1363 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 1 fail.");
1364 goto exit_burn_fw_ss51;
1365 }
1366
1367 //step5:load ss51 firmware section 2 file data
1368 GTP_DEBUG("[burn_fw_ss51]step5:load ss51 firmware section 2 file data");
1369 ret = gup_load_section_file(fw_ss51, FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1370
1371 if (FAIL == ret)
1372 {
1373 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 2 fail.");
1374 goto exit_burn_fw_ss51;
1375 }
1376
1377 //step6:burn ss51 firmware section 2
1378 GTP_DEBUG("[burn_fw_ss51]step6:burn ss51 firmware section 2");
1379 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x02);
1380
1381 if (FAIL == ret)
1382 {
1383 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 2 fail.");
1384 goto exit_burn_fw_ss51;
1385 }
1386
1387 //step7:load ss51 firmware section 3 file data
1388 GTP_DEBUG("[burn_fw_ss51]step7:load ss51 firmware section 3 file data");
1389 ret = gup_load_section_file(fw_ss51, 2 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1390
1391 if (FAIL == ret)
1392 {
1393 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 3 fail.");
1394 goto exit_burn_fw_ss51;
1395 }
1396
1397 //step8:burn ss51 firmware section 3
1398 GTP_DEBUG("[burn_fw_ss51]step8:burn ss51 firmware section 3");
1399 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x13);
1400
1401 if (FAIL == ret)
1402 {
1403 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 3 fail.");
1404 goto exit_burn_fw_ss51;
1405 }
1406
1407 //step9:load ss51 firmware section 4 file data
1408 GTP_DEBUG("[burn_fw_ss51]step9:load ss51 firmware section 4 file data");
1409 ret = gup_load_section_file(fw_ss51, 3 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1410
1411 if (FAIL == ret)
1412 {
1413 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 4 fail.");
1414 goto exit_burn_fw_ss51;
1415 }
1416
1417 //step10:burn ss51 firmware section 4
1418 GTP_DEBUG("[burn_fw_ss51]step10:burn ss51 firmware section 4");
1419 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x14);
1420
1421 if (FAIL == ret)
1422 {
1423 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 4 fail.");
1424 goto exit_burn_fw_ss51;
1425 }
1426
1427 update_msg.fw_burned_len += (FW_SECTION_LENGTH*4);
1428 GTP_DEBUG("[burn_fw_ss51]Burned length:%d", update_msg.fw_burned_len);
1429 ret = SUCCESS;
1430
1431 exit_burn_fw_ss51:
1432 kfree(fw_ss51);
1433 return ret;
1434 }
1435
1436 static u8 gup_burn_fw_dsp(struct i2c_client *client)
1437 {
1438 s32 ret = 0;
1439 u8 *fw_dsp = NULL;
1440 u8 retry = 0;
1441 u8 rd_buf[5];
1442
1443 GTP_INFO("[burn_fw_dsp]Begin burn dsp firmware---->>");
1444 //step1:alloc memory
1445 GTP_DEBUG("[burn_fw_dsp]step1:alloc memory");
1446
1447 while (retry++ < 5)
1448 {
1449 fw_dsp = (u8 *)kzalloc(FW_DSP_LENGTH, GFP_KERNEL);
1450
1451 if (fw_dsp == NULL)
1452 {
1453 continue;
1454 }
1455 else
1456 {
1457 GTP_INFO("[burn_fw_dsp]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1458 break;
1459 }
1460 }
1461
1462 if (retry >= 5)
1463 {
1464 GTP_ERROR("[burn_fw_dsp]Alloc memory fail,exit.");
1465 return FAIL;
1466 }
1467
1468 //step2:load firmware dsp
1469 GTP_DEBUG("[burn_fw_dsp]step2:load firmware dsp");
1470 ret = gup_load_section_file(fw_dsp, 4 * FW_SECTION_LENGTH, FW_DSP_LENGTH, SEEK_SET);
1471
1472 if (FAIL == ret)
1473 {
1474 GTP_ERROR("[burn_fw_dsp]load firmware dsp fail.");
1475 goto exit_burn_fw_dsp;
1476 }
1477
1478 //step3:select bank3
1479 GTP_DEBUG("[burn_fw_dsp]step3:select bank3");
1480 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1481
1482 if (ret <= 0)
1483 {
1484 GTP_ERROR("[burn_fw_dsp]select bank3 fail.");
1485 ret = FAIL;
1486 goto exit_burn_fw_dsp;
1487 }
1488
1489 //step4:hold ss51 & dsp
1490 GTP_DEBUG("[burn_fw_dsp]step4:hold ss51 & dsp");
1491 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1492
1493 if (ret <= 0)
1494 {
1495 GTP_ERROR("[burn_fw_dsp]hold ss51 & dsp fail.");
1496 ret = FAIL;
1497 goto exit_burn_fw_dsp;
1498 }
1499
1500 //step5:set scramble
1501 GTP_DEBUG("[burn_fw_dsp]step5:set scramble");
1502 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1503
1504 if (ret <= 0)
1505 {
1506 GTP_ERROR("[burn_fw_dsp]set scramble fail.");
1507 ret = FAIL;
1508 goto exit_burn_fw_dsp;
1509 }
1510
1511 //step6:release ss51 & dsp
1512 GTP_DEBUG("[burn_fw_dsp]step6:release ss51 & dsp");
1513 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121212
1514
1515 if (ret <= 0)
1516 {
1517 GTP_ERROR("[burn_fw_dsp]release ss51 & dsp fail.");
1518 ret = FAIL;
1519 goto exit_burn_fw_dsp;
1520 }
1521
1522 //must delay
1523 msleep(1);
1524
1525 //step7:burn 4k dsp firmware
1526 GTP_DEBUG("[burn_fw_dsp]step7:burn 4k dsp firmware");
1527 ret = gup_burn_proc(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1528
1529 if (FAIL == ret)
1530 {
1531 GTP_ERROR("[burn_fw_dsp]burn fw_section fail.");
1532 goto exit_burn_fw_dsp;
1533 }
1534
1535 //step8:send burn cmd to move data to flash from sram
1536 GTP_DEBUG("[burn_fw_dsp]step8:send burn cmd to move data to flash from sram");
1537 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x05);
1538
1539 if (ret <= 0)
1540 {
1541 GTP_ERROR("[burn_fw_dsp]send burn cmd fail.");
1542 goto exit_burn_fw_dsp;
1543 }
1544
1545 GTP_DEBUG("[burn_fw_dsp]Wait for the burn is complete......");
1546
1547 do
1548 {
1549 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1550
1551 if (ret <= 0)
1552 {
1553 GTP_ERROR("[burn_fw_dsp]Get burn state fail");
1554 goto exit_burn_fw_dsp;
1555 }
1556
1557 msleep(10);
1558 //GTP_DEBUG("[burn_fw_dsp]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1559 }
1560 while (rd_buf[GTP_ADDR_LENGTH]);
1561
1562 //step9:recall check 4k dsp firmware
1563 GTP_DEBUG("[burn_fw_dsp]step9:recall check 4k dsp firmware");
1564 ret = gup_recall_check(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1565
1566 if (FAIL == ret)
1567 {
1568 GTP_ERROR("[burn_fw_dsp]recall check 4k dsp firmware fail.");
1569 goto exit_burn_fw_dsp;
1570 }
1571
1572 update_msg.fw_burned_len += FW_DSP_LENGTH;
1573 GTP_DEBUG("[burn_fw_dsp]Burned length:%d", update_msg.fw_burned_len);
1574 ret = SUCCESS;
1575
1576 exit_burn_fw_dsp:
1577 kfree(fw_dsp);
1578 return ret;
1579 }
1580
1581 static u8 gup_burn_fw_boot(struct i2c_client *client)
1582 {
1583 s32 ret = 0;
1584 u8* fw_boot = NULL;
1585 u8 retry = 0;
1586 u8 rd_buf[5];
1587
1588 GTP_DEBUG("[burn_fw_boot]Begin burn bootloader firmware---->>");
1589
1590 //step1:Alloc memory
1591 GTP_DEBUG("[burn_fw_boot]step1:Alloc memory");
1592
1593 while(retry++ < 5)
1594 {
1595 fw_boot = (u8*)kzalloc(FW_BOOT_LENGTH, GFP_KERNEL);
1596
1597 if(fw_boot == NULL)
1598 {
1599 continue;
1600 }
1601 else
1602 {
1603 GTP_INFO("[burn_fw_boot]Alloc %dk byte memory success.", (FW_BOOT_LENGTH/1024));
1604 break;
1605 }
1606 }
1607
1608 if(retry >= 5)
1609 {
1610 GTP_ERROR("[burn_fw_boot]Alloc memory fail,exit.");
1611 return FAIL;
1612 }
1613
1614 //step2:load firmware bootloader
1615 GTP_DEBUG("[burn_fw_boot]step2:load firmware bootloader");
1616 ret = gup_load_section_file(fw_boot, (4 * FW_SECTION_LENGTH + FW_DSP_LENGTH), FW_BOOT_LENGTH, SEEK_SET);
1617
1618 if(FAIL == ret)
1619 {
1620 GTP_ERROR("[burn_fw_boot]load firmware bootcode fail.");
1621 goto exit_burn_fw_boot;
1622 }
1623
1624 //step3:hold ss51 & dsp
1625 GTP_DEBUG("[burn_fw_boot]step3:hold ss51 & dsp");
1626 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1627 if(ret <= 0)
1628 {
1629 GTP_ERROR("[burn_fw_boot]hold ss51 & dsp fail.");
1630 ret = FAIL;
1631 goto exit_burn_fw_boot;
1632 }
1633
1634 //step4:set scramble
1635 GTP_DEBUG("[burn_fw_boot]step4:set scramble");
1636 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1637 if(ret <= 0)
1638 {
1639 GTP_ERROR("[burn_fw_boot]set scramble fail.");
1640 ret = FAIL;
1641 goto exit_burn_fw_boot;
1642 }
1643
1644 //step5:hold ss51 & release dsp
1645 GTP_DEBUG("[burn_fw_boot]step5:hold ss51 & release dsp");
1646 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121211
1647 if(ret <= 0)
1648 {
1649 GTP_ERROR("[burn_fw_boot]release ss51 & dsp fail.");
1650 ret = FAIL;
1651 goto exit_burn_fw_boot;
1652 }
1653 //must delay
1654 msleep(1);
1655
1656 //step6:select bank3
1657 GTP_DEBUG("[burn_fw_boot]step6:select bank3");
1658 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1659 if(ret <= 0)
1660 {
1661 GTP_ERROR("[burn_fw_boot]select bank3 fail.");
1662 ret = FAIL;
1663 goto exit_burn_fw_boot;
1664 }
1665
1666 //step7:burn 2k bootloader firmware
1667 GTP_DEBUG("[burn_fw_boot]step7:burn 2k bootloader firmware");
1668 ret = gup_burn_proc(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1669 if(FAIL == ret)
1670 {
1671 GTP_ERROR("[burn_fw_boot]burn fw_boot fail.");
1672 goto exit_burn_fw_boot;
1673 }
1674
1675 //step7:send burn cmd to move data to flash from sram
1676 GTP_DEBUG("[burn_fw_boot]step7:send burn cmd to move data to flash from sram");
1677 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x06);
1678 if(ret <= 0)
1679 {
1680 GTP_ERROR("[burn_fw_boot]send burn cmd fail.");
1681 goto exit_burn_fw_boot;
1682 }
1683 GTP_DEBUG("[burn_fw_boot]Wait for the burn is complete......");
1684 do{
1685 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1686 if(ret <= 0)
1687 {
1688 GTP_ERROR("[burn_fw_boot]Get burn state fail");
1689 goto exit_burn_fw_boot;
1690 }
1691 msleep(10);
1692 //GTP_DEBUG("[burn_fw_boot]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1693 }while(rd_buf[GTP_ADDR_LENGTH]);
1694
1695 //step8:recall check 2k bootloader firmware
1696 GTP_DEBUG("[burn_fw_boot]step8:recall check 2k bootloader firmware");
1697 ret = gup_recall_check(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1698 if(FAIL == ret)
1699 {
1700 GTP_ERROR("[burn_fw_boot]recall check 2k bootcode firmware fail.");
1701 goto exit_burn_fw_boot;
1702 }
1703
1704 update_msg.fw_burned_len += FW_BOOT_LENGTH;
1705 GTP_DEBUG("[burn_fw_boot]Burned length:%d", update_msg.fw_burned_len);
1706 ret = SUCCESS;
1707
1708 exit_burn_fw_boot:
1709 kfree(fw_boot);
1710 return ret;
1711 }
1712
1713 static u8 gup_burn_fw_boot_isp(struct i2c_client *client)
1714 {
1715 s32 ret = 0;
1716 u8* fw_boot_isp = NULL;
1717 u8 retry = 0;
1718 u8 rd_buf[5];
1719
1720 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
1721 {
1722 GTP_INFO("No need to upgrade the boot_isp code!");
1723 return SUCCESS;
1724 }
1725 GTP_DEBUG("[burn_fw_boot_isp]Begin burn bootloader firmware---->>");
1726
1727 //step1:Alloc memory
1728 GTP_DEBUG("[burn_fw_boot_isp]step1:Alloc memory");
1729 while(retry++ < 5)
1730 {
1731 fw_boot_isp = (u8*)kzalloc(FW_BOOT_ISP_LENGTH, GFP_KERNEL);
1732 if(fw_boot_isp == NULL)
1733 {
1734 continue;
1735 }
1736 else
1737 {
1738 GTP_INFO("[burn_fw_boot_isp]Alloc %dk byte memory success.", (FW_BOOT_ISP_LENGTH/1024));
1739 break;
1740 }
1741 }
1742 if(retry >= 5)
1743 {
1744 GTP_ERROR("[burn_fw_boot_isp]Alloc memory fail,exit.");
1745 return FAIL;
1746 }
1747
1748 //step2:load firmware bootloader
1749 GTP_DEBUG("[burn_fw_boot_isp]step2:load firmware bootloader isp");
1750 //ret = gup_load_section_file(fw_boot_isp, (4*FW_SECTION_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH+FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
1751 ret = gup_load_section_file(fw_boot_isp, (update_msg.fw_burned_len - FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
1752 if(FAIL == ret)
1753 {
1754 GTP_ERROR("[burn_fw_boot_isp]load firmware boot_isp fail.");
1755 goto exit_burn_fw_boot_isp;
1756 }
1757
1758 //step3:hold ss51 & dsp
1759 GTP_DEBUG("[burn_fw_boot_isp]step3:hold ss51 & dsp");
1760 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1761 if(ret <= 0)
1762 {
1763 GTP_ERROR("[burn_fw_boot_isp]hold ss51 & dsp fail.");
1764 ret = FAIL;
1765 goto exit_burn_fw_boot_isp;
1766 }
1767
1768 //step4:set scramble
1769 GTP_DEBUG("[burn_fw_boot_isp]step4:set scramble");
1770 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1771 if(ret <= 0)
1772 {
1773 GTP_ERROR("[burn_fw_boot_isp]set scramble fail.");
1774 ret = FAIL;
1775 goto exit_burn_fw_boot_isp;
1776 }
1777
1778
1779 //step5:hold ss51 & release dsp
1780 GTP_DEBUG("[burn_fw_boot_isp]step5:hold ss51 & release dsp");
1781 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121211
1782 if(ret <= 0)
1783 {
1784 GTP_ERROR("[burn_fw_boot_isp]release ss51 & dsp fail.");
1785 ret = FAIL;
1786 goto exit_burn_fw_boot_isp;
1787 }
1788 //must delay
1789 msleep(1);
1790
1791 //step6:select bank3
1792 GTP_DEBUG("[burn_fw_boot_isp]step6:select bank3");
1793 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1794 if(ret <= 0)
1795 {
1796 GTP_ERROR("[burn_fw_boot_isp]select bank3 fail.");
1797 ret = FAIL;
1798 goto exit_burn_fw_boot_isp;
1799 }
1800
1801 //step7:burn 2k bootload_isp firmware
1802 GTP_DEBUG("[burn_fw_boot_isp]step7:burn 2k bootloader firmware");
1803 ret = gup_burn_proc(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
1804 if(FAIL == ret)
1805 {
1806 GTP_ERROR("[burn_fw_boot_isp]burn fw_section fail.");
1807 goto exit_burn_fw_boot_isp;
1808 }
1809
1810 //step7:send burn cmd to move data to flash from sram
1811 GTP_DEBUG("[burn_fw_boot_isp]step7:send burn cmd to move data to flash from sram");
1812 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x07);
1813 if(ret <= 0)
1814 {
1815 GTP_ERROR("[burn_fw_boot_isp]send burn cmd fail.");
1816 goto exit_burn_fw_boot_isp;
1817 }
1818 GTP_DEBUG("[burn_fw_boot_isp]Wait for the burn is complete......");
1819 do{
1820 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1821 if(ret <= 0)
1822 {
1823 GTP_ERROR("[burn_fw_boot_isp]Get burn state fail");
1824 goto exit_burn_fw_boot_isp;
1825 }
1826 msleep(10);
1827 //GTP_DEBUG("[burn_fw_boot_isp]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1828 }while(rd_buf[GTP_ADDR_LENGTH]);
1829
1830 //step8:recall check 2k bootload_isp firmware
1831 GTP_DEBUG("[burn_fw_boot_isp]step8:recall check 2k bootloader firmware");
1832 ret = gup_recall_check(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
1833 if(FAIL == ret)
1834 {
1835 GTP_ERROR("[burn_fw_boot_isp]recall check 2k bootcode_isp firmware fail.");
1836 goto exit_burn_fw_boot_isp;
1837 }
1838
1839 update_msg.fw_burned_len += FW_BOOT_ISP_LENGTH;
1840 GTP_DEBUG("[burn_fw_boot_isp]Burned length:%d", update_msg.fw_burned_len);
1841 ret = SUCCESS;
1842
1843 exit_burn_fw_boot_isp:
1844 kfree(fw_boot_isp);
1845 return ret;
1846 }
1847
1848 static u8 gup_burn_fw_link(struct i2c_client *client)
1849 {
1850 s32 ret = 0;
1851 u8* fw_link = NULL;
1852 u8 retry = 0;
1853 u32 offset;
1854
1855 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
1856 {
1857 GTP_INFO("No need to upgrade the link code!");
1858 return SUCCESS;
1859 }
1860 GTP_DEBUG("[burn_fw_link]Begin burn link firmware---->>");
1861
1862 //step1:Alloc memory
1863 GTP_DEBUG("[burn_fw_link]step1:Alloc memory");
1864 while(retry++ < 5)
1865 {
1866 fw_link = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
1867 if(fw_link == NULL)
1868 {
1869 continue;
1870 }
1871 else
1872 {
1873 GTP_INFO("[burn_fw_link]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
1874 break;
1875 }
1876 }
1877 if(retry >= 5)
1878 {
1879 GTP_ERROR("[burn_fw_link]Alloc memory fail,exit.");
1880 return FAIL;
1881 }
1882
1883 //step2:load firmware link section 1
1884 GTP_DEBUG("[burn_fw_link]step2:load firmware link section 1");
1885 offset = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
1886 ret = gup_load_section_file(fw_link, offset, FW_SECTION_LENGTH, SEEK_SET);
1887 if(FAIL == ret)
1888 {
1889 GTP_ERROR("[burn_fw_link]load firmware link section 1 fail.");
1890 goto exit_burn_fw_link;
1891 }
1892
1893
1894 //step3:burn link firmware section 1
1895 GTP_DEBUG("[burn_fw_link]step3:burn link firmware section 1");
1896 ret = gup_burn_fw_app_section(client, fw_link, 0x9000, FW_SECTION_LENGTH, 0x38);
1897
1898 if (FAIL == ret)
1899 {
1900 GTP_ERROR("[burn_fw_link]burn link firmware section 1 fail.");
1901 goto exit_burn_fw_link;
1902 }
1903
1904 //step4:load link firmware section 2 file data
1905 GTP_DEBUG("[burn_fw_link]step4:load link firmware section 2 file data");
1906 offset += FW_SECTION_LENGTH;
1907 ret = gup_load_section_file(fw_link, offset, FW_LINK_LENGTH - FW_SECTION_LENGTH, SEEK_SET);
1908
1909 if (FAIL == ret)
1910 {
1911 GTP_ERROR("[burn_fw_link]load link firmware section 2 fail.");
1912 goto exit_burn_fw_link;
1913 }
1914
1915 //step5:burn link firmware section 2
1916 GTP_DEBUG("[burn_fw_link]step4:burn link firmware section 2");
1917 ret = gup_burn_fw_app_section(client, fw_link, 0x9000, FW_LINK_LENGTH - FW_SECTION_LENGTH, 0x39);
1918
1919 if (FAIL == ret)
1920 {
1921 GTP_ERROR("[burn_fw_link]burn link firmware section 2 fail.");
1922 goto exit_burn_fw_link;
1923 }
1924
1925 update_msg.fw_burned_len += FW_LINK_LENGTH;
1926 GTP_DEBUG("[burn_fw_link]Burned length:%d", update_msg.fw_burned_len);
1927 ret = SUCCESS;
1928
1929 exit_burn_fw_link:
1930 kfree(fw_link);
1931 return ret;
1932 }
1933
1934 static u8 gup_burn_fw_app_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd )
1935 {
1936 s32 ret = 0;
1937 u8 rd_buf[5];
1938
1939 //step1:hold ss51 & dsp
1940 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1941 if(ret <= 0)
1942 {
1943 GTP_ERROR("[burn_fw_app_section]hold ss51 & dsp fail.");
1944 return FAIL;
1945 }
1946
1947 //step2:set scramble
1948 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1949 if(ret <= 0)
1950 {
1951 GTP_ERROR("[burn_fw_app_section]set scramble fail.");
1952 return FAIL;
1953 }
1954
1955 //step3:hold ss51 & release dsp
1956 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
1957 if(ret <= 0)
1958 {
1959 GTP_ERROR("[burn_fw_app_section]hold ss51 & release dsp fail.");
1960 return FAIL;
1961 }
1962 //must delay
1963 msleep(1);
1964
1965 //step4:select bank
1966 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4)&0x0F);
1967 if(ret <= 0)
1968 {
1969 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4)&0x0F);
1970 return FAIL;
1971 }
1972
1973 //step5:burn fw section
1974 ret = gup_burn_proc(client, fw_section, start_addr, len);
1975 if(FAIL == ret)
1976 {
1977 GTP_ERROR("[burn_fw_app_section]burn fw_section fail.");
1978 return FAIL;
1979 }
1980
1981 //step6:send burn cmd to move data to flash from sram
1982 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd&0x0F);
1983 if(ret <= 0)
1984 {
1985 GTP_ERROR("[burn_fw_app_section]send burn cmd fail.");
1986 return FAIL;
1987 }
1988 GTP_DEBUG("[burn_fw_section]Wait for the burn is complete......");
1989 do{
1990 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1991 if(ret <= 0)
1992 {
1993 GTP_ERROR("[burn_fw_app_section]Get burn state fail");
1994 return FAIL;
1995 }
1996 msleep(10);
1997 //GTP_DEBUG("[burn_fw_app_section]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1998 }while(rd_buf[GTP_ADDR_LENGTH]);
1999
2000 //step7:recall fw section
2001 ret = gup_recall_check(client, fw_section, start_addr, len);
2002 if(FAIL == ret)
2003 {
2004 GTP_ERROR("[burn_fw_app_section]recall check %dk firmware fail.", len/1024);
2005 return FAIL;
2006 }
2007
2008 return SUCCESS;
2009 }
2010
2011 static u8 gup_burn_fw_app_code(struct i2c_client *client)
2012 {
2013 u8* fw_app_code = NULL;
2014 u8 retry = 0;
2015 s32 ret = 0;
2016 //u16 start_index = 4*FW_SECTION_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH + FW_DSP_ISP_LENGTH + FW_BOOT_ISP_LENGTH; // 32 + 4 + 2 + 4 = 42K
2017 u16 start_index;
2018
2019 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
2020 {
2021 GTP_INFO("No need to upgrade the app code!");
2022 return SUCCESS;
2023 }
2024 start_index = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
2025 GTP_DEBUG("[burn_fw_app_code]Begin burn app_code firmware---->>");
2026
2027 //step1:alloc memory
2028 GTP_DEBUG("[burn_fw_app_code]step1:alloc memory");
2029 while(retry++ < 5)
2030 {
2031 fw_app_code = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
2032 if(fw_app_code == NULL)
2033 {
2034 continue;
2035 }
2036 else
2037 {
2038 GTP_INFO("[burn_fw_app_code]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
2039 break;
2040 }
2041 }
2042 if(retry >= 5)
2043 {
2044 GTP_ERROR("[burn_fw_app_code]Alloc memory fail,exit.");
2045 return FAIL;
2046 }
2047
2048 //step2:load app_code firmware section 1 file data
2049 GTP_DEBUG("[burn_fw_app_code]step2:load app_code firmware section 1 file data");
2050 ret = gup_load_section_file(fw_app_code, start_index, FW_SECTION_LENGTH, SEEK_SET);
2051 if(FAIL == ret)
2052 {
2053 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 1 fail.");
2054 goto exit_burn_fw_app_code;
2055 }
2056
2057 //step3:burn app_code firmware section 1
2058 GTP_DEBUG("[burn_fw_app_code]step3:burn app_code firmware section 1");
2059 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3A);
2060 if(FAIL == ret)
2061 {
2062 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 1 fail.");
2063 goto exit_burn_fw_app_code;
2064 }
2065
2066 //step5:load app_code firmware section 2 file data
2067 GTP_DEBUG("[burn_fw_app_code]step5:load app_code firmware section 2 file data");
2068 ret = gup_load_section_file(fw_app_code, start_index+FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2069 if(FAIL == ret)
2070 {
2071 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 2 fail.");
2072 goto exit_burn_fw_app_code;
2073 }
2074
2075 //step6:burn app_code firmware section 2
2076 GTP_DEBUG("[burn_fw_app_code]step6:burn app_code firmware section 2");
2077 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3B);
2078 if(FAIL == ret)
2079 {
2080 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 2 fail.");
2081 goto exit_burn_fw_app_code;
2082 }
2083
2084 //step7:load app_code firmware section 3 file data
2085 GTP_DEBUG("[burn_fw_app_code]step7:load app_code firmware section 3 file data");
2086 ret = gup_load_section_file(fw_app_code, start_index+2*FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2087 if(FAIL == ret)
2088 {
2089 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 3 fail.");
2090 goto exit_burn_fw_app_code;
2091 }
2092
2093 //step8:burn app_code firmware section 3
2094 GTP_DEBUG("[burn_fw_app_code]step8:burn app_code firmware section 3");
2095 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3C);
2096 if(FAIL == ret)
2097 {
2098 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 3 fail.");
2099 goto exit_burn_fw_app_code;
2100 }
2101
2102 //step9:load app_code firmware section 4 file data
2103 GTP_DEBUG("[burn_fw_app_code]step9:load app_code firmware section 4 file data");
2104 ret = gup_load_section_file(fw_app_code, start_index + 3*FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2105 if(FAIL == ret)
2106 {
2107 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 4 fail.");
2108 goto exit_burn_fw_app_code;
2109 }
2110
2111 //step10:burn app_code firmware section 4
2112 GTP_DEBUG("[burn_fw_app_code]step10:burn app_code firmware section 4");
2113 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3D);
2114 if(FAIL == ret)
2115 {
2116 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 4 fail.");
2117 goto exit_burn_fw_app_code;
2118 }
2119
2120 update_msg.fw_burned_len += FW_APP_CODE_LENGTH;
2121 GTP_DEBUG("[burn_fw_gwake]Burned length:%d", update_msg.fw_burned_len);
2122 ret = SUCCESS;
2123
2124 exit_burn_fw_app_code:
2125 kfree(fw_app_code);
2126 return ret;
2127 }
2128
2129 static u8 gup_burn_fw_finish(struct i2c_client *client)
2130 {
2131 u8* fw_ss51 = NULL;
2132 u8 retry = 0;
2133 s32 ret = 0;
2134
2135 GTP_INFO("[burn_fw_finish]burn first 8K of ss51 and finish update.");
2136 //step1:alloc memory
2137 GTP_DEBUG("[burn_fw_finish]step1:alloc memory");
2138 while(retry++ < 5)
2139 {
2140 fw_ss51 = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
2141 if(fw_ss51 == NULL)
2142 {
2143 continue;
2144 }
2145 else
2146 {
2147 GTP_DEBUG("[burn_fw_finish]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
2148 break;
2149 }
2150 }
2151 if(retry >= 5)
2152 {
2153 GTP_ERROR("[burn_fw_finish]Alloc memory fail,exit.");
2154 return FAIL;
2155 }
2156
2157 GTP_DEBUG("[burn_fw_finish]step2: burn ss51 first 8K.");
2158 ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
2159 if(FAIL == ret)
2160 {
2161 GTP_ERROR("[burn_fw_finish]load ss51 firmware section 1 fail.");
2162 goto exit_burn_fw_finish;
2163 }
2164
2165 GTP_DEBUG("[burn_fw_finish]step3:clear control flag");
2166 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
2167 if(ret <= 0)
2168 {
2169 GTP_ERROR("[burn_fw_finish]clear control flag fail.");
2170 goto exit_burn_fw_finish;
2171 }
2172
2173 GTP_DEBUG("[burn_fw_finish]step4:burn ss51 firmware section 1");
2174 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
2175 if(FAIL == ret)
2176 {
2177 GTP_ERROR("[burn_fw_finish]burn ss51 firmware section 1 fail.");
2178 goto exit_burn_fw_finish;
2179 }
2180
2181 //step11:enable download DSP code
2182 GTP_DEBUG("[burn_fw_finish]step5:enable download DSP code ");
2183 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x99);
2184 if(ret <= 0)
2185 {
2186 GTP_ERROR("[burn_fw_finish]enable download DSP code fail.");
2187 goto exit_burn_fw_finish;
2188 }
2189
2190 //step12:release ss51 & hold dsp
2191 GTP_DEBUG("[burn_fw_finish]step6:release ss51 & hold dsp");
2192 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x08);
2193 if(ret <= 0)
2194 {
2195 GTP_ERROR("[burn_fw_finish]release ss51 & hold dsp fail.");
2196 goto exit_burn_fw_finish;
2197 }
2198
2199 if (fw_ss51)
2200 {
2201 kfree(fw_ss51);
2202 }
2203 return SUCCESS;
2204
2205 exit_burn_fw_finish:
2206 if (fw_ss51)
2207 {
2208 kfree(fw_ss51);
2209 }
2210 return FAIL;
2211 }
2212
2213 s32 gup_update_proc(void *dir)
2214 {
2215 s32 ret = 0;
2216 u8 retry = 0;
2217 s32 update_ret = FAIL;
2218 st_fw_head fw_head;
2219 #if GT917S_UPDATE_RULE
2220 char temp_data[6] = {0};
2221 #endif
2222
2223 GTP_INFO("[update_proc]Begin update ......");
2224
2225 #if GTP_AUTO_UPDATE
2226 if (1 == searching_file)
2227 {
2228 u8 timeout = 0;
2229 searching_file = 0; // exit .bin update file searching
2230 GTP_INFO("Exiting searching file for auto update.");
2231 while ((show_len != 200) && (show_len != 100) && (timeout++ < 150)) // wait for auto update quitted completely
2232 {
2233 msleep(100);
2234 }
2235 }
2236 #endif
2237
2238 show_len = 1;
2239 total_len = 100;
2240
2241 #if GTP_COMPATIBLE_MODE
2242 if (CHIP_TYPE_GT9F == gtp_chip_type)
2243 {
2244 return gup_fw_download_proc(dir, GTP_FL_FW_BURN);
2245 }
2246 #endif
2247 update_msg.file = NULL;
2248 ret = gup_check_update_file(i2c_client_point, &fw_head, (u8 *)dir); //20121212
2249
2250 if (FAIL == ret)
2251 {
2252 GTP_ERROR("[update_proc]check update file fail.");
2253 goto file_fail;
2254 }
2255
2256 //gtp_reset_guitar(i2c_client_point, 20);
2257 ret = gup_get_ic_fw_msg(i2c_client_point);
2258
2259 if (FAIL == ret)
2260 {
2261 GTP_ERROR("[update_proc]get ic message fail.");
2262 goto file_fail;
2263 }
2264
2265 ret = gup_enter_update_judge(&fw_head); //20121212
2266
2267 #if GT917S_UPDATE_RULE
2268 i2c_read_bytes(i2c_client_point, 0x8140, temp_data, 6);
2269 GTP_INFO("917S firmware detect add function temp_data = (%c, %c, %c, %c)!",temp_data[0], temp_data[1],temp_data[2],temp_data[3]);
2270 if(temp_data[0]==57 && temp_data[1]==49 && temp_data[2]==55 && temp_data[3]==83)
2271 {
2272 GTP_INFO("GT917S firmware detect Force Update!");
2273 ret = SUCCESS;
2274 }
2275 #endif
2276
2277 #ifdef GTP_FORCE_UPDATE_FW_K92
2278 ret = SUCCESS;
2279 #endif
2280
2281 #if GTP_FORCE_UPDATE_FW
2282 ret = SUCCESS; //for test
2283 #endif
2284
2285 if (FAIL == ret)
2286 {
2287 GTP_ERROR("[update_proc]Check *.bin file fail.");
2288 goto file_fail;
2289 }
2290
2291 #ifdef CONFIG_OF_TOUCH
2292 disable_irq(touch_irq);
2293 #else
2294 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
2295 #endif
2296
2297 #if GTP_ESD_PROTECT
2298 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
2299 #endif
2300 ret = gup_enter_update_mode(i2c_client_point);
2301
2302 if (FAIL == ret)
2303 {
2304 GTP_ERROR("[update_proc]enter update mode fail.");
2305 goto update_fail;
2306 }
2307
2308 while (retry++ < 5)
2309 {
2310 show_len = 10;
2311 total_len = 100;
2312 update_msg.fw_burned_len = 0;
2313 GTP_DEBUG("[update_proc]Burned length:%d", update_msg.fw_burned_len);
2314 ret = gup_burn_dsp_isp(i2c_client_point);
2315 if(FAIL == ret)
2316 {
2317 GTP_ERROR("[update_proc]burn dsp isp fail.");
2318 continue;
2319 }
2320
2321 show_len = 30;
2322 ret = gup_burn_fw_ss51(i2c_client_point);
2323 if(FAIL == ret)
2324 {
2325 GTP_ERROR("[update_proc]burn ss51 firmware fail.");
2326 continue;
2327 }
2328
2329 show_len = 40;
2330 ret = gup_burn_fw_dsp(i2c_client_point);
2331 if(FAIL == ret)
2332 {
2333 GTP_ERROR("[update_proc]burn dsp firmware fail.");
2334 continue;
2335 }
2336
2337 show_len = 50;
2338 ret = gup_burn_fw_boot(i2c_client_point);
2339 if(FAIL == ret)
2340 {
2341 GTP_ERROR("[update_proc]burn bootloader firmware fail.");
2342 continue;
2343 }
2344 show_len = 60;
2345
2346 ret = gup_burn_fw_boot_isp(i2c_client_point);
2347 if (FAIL == ret)
2348 {
2349 GTP_ERROR("[update_proc]burn boot_isp firmware fail.");
2350 continue;
2351 }
2352
2353 show_len = 70;
2354 ret = gup_burn_fw_link(i2c_client_point);
2355 if (FAIL == ret)
2356 {
2357 GTP_ERROR("[update_proc]burn link firmware fail.");
2358 continue;
2359 }
2360
2361 show_len = 80;
2362 ret = gup_burn_fw_app_code(i2c_client_point);
2363 if (FAIL == ret)
2364 {
2365 GTP_ERROR("[update_proc]burn app_code firmware fail.");
2366 continue;
2367 }
2368 show_len = 90;
2369 ret = gup_burn_fw_finish(i2c_client_point);
2370 if (FAIL == ret)
2371 {
2372 GTP_ERROR("[update_proc]burn finish fail.");
2373 continue;
2374 }
2375 show_len = 95;
2376 GTP_INFO("[update_proc]UPDATE SUCCESS.");
2377 break;
2378 }
2379
2380 if (retry >= 5)
2381 {
2382 GTP_ERROR("[update_proc]retry timeout,UPDATE FAIL.");
2383 update_ret = FAIL;
2384 }
2385 else
2386 {
2387 update_ret = SUCCESS;
2388 }
2389
2390 update_fail:
2391 GTP_DEBUG("[update_proc]leave update mode.");
2392 gup_leave_update_mode();
2393
2394 if (SUCCESS == update_ret)
2395 {
2396 GTP_DEBUG("[update_proc]send config.");
2397 ret = gtp_send_cfg(i2c_client_point);
2398 if (ret < 0)
2399 {
2400 GTP_ERROR("[update_proc]send config fail.");
2401 }
2402 }
2403
2404 #if GTP_ESD_PROTECT
2405 gtp_esd_switch(i2c_client_point, SWITCH_ON);
2406 #endif
2407
2408 file_fail:
2409
2410 #ifdef CONFIG_OF_TOUCH
2411 enable_irq(touch_irq);
2412 #else
2413 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
2414 #endif
2415
2416
2417 if (update_msg.file && !IS_ERR(update_msg.file))
2418 {
2419 if (update_msg.old_fs)
2420 {
2421 set_fs(update_msg.old_fs);
2422 }
2423 filp_close(update_msg.file, NULL);
2424 }
2425 #if (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE && GTP_AUTO_UPDATE_CFG)
2426 if (NULL == dir)
2427 {
2428 gup_search_file(AUTO_SEARCH_CFG);
2429 if (got_file_flag & CFG_FILE_READY)
2430 {
2431 ret = gup_update_config(i2c_client_point);
2432 if (FAIL == ret)
2433 {
2434 GTP_ERROR("Update config failed!");
2435 }
2436 }
2437 }
2438 #endif
2439
2440 total_len = 100;
2441 if (SUCCESS == update_ret)
2442 {
2443 show_len = 100;
2444 return SUCCESS;
2445 }
2446 else
2447 {
2448 show_len = 200;
2449 return FAIL;
2450 }
2451 }
2452
2453 u8 gup_init_update_proc(struct i2c_client *client)
2454 {
2455 struct task_struct *thread = NULL;
2456
2457 GTP_INFO("Ready to run auto update thread");
2458
2459 #if GTP_COMPATIBLE_MODE
2460 if (CHIP_TYPE_GT9F == gtp_chip_type)
2461 {
2462 thread = kthread_run(gup_update_proc, "update", "fl_auto_update");
2463 }
2464 else
2465 #endif
2466 {
2467 thread = kthread_run(gup_update_proc, (void *)NULL, "guitar_update");
2468 }
2469 if (IS_ERR(thread))
2470 {
2471 GTP_ERROR("Failed to create update thread.\n");
2472 return -1;
2473 }
2474
2475 return 0;
2476 }
2477
2478
2479 //******************* For GT9XXF Start ********************//
2480
2481 #define FL_UPDATE_PATH "/data/_fl_update_.bin"
2482 #define FL_UPDATE_PATH_SD "/sdcard/_fl_update_.bin"
2483
2484 #define GUP_FW_CHK_SIZE 256
2485 #define MAX_CHECK_TIMES 128 // max: 2 * (16 * 1024) / 256 = 128
2486
2487 //for clk cal
2488 #define PULSE_LENGTH (200)
2489 #define INIT_CLK_DAC (50)
2490 #define MAX_CLK_DAC (120)
2491 #define CLK_AVG_TIME (1)
2492 #define MILLION 1000000
2493
2494 #define _wRW_MISCTL__RG_DMY 0x4282
2495 #define _bRW_MISCTL__RG_OSC_CALIB 0x4268
2496 #define _fRW_MISCTL__GIO0 0x41e9
2497 #define _fRW_MISCTL__GIO1 0x41ed
2498 #define _fRW_MISCTL__GIO2 0x41f1
2499 #define _fRW_MISCTL__GIO3 0x41f5
2500 #define _fRW_MISCTL__GIO4 0x41f9
2501 #define _fRW_MISCTL__GIO5 0x41fd
2502 #define _fRW_MISCTL__GIO6 0x4201
2503 #define _fRW_MISCTL__GIO7 0x4205
2504 #define _fRW_MISCTL__GIO8 0x4209
2505 #define _fRW_MISCTL__GIO9 0x420d
2506 #define _fRW_MISCTL__MEA 0x41a0
2507 #define _bRW_MISCTL__MEA_MODE 0x41a1
2508 #define _wRW_MISCTL__MEA_MAX_NUM 0x41a4
2509 #define _dRO_MISCTL__MEA_VAL 0x41b0
2510 #define _bRW_MISCTL__MEA_SRCSEL 0x41a3
2511 #define _bRO_MISCTL__MEA_RDY 0x41a8
2512 #define _rRW_MISCTL__ANA_RXADC_B0_ 0x4250
2513 #define _bRW_MISCTL__RG_LDO_A18_PWD 0x426f
2514 #define _bRW_MISCTL__RG_BG_PWD 0x426a
2515 #define _bRW_MISCTL__RG_CLKGEN_PWD 0x4269
2516 #define _fRW_MISCTL__RG_RXADC_PWD 0x426a
2517 #define _bRW_MISCTL__OSC_CK_SEL 0x4030
2518 #define _rRW_MISCTL_RG_DMY83 0x4283
2519 #define _rRW_MISCTL__GIO1CTL_B2_ 0x41ee
2520 #define _rRW_MISCTL__GIO1CTL_B1_ 0x41ed
2521
2522 #if GTP_COMPATIBLE_MODE
2523
2524 u8 gup_check_fs_mounted(char *path_name)
2525 {
2526 struct path root_path;
2527 struct path path;
2528 int err;
2529 err = kern_path("/", LOOKUP_FOLLOW, &root_path);
2530
2531 if (err){
2532 path_put(&root_path);
2533 return FAIL;
2534 }
2535
2536 err = kern_path(path_name, LOOKUP_FOLLOW, &path);
2537 if (err){
2538 path_put(&root_path);
2539 path_put(&path);
2540 return FAIL;
2541 }
2542
2543 if (path.mnt->mnt_sb == root_path.mnt->mnt_sb)
2544 {
2545 //-- not mounted
2546 path_put(&root_path);
2547 path_put(&path);
2548 return FAIL;
2549 }
2550 else
2551 {
2552 path_put(&root_path);
2553 path_put(&path);
2554 return SUCCESS;
2555 }
2556 }
2557
2558 s32 gup_hold_ss51_dsp(struct i2c_client *client)
2559 {
2560 s32 ret = -1;
2561 s32 retry = 0;
2562 u8 rd_buf[3];
2563
2564 while(retry++ < 200)
2565 {
2566 // step4:Hold ss51 & dsp
2567 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
2568 if(ret <= 0)
2569 {
2570 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
2571 continue;
2572 }
2573
2574 // step5:Confirm hold
2575 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
2576 if (ret <= 0)
2577 {
2578 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
2579 continue;
2580 }
2581 if (0x0C == rd_buf[GTP_ADDR_LENGTH])
2582 {
2583 GTP_DEBUG("[enter_update_mode]Hold ss51 & dsp confirm SUCCESS");
2584 break;
2585 }
2586 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
2587 }
2588 if(retry >= 200)
2589 {
2590 GTP_ERROR("Enter update Hold ss51 failed.");
2591 return FAIL;
2592 }
2593 //DSP_CK and DSP_ALU_CK PowerOn
2594 ret = gup_set_ic_msg(client, 0x4010, 0x00);
2595 if (ret <= 0)
2596 {
2597 GTP_ERROR("[enter_update_mode]DSP_CK and DSP_ALU_CK PowerOn fail.");
2598 return FAIL;
2599 }
2600
2601 //disable wdt
2602 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
2603
2604 if (ret <= 0)
2605 {
2606 GTP_ERROR("[enter_update_mode]disable wdt fail.");
2607 return FAIL;
2608 }
2609
2610 //clear cache enable
2611 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
2612
2613 if (ret <= 0)
2614 {
2615 GTP_ERROR("[enter_update_mode]clear cache enable fail.");
2616 return FAIL;
2617 }
2618
2619 //set boot from sram
2620 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
2621
2622 if (ret <= 0)
2623 {
2624 GTP_ERROR("[enter_update_mode]set boot from sram fail.");
2625 return FAIL;
2626 }
2627
2628 //software reboot
2629 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
2630 if (ret <= 0)
2631 {
2632 GTP_ERROR("[enter_update_mode]software reboot fail.");
2633 return FAIL;
2634 }
2635
2636 return SUCCESS;
2637 }
2638
2639 s32 gup_enter_update_mode_fl(struct i2c_client *client)
2640 {
2641 s32 ret = -1;
2642 //s32 retry = 0;
2643 //u8 rd_buf[3];
2644
2645 //step1:RST output low last at least 2ms
2646 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
2647 msleep(2);
2648
2649 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
2650 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
2651 msleep(2);
2652
2653 //step3:RST output high reset guitar
2654 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
2655
2656 msleep(5);
2657
2658 //select addr & hold ss51_dsp
2659 ret = gup_hold_ss51_dsp(client);
2660 if (ret <= 0)
2661 {
2662 GTP_ERROR("[enter_update_mode]hold ss51 & dsp failed.");
2663 return FAIL;
2664 }
2665
2666 //clear control flag
2667 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
2668
2669 if (ret <= 0)
2670 {
2671 GTP_ERROR("[enter_update_mode]clear control flag fail.");
2672 return FAIL;
2673 }
2674
2675 //set scramble
2676 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
2677
2678 if (ret <= 0)
2679 {
2680 GTP_ERROR("[enter_update_mode]set scramble fail.");
2681 return FAIL;
2682 }
2683
2684 //enable accessing code
2685 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
2686
2687 if (ret <= 0)
2688 {
2689 GTP_ERROR("[enter_update_mode]enable accessing code fail.");
2690 return FAIL;
2691 }
2692
2693 return SUCCESS;
2694 }
2695
2696
2697 static s32 gup_prepare_fl_fw(char *path, st_fw_head *fw_head)
2698 {
2699 s32 i = 0;
2700 s32 ret = 0;
2701 s32 timeout = 0;
2702
2703 if (!memcmp(path, "update", 6))
2704 {
2705 GTP_INFO("Search for Flashless firmware file to update");
2706 searching_file = 1;
2707 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
2708 {
2709 if (0 == searching_file)
2710 {
2711 GTP_INFO("Force terminate searching file auto update.");
2712 return FAIL;
2713 }
2714 update_msg.file = filp_open(FL_UPDATE_PATH, O_RDONLY, 0);
2715 if (IS_ERR(update_msg.file))
2716 {
2717 update_msg.file = filp_open(FL_UPDATE_PATH_SD, O_RDONLY, 0);
2718 if (IS_ERR(update_msg.file))
2719 {
2720 msleep(2000);
2721 continue;
2722 }
2723 else
2724 {
2725 path = FL_UPDATE_PATH_SD;
2726 break;
2727 }
2728 }
2729 else
2730 {
2731 path = FL_UPDATE_PATH;
2732 break;
2733 }
2734 }
2735 searching_file = 0;
2736 if (i >= 50)
2737 {
2738 GTP_ERROR("Search timeout, update aborted");
2739 return FAIL;
2740 }
2741 else
2742 {
2743 _CLOSE_FILE(update_msg.file);
2744 }
2745 while (rqst_processing && (timeout++ < 15))
2746 {
2747 GTP_INFO("wait for request process completed!");
2748 msleep(1000);
2749 }
2750 }
2751
2752 GTP_INFO("Firmware update file path: %s", path);
2753 update_msg.file = filp_open(path, O_RDONLY, 0);
2754
2755 if (IS_ERR(update_msg.file))
2756 {
2757 GTP_ERROR("Open update file(%s) error!", path);
2758 return FAIL;
2759 }
2760
2761 update_msg.old_fs = get_fs();
2762 set_fs(KERNEL_DS);
2763 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2764 update_msg.fw_total_len = update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_END);
2765 if (sizeof(gtp_default_FW_fl) != update_msg.fw_total_len)
2766 {
2767 //GTP_ERROR("Inconsistent firmware size. File size: %du, default fw size: %lu", update_msg.fw_total_len, sizeof(gtp_default_FW_fl));
2768 set_fs(update_msg.old_fs);
2769 _CLOSE_FILE(update_msg.file);
2770 return FAIL;
2771 }
2772
2773 GTP_DEBUG("Firmware size: %d", update_msg.fw_total_len);
2774 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2775 update_msg.file->f_op->read(update_msg.file, (char*)fw_head, FW_HEAD_LENGTH, &update_msg.file->f_pos);
2776 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2777 //copy fw file to gtp_default_FW_fl array
2778 ret = update_msg.file->f_op->read(update_msg.file,
2779 (char*)gtp_default_FW_fl,
2780 update_msg.fw_total_len,
2781 &update_msg.file->f_pos);
2782 if (ret < 0)
2783 {
2784 GTP_ERROR("Failed to read firmware data from %s, err-code: %d", path, ret);
2785 ret = FAIL;
2786 }
2787 else
2788 {
2789 ret = SUCCESS;
2790 }
2791 set_fs(update_msg.old_fs);
2792 _CLOSE_FILE(update_msg.file);
2793 return ret;
2794 }
2795
2796 static u8 gup_check_update_file_fl(struct i2c_client *client, st_fw_head *fw_head, char *path)
2797 {
2798 s32 i = 0;
2799 s32 fw_checksum = 0;
2800 s32 ret = 0;
2801
2802 if (NULL != path)
2803 {
2804 ret = gup_prepare_fl_fw(path, fw_head);
2805 if (ret == FAIL)
2806 {
2807 return FAIL;
2808 }
2809 }
2810 else
2811 {
2812 memcpy(fw_head, gtp_default_FW_fl, FW_HEAD_LENGTH);
2813 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
2814 GTP_INFO("FILE PID:%s", fw_head->pid);
2815 fw_head->vid = ((fw_head->vid & 0xFF00) >> 8) + ((fw_head->vid & 0x00FF) << 8);
2816 GTP_INFO("FILE VID:%04x", fw_head->vid);
2817 }
2818
2819 //check firmware legality
2820 fw_checksum = 0;
2821 for (i = FW_HEAD_LENGTH; i < (FW_HEAD_LENGTH + update_msg.fw_total_len); i += 2)
2822 {
2823 fw_checksum = (gtp_default_FW_fl[i]<<8) + gtp_default_FW_fl[i+1];
2824 }
2825
2826 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
2827 if(fw_checksum&0xFFFF)
2828 {
2829 GTP_ERROR("Illegal firmware file.");
2830 return FAIL;
2831 }
2832
2833 return SUCCESS;
2834 }
2835
2836
2837 static u8 gup_download_fw_ss51(struct i2c_client *client, u8 dwn_mode)
2838 {
2839 s32 ret = 0;
2840
2841 if(GTP_FL_FW_BURN == dwn_mode)
2842 {
2843 GTP_INFO("[download_fw_ss51]Begin download ss51 firmware---->>");
2844 }
2845 else
2846 {
2847 GTP_INFO("[download_fw_ss51]Begin check ss51 firmware----->>");
2848 }
2849 //step1:download FW section 1
2850 GTP_DEBUG("[download_fw_ss51]step1:download FW section 1");
2851 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x00);
2852
2853 if (ret <= 0)
2854 {
2855 GTP_ERROR("[download_fw_ss51]select bank0 fail.");
2856 ret = FAIL;
2857 goto exit_download_fw_ss51;
2858 }
2859
2860
2861 ret = i2c_write_bytes(client, 0xC000,
2862 &gtp_default_FW_fl[FW_HEAD_LENGTH], FW_DOWNLOAD_LENGTH); // write the first bank
2863
2864 if (ret == -1)
2865 {
2866 GTP_ERROR("[download_fw_ss51]download FW section 1 fail.");
2867 ret = FAIL;
2868 goto exit_download_fw_ss51;
2869 }
2870
2871
2872 if (GTP_FL_FW_BURN == dwn_mode)
2873 {
2874 ret = gup_check_and_repair(i2c_client_point,
2875 0xC000,
2876 &gtp_default_FW_fl[FW_HEAD_LENGTH],
2877 FW_DOWNLOAD_LENGTH);
2878 if(FAIL == ret)
2879 {
2880 GTP_ERROR("[download_fw_ss51]Checked FW section 1 fail.");
2881 goto exit_download_fw_ss51;
2882 }
2883 }
2884
2885 //step2:download FW section 2
2886 GTP_DEBUG("[download_fw_ss51]step2:download FW section 1");
2887 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x01);
2888
2889 if (ret <= 0)
2890 {
2891 GTP_ERROR("[download_fw_ss51]select bank1 fail.");
2892 ret = FAIL;
2893 goto exit_download_fw_ss51;
2894 }
2895
2896 ret = i2c_write_bytes(client, 0xC000, &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],FW_DOWNLOAD_LENGTH); // write the second bank
2897
2898 if (ret == -1)
2899 {
2900 GTP_ERROR("[download_fw_ss51]download FW section 2 fail.");
2901 ret = FAIL;
2902 goto exit_download_fw_ss51;
2903 }
2904
2905 if (GTP_FL_FW_BURN == dwn_mode)
2906 {
2907 ret = gup_check_and_repair(i2c_client_point,
2908 0xC000,
2909 &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],
2910 FW_DOWNLOAD_LENGTH);
2911
2912 if(FAIL == ret)
2913 {
2914 GTP_ERROR("[download_fw_ss51]Checked FW section 2 fail.");
2915 goto exit_download_fw_ss51;
2916 }
2917 }
2918 ret = SUCCESS;
2919
2920 exit_download_fw_ss51:
2921
2922 return ret;
2923 }
2924 #if (!GTP_SUPPORT_I2C_DMA)
2925 static s32 i2c_auto_read(struct i2c_client *client,u8 *rxbuf, int len)
2926 {
2927 u8 retry;
2928 u16 left = len;
2929 u16 offset = 0;
2930
2931 struct i2c_msg msg =
2932 {
2933 //.addr = ((client->addr &I2C_MASK_FLAG) | (I2C_ENEXT_FLAG)),
2934 .addr = ((client->addr &I2C_MASK_FLAG) | (I2C_PUSHPULL_FLAG)),
2935 .flags = I2C_M_RD,
2936 .timing = I2C_MASTER_CLOCK
2937 };
2938
2939 if(NULL == rxbuf)
2940 {
2941 return -1;
2942 }
2943
2944 while (left > 0)
2945 {
2946 msg.buf = &rxbuf[offset];
2947
2948 if (left > MAX_TRANSACTION_LENGTH)
2949 {
2950 msg.len = MAX_TRANSACTION_LENGTH;
2951 left -= MAX_TRANSACTION_LENGTH;
2952 offset += MAX_TRANSACTION_LENGTH;
2953 }
2954 else
2955 {
2956 msg.len = left;
2957 left = 0;
2958 }
2959
2960 retry = 0;
2961
2962 while (i2c_transfer(client->adapter, &msg, 1) != 1)
2963 {
2964 retry++;
2965
2966 if (retry == 20)
2967 {
2968 GTP_ERROR("I2C read 0x%X length=%d failed\n", offset, len);
2969 return -1;
2970 }
2971 }
2972 }
2973
2974 return 0;
2975 }
2976 #endif
2977 static u8 gup_check_and_repair(struct i2c_client *client, s32 chk_start_addr, u8 *target_fw, u32 chk_total_length)
2978 {
2979 s32 ret = 0;
2980 u32 chked_len = 0;
2981 u8 chked_times = 0;
2982 u32 chk_addr = 0;
2983 u8 chk_buf[GUP_FW_CHK_SIZE];
2984 u32 rd_size = 0;
2985 u8 flag_err = 0;
2986 s32 i = 0;
2987
2988 chk_addr = chk_start_addr;
2989 while((chked_times < MAX_CHECK_TIMES) && (chked_len < chk_total_length))
2990 {
2991 rd_size = chk_total_length - chked_len;
2992 if(rd_size >= GUP_FW_CHK_SIZE)
2993 {
2994 rd_size = GUP_FW_CHK_SIZE;
2995 }
2996 #if GTP_SUPPORT_I2C_DMA
2997 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
2998 #else
2999 if (!i)
3000 {
3001 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
3002 }
3003 else
3004 {
3005 ret = i2c_auto_read(client, chk_buf, rd_size);
3006 }
3007 #endif
3008
3009 if(-1 == ret)
3010 {
3011 GTP_ERROR("Read chk ram fw i2c error");
3012 chked_times++;
3013 continue;
3014 }
3015
3016 for(i=0; i<rd_size; i++)
3017 {
3018 if(chk_buf[i] != target_fw[i])
3019 {
3020 GTP_ERROR("chk_buf[%d] = 0x%x, target_fw[%d] = 0x%x.", i,chk_buf[i],i,target_fw[i]);
3021 GTP_ERROR("Ram pos[0x%04x] checked failed,rewrite.", chk_addr + i);
3022 i2c_write_bytes(client, chk_addr+i, &target_fw[i], rd_size-i);
3023 flag_err = 1;
3024 i = 0;
3025 break;
3026 }
3027 }
3028
3029 if(!flag_err)
3030 {
3031 GTP_DEBUG("Ram pos[0x%04X] check pass!", chk_addr);
3032 chked_len += rd_size;
3033 target_fw += rd_size;
3034 chk_addr += rd_size;
3035 }
3036 else
3037 {
3038 flag_err = 0;
3039 chked_times++;
3040 }
3041 }
3042
3043 if(chked_times >= MAX_CHECK_TIMES)
3044 {
3045 GTP_ERROR("Ram data check failed.");
3046 return FAIL;
3047 }
3048 return SUCCESS;
3049 }
3050
3051 static u8 gup_download_fw_dsp(struct i2c_client *client, u8 dwn_mode)
3052 {
3053 s32 ret = 0;
3054
3055 if(GTP_FL_FW_BURN == dwn_mode)
3056 {
3057 GTP_INFO("[download_fw_dsp]Begin download dsp fw---->>");
3058 }
3059 else
3060 {
3061 GTP_INFO("[download_fw_dsp]Begin check dsp fw---->>");
3062 }
3063
3064 //step1:select bank2
3065 GTP_DEBUG("[download_fw_dsp]step1:select bank2");
3066 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
3067
3068 if (ret <= 0)
3069 {
3070 GTP_ERROR("[download_fw_dsp]select bank2 fail.");
3071 ret = FAIL;
3072 goto exit_download_fw_dsp;
3073 }
3074
3075 ret = i2c_write_bytes(client,
3076 0xC000,
3077 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
3078 FW_DSP_LENGTH); // write the second bank
3079 if (ret == -1)
3080 {
3081 GTP_ERROR("[download_fw_dsp]download FW dsp fail.");
3082 ret = FAIL;
3083 goto exit_download_fw_dsp;
3084 }
3085
3086 if (GTP_FL_FW_BURN == dwn_mode)
3087 {
3088 ret = gup_check_and_repair(client,
3089 0xC000,
3090 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
3091 FW_DSP_LENGTH);
3092
3093 if(FAIL == ret)
3094 {
3095 GTP_ERROR("[download_fw_dsp]Checked FW dsp fail.");
3096 goto exit_download_fw_dsp;
3097 }
3098
3099 }
3100 ret = SUCCESS;
3101
3102 exit_download_fw_dsp:
3103
3104 return ret;
3105 }
3106
3107 s32 gup_fw_download_proc(void *dir, u8 dwn_mode)
3108 {
3109 s32 ret = 0;
3110 u8 retry = 0;
3111 st_fw_head fw_head;
3112
3113 if(GTP_FL_FW_BURN == dwn_mode)
3114 {
3115 GTP_INFO("[fw_download_proc]Begin fw download ......");
3116 }
3117 else
3118 {
3119 GTP_INFO("[fw_download_proc]Begin fw check ......");
3120 }
3121 show_len = 0;
3122 total_len = 100;
3123
3124 ret = gup_check_update_file_fl(i2c_client_point, &fw_head, (char *)dir);
3125
3126 show_len = 10;
3127
3128 if (FAIL == ret)
3129 {
3130 GTP_ERROR("[fw_download_proc]check update file fail.");
3131 goto file_fail;
3132 }
3133
3134 #ifdef CONFIG_OF_TOUCH
3135 disable_irq(touch_irq);
3136 #else
3137 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
3138 #endif
3139
3140 if (NULL != dir)
3141 {
3142 #if GTP_ESD_PROTECT
3143 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
3144 #endif
3145 }
3146
3147 ret = gup_enter_update_mode_fl(i2c_client_point);
3148 show_len = 20;
3149
3150 if (FAIL == ret)
3151 {
3152 GTP_ERROR("[fw_download_proc]enter update mode fail.");
3153 goto download_fail;
3154 }
3155
3156 while (retry++ < 5)
3157 {
3158 ret = gup_download_fw_ss51(i2c_client_point, dwn_mode);
3159 show_len = 60;
3160 if (FAIL == ret)
3161 {
3162 GTP_ERROR("[fw_download_proc]burn ss51 firmware fail.");
3163 continue;
3164 }
3165
3166 ret = gup_download_fw_dsp(i2c_client_point, dwn_mode);
3167 show_len = 80;
3168 if (FAIL == ret)
3169 {
3170 GTP_ERROR("[fw_download_proc]burn dsp firmware fail.");
3171 continue;
3172 }
3173
3174 GTP_INFO("[fw_download_proc]UPDATE SUCCESS.");
3175 break;
3176 }
3177
3178 if (retry >= 5)
3179 {
3180 GTP_ERROR("[fw_download_proc]retry timeout,UPDATE FAIL.");
3181 goto download_fail;
3182 }
3183
3184 if (NULL != dir)
3185 {
3186 gtp_fw_startup(i2c_client_point);
3187 #if GTP_ESD_PROTECT
3188 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3189 #endif
3190 }
3191 show_len = 100;
3192
3193 #ifdef CONFIG_OF_TOUCH
3194 enable_irq(touch_irq);
3195 #else
3196 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3197 #endif
3198
3199 return SUCCESS;
3200
3201 download_fail:
3202 if (NULL != dir)
3203 {
3204 gtp_fw_startup(i2c_client_point);
3205 #if GTP_ESD_PROTECT
3206 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3207 #endif
3208 }
3209
3210 file_fail:
3211 show_len = 200;
3212
3213 #ifdef CONFIG_OF_TOUCH
3214 enable_irq(touch_irq);
3215 #else
3216 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3217 #endif
3218
3219 return FAIL;
3220 }
3221
3222
3223 static void gup_bit_write(s32 addr, s32 bit, s32 val)
3224 {
3225 u8 buf;
3226 i2c_read_bytes(i2c_client_point, addr, &buf, 1);
3227
3228 buf = (buf & (~((u8)1 << bit))) | ((u8)val << bit);
3229
3230 i2c_write_bytes(i2c_client_point, addr, &buf, 1);
3231 }
3232
3233 static void gup_clk_count_init(s32 bCh, s32 bCNT)
3234 {
3235 u8 buf;
3236
3237 //_fRW_MISCTL__MEA_EN = 0; //Frequency measure enable
3238 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
3239 //_fRW_MISCTL__MEA_CLR = 1; //Frequency measure clear
3240 gup_bit_write(_fRW_MISCTL__MEA, 1, 1);
3241 //_bRW_MISCTL__MEA_MODE = 0; //Pulse mode
3242 buf = 0;
3243 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_MODE, &buf, 1);
3244 //_bRW_MISCTL__MEA_SRCSEL = 8 + bCh; //From GIO1
3245 buf = 8 + bCh;
3246 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_SRCSEL, &buf, 1);
3247 //_wRW_MISCTL__MEA_MAX_NUM = bCNT; //Set the Measure Counts = 1
3248 buf = bCNT;
3249 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__MEA_MAX_NUM, &buf, 1);
3250 //_fRW_MISCTL__MEA_CLR = 0; //Frequency measure not clear
3251 gup_bit_write(_fRW_MISCTL__MEA, 1, 0);
3252 //_fRW_MISCTL__MEA_EN = 1;
3253 gup_bit_write(_fRW_MISCTL__MEA, 0, 1);
3254 }
3255
3256 static u32 gup_clk_count_get(void)
3257 {
3258 s32 ready = 0;
3259 s32 temp;
3260 s8 buf[4];
3261
3262 while ((ready == 0)) //Wait for measurement complete
3263 {
3264 i2c_read_bytes(i2c_client_point, _bRO_MISCTL__MEA_RDY, buf, 1);
3265 ready = buf[0];
3266 }
3267
3268 udelay(50);
3269
3270 //_fRW_MISCTL__MEA_EN = 0;
3271 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
3272 i2c_read_bytes(i2c_client_point, _dRO_MISCTL__MEA_VAL, buf, 4);
3273 GTP_INFO("Clk_count 0: %2X", buf[0]);
3274 GTP_INFO("Clk_count 1: %2X", buf[1]);
3275 GTP_INFO("Clk_count 2: %2X", buf[2]);
3276 GTP_INFO("Clk_count 3: %2X", buf[3]);
3277
3278 temp = (s32)buf[0] + ((s32)buf[1] << 8) + ((s32)buf[2] << 16) + ((s32)buf[3] << 24);
3279 GTP_INFO("Clk_count : %d", temp);
3280 return temp;
3281 }
3282 u8 gup_clk_dac_setting(int dac)
3283 {
3284 s8 buf1, buf2;
3285
3286 i2c_read_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
3287 i2c_read_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
3288
3289 buf1 = (buf1 & 0xFFCF) | ((dac & 0x03) << 4);
3290 buf2 = (dac >> 2) & 0x3f;
3291
3292 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
3293 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
3294
3295 return 0;
3296 }
3297
3298 static u8 gup_clk_calibration_pin_select(s32 bCh)
3299 {
3300 s32 i2c_addr;
3301
3302 switch (bCh)
3303 {
3304 case 0:
3305 i2c_addr = _fRW_MISCTL__GIO0;
3306 break;
3307
3308 case 1:
3309 i2c_addr = _fRW_MISCTL__GIO1;
3310 break;
3311
3312 case 2:
3313 i2c_addr = _fRW_MISCTL__GIO2;
3314 break;
3315
3316 case 3:
3317 i2c_addr = _fRW_MISCTL__GIO3;
3318 break;
3319
3320 case 4:
3321 i2c_addr = _fRW_MISCTL__GIO4;
3322 break;
3323
3324 case 5:
3325 i2c_addr = _fRW_MISCTL__GIO5;
3326 break;
3327
3328 case 6:
3329 i2c_addr = _fRW_MISCTL__GIO6;
3330 break;
3331
3332 case 7:
3333 i2c_addr = _fRW_MISCTL__GIO7;
3334 break;
3335
3336 case 8:
3337 i2c_addr = _fRW_MISCTL__GIO8;
3338 break;
3339
3340 case 9:
3341 i2c_addr = _fRW_MISCTL__GIO9;
3342 break;
3343 }
3344
3345 gup_bit_write(i2c_addr, 1, 0);
3346
3347 return 0;
3348 }
3349
3350 void gup_output_pulse(int t)
3351 {
3352 unsigned long flags;
3353 //s32 i;
3354
3355 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3356 udelay(10);
3357
3358 local_irq_save(flags);
3359
3360 mt_set_gpio_out(GTP_INT_PORT, 1);
3361 udelay(50);
3362 mt_set_gpio_out(GTP_INT_PORT, 0);
3363 udelay(t - 50);
3364 mt_set_gpio_out(GTP_INT_PORT, 1);
3365
3366 local_irq_restore(flags);
3367
3368 udelay(20);
3369 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3370 }
3371
3372 static void gup_sys_clk_init(void)
3373 {
3374 u8 buf;
3375
3376 //_fRW_MISCTL__RG_RXADC_CKMUX = 0;
3377 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 5, 0);
3378 //_bRW_MISCTL__RG_LDO_A18_PWD = 0; //DrvMISCTL_A18_PowerON
3379 buf = 0;
3380 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_LDO_A18_PWD, &buf, 1);
3381 //_bRW_MISCTL__RG_BG_PWD = 0; //DrvMISCTL_BG_PowerON
3382 buf = 0;
3383 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_BG_PWD, &buf, 1);
3384 //_bRW_MISCTL__RG_CLKGEN_PWD = 0; //DrvMISCTL_CLKGEN_PowerON
3385 buf = 0;
3386 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_CLKGEN_PWD, &buf, 1);
3387 //_fRW_MISCTL__RG_RXADC_PWD = 0; //DrvMISCTL_RX_ADC_PowerON
3388 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 0, 0);
3389 //_fRW_MISCTL__RG_RXADC_REF_PWD = 0; //DrvMISCTL_RX_ADCREF_PowerON
3390 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 1, 0);
3391 //gup_clk_dac_setting(60);
3392 //_bRW_MISCTL__OSC_CK_SEL = 1;;
3393 buf = 1;
3394 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__OSC_CK_SEL, &buf, 1);
3395 }
3396
3397 u8 gup_clk_calibration(void)
3398 {
3399 //u8 buf;
3400 //u8 trigger;
3401 s32 i;
3402 struct timeval start, end;
3403 s32 count;
3404 s32 count_ref;
3405 s32 sec;
3406 s32 usec;
3407 s32 ret = 0;
3408 //unsigned long flags;
3409
3410 //buf = 0x0C; // hold ss51 and dsp
3411 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
3412 ret = gup_hold_ss51_dsp(i2c_client_point);
3413 if (ret <= 0)
3414 {
3415 GTP_ERROR("[gup_clk_calibration]hold ss51 & dsp failed.");
3416 return FAIL;
3417 }
3418
3419 //_fRW_MISCTL__CLK_BIAS = 0; //disable clock bias
3420 gup_bit_write(_rRW_MISCTL_RG_DMY83, 7, 0);
3421
3422 //_fRW_MISCTL__GIO1_PU = 0; //set TOUCH INT PIN MODE as input
3423 gup_bit_write(_rRW_MISCTL__GIO1CTL_B2_, 0, 0);
3424
3425 //_fRW_MISCTL__GIO1_OE = 0; //set TOUCH INT PIN MODE as input
3426 gup_bit_write(_rRW_MISCTL__GIO1CTL_B1_, 1, 0);
3427
3428 //buf = 0x00;
3429 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
3430 //msleep(1000);
3431
3432 GTP_INFO("CLK calibration GO");
3433 gup_sys_clk_init();
3434 gup_clk_calibration_pin_select(1);//use GIO1 to do the calibration
3435
3436 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3437
3438 for (i = INIT_CLK_DAC; i < MAX_CLK_DAC; i++)
3439 {
3440 if (tpd_halt)
3441 {
3442 i = 80; // if sleeping while calibrating main clock, set it default 80
3443 break;
3444 }
3445 GTP_INFO("CLK calibration DAC %d", i);
3446
3447 gup_clk_dac_setting(i);
3448 gup_clk_count_init(1, CLK_AVG_TIME);
3449
3450 #if 0
3451 gup_output_pulse(PULSE_LENGTH);
3452 count = gup_clk_count_get();
3453
3454 if (count > PULSE_LENGTH * 60)//60= 60Mhz * 1us
3455 {
3456 break;
3457 }
3458
3459 #else
3460 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3461
3462 //local_irq_save(flags);
3463 do_gettimeofday(&start);
3464 mt_set_gpio_out(GTP_INT_PORT, 1);
3465 //local_irq_restore(flags);
3466
3467 msleep(1);
3468 mt_set_gpio_out(GTP_INT_PORT, 0);
3469 msleep(1);
3470
3471 //local_irq_save(flags);
3472 do_gettimeofday(&end);
3473 mt_set_gpio_out(GTP_INT_PORT, 1);
3474 //local_irq_restore(flags);
3475
3476 count = gup_clk_count_get();
3477 udelay(20);
3478 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3479
3480 usec = end.tv_usec - start.tv_usec;
3481 sec = end.tv_sec - start.tv_sec;
3482 count_ref = 60 * (usec+ sec * MILLION);//60= 60Mhz * 1us
3483
3484 GTP_DEBUG("== time %d, %d, %d", sec, usec, count_ref);
3485
3486 if (count > count_ref)
3487 {
3488 GTP_DEBUG("== count_diff %d", count - count_ref);
3489 break;
3490 }
3491
3492 #endif
3493 }
3494
3495 //clk_dac = i;
3496
3497 //gtp_reset_guitar(i2c_client_point, 20);
3498
3499 #if 0//for debug
3500 //-- ouput clk to GPIO 4
3501 buf = 0x00;
3502 i2c_write_bytes(i2c_client_point, 0x41FA, &buf, 1);
3503 buf = 0x00;
3504 i2c_write_bytes(i2c_client_point, 0x4104, &buf, 1);
3505 buf = 0x00;
3506 i2c_write_bytes(i2c_client_point, 0x4105, &buf, 1);
3507 buf = 0x00;
3508 i2c_write_bytes(i2c_client_point, 0x4106, &buf, 1);
3509 buf = 0x01;
3510 i2c_write_bytes(i2c_client_point, 0x4107, &buf, 1);
3511 buf = 0x06;
3512 i2c_write_bytes(i2c_client_point, 0x41F8, &buf, 1);
3513 buf = 0x02;
3514 i2c_write_bytes(i2c_client_point, 0x41F9, &buf, 1);
3515 #endif
3516
3517 GTP_GPIO_AS_INT(GTP_INT_PORT);
3518 return i;
3519 }
3520
3521
3522 #define BANK_LENGTH (16*1024)
3523 #define FIRMWARE_HEADER_LEN 14
3524
3525 static u32 current_system_length = 0;
3526
3527 char * gup_load_fw_from_file(char *filepath)
3528 {
3529 struct file *fw_file = NULL;
3530 mm_segment_t old_fs;
3531 long len = 0;
3532 char *buffer = NULL;
3533
3534 if(filepath == NULL)
3535 {
3536 GTP_ERROR("[Load_firmware]filepath: NULL");
3537 goto load_firmware_exit;
3538 }
3539
3540 old_fs = get_fs();
3541 set_fs(KERNEL_DS);
3542
3543 fw_file = filp_open(filepath, O_RDONLY, 0);
3544 if (fw_file == NULL || IS_ERR(fw_file))
3545 {
3546 GTP_ERROR("[Load_firmware]Failed to open: %s", filepath);
3547 goto load_firmware_exit;
3548 }
3549 fw_file->f_op->llseek(fw_file, 0, SEEK_SET);
3550 len = fw_file->f_op->llseek(fw_file, 0, SEEK_END);
3551 if(len<1024)
3552 {
3553 GTP_ERROR("[Load_firmware]Firmware is too short: %ld", len);
3554 goto load_firmware_failed;
3555 }
3556 buffer = (char *)kmalloc(sizeof(char) * len, GFP_KERNEL);
3557 if(buffer == NULL)
3558 {
3559 GTP_ERROR("[Load_firmware]Failed to allocate buffer: %ld", len);
3560 goto load_firmware_failed;
3561 }
3562
3563 memset(buffer, 0, sizeof(char) * len);
3564
3565 fw_file->f_op->llseek(fw_file, 0, SEEK_SET);
3566 fw_file->f_op->read(fw_file, buffer, len, &fw_file->f_pos);
3567
3568 GTP_ERROR("[Load_firmware]Load from file success: %ld %s", len, filepath);
3569
3570
3571 load_firmware_failed:
3572 filp_close(fw_file, NULL);
3573 set_fs(old_fs);
3574
3575 load_firmware_exit:
3576 return buffer;
3577 }
3578
3579 s32 gup_check_firmware(char *fw, u32 length)
3580 {
3581 u32 i = 0;
3582 u32 fw_checksum = 0;
3583 u16 temp;
3584
3585 for(i=0; i<length; i+=2)
3586 {
3587 temp = (fw[i]<<8) + fw[i+1];
3588 fw_checksum += temp;
3589 }
3590
3591 GTP_DEBUG("firmware checksum: %4X", fw_checksum&0xFFFF);
3592 if(fw_checksum&0xFFFF)
3593 {
3594 return FAIL;
3595 }
3596 return SUCCESS;
3597 }
3598
3599 s32 gup_enter_update_mode_noreset(void)
3600 {
3601 s32 ret = FAIL;
3602
3603 // disable watchdog
3604 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__TMR0_EN, 0x00);
3605 if (ret <= 0)
3606 {
3607 GTP_ERROR("[enter_update_mode]disable wdt fail.");
3608 return FAIL;
3609 }
3610 //select addr & hold ss51_dsp
3611 ret = gup_hold_ss51_dsp(i2c_client_point);
3612 if (ret <= 0)
3613 {
3614 GTP_ERROR("[enter_update_mode]hold ss51 & dsp failed.");
3615 return FAIL;
3616 }
3617
3618 //clear control flag
3619 ret = gup_set_ic_msg(i2c_client_point, _rRW_MISCTL__BOOT_CTL_, 0x00);
3620
3621 if (ret <= 0)
3622 {
3623 GTP_ERROR("[enter_update_mode]clear control flag fail.");
3624 return FAIL;
3625 }
3626
3627 //set scramble
3628 ret = gup_set_ic_msg(i2c_client_point, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
3629
3630 if (ret <= 0)
3631 {
3632 GTP_ERROR("[enter_update_mode]set scramble fail.");
3633 return FAIL;
3634 }
3635
3636 //enable accessing code
3637 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__MEM_CD_EN, 0x01);
3638
3639 if (ret <= 0)
3640 {
3641 GTP_ERROR("[enter_update_mode]enable accessing code fail.");
3642 return FAIL;
3643 }
3644
3645 return SUCCESS;
3646 }
3647
3648 s32 gup_load_by_bank(u8 bank, u8 need_check, u8 *fw, u32 length)
3649 {
3650 s32 ret = FAIL;
3651 s32 retry = 0;
3652
3653 GTP_DEBUG("[load_by_bank]begin download [bank:%d,length:%d].",bank,length);
3654 while(retry++ < 5)
3655 {
3656 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, bank);
3657 if (ret <= 0)
3658 {
3659 GTP_ERROR("[load_by_bank]select bank fail.");
3660 continue;
3661 }
3662
3663 ret = i2c_write_bytes(i2c_client_point, 0xC000,fw, length);
3664 if (ret == -1)
3665 {
3666 GTP_ERROR("[load_by_bank]download bank fail.");
3667 continue;
3668 }
3669
3670 if(need_check)
3671 {
3672 ret = gup_check_and_repair(i2c_client_point, 0xC000, fw, length);
3673 if(FAIL == ret)
3674 {
3675 GTP_ERROR("[load_by_bank]checked FW bank fail.");
3676 continue;
3677 }
3678 }
3679 break;
3680 }
3681 if(retry<5)
3682 {
3683 return SUCCESS;
3684 }
3685 else
3686 {
3687 return FAIL;
3688 }
3689 }
3690
3691 s32 gup_load_system(char *firmware, s32 length, u8 need_check)
3692 {
3693 s32 ret = -1;
3694 u8 bank = 0;
3695
3696 #ifdef CONFIG_OF_TOUCH
3697 disable_irq(touch_irq);
3698 #else
3699 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
3700 #endif
3701
3702 #if GTP_ESD_PROTECT
3703 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
3704 #endif
3705 ret = gup_enter_update_mode_noreset();
3706 if (FAIL == ret)
3707 {
3708 goto gup_load_system_exit;
3709 }
3710 GTP_DEBUG("enter update mode success.");
3711 while(length > 0)
3712 {
3713 u32 len = length >BANK_LENGTH? BANK_LENGTH:length;
3714 ret = gup_load_by_bank(bank, need_check, &firmware[bank*BANK_LENGTH], len);
3715 if(FAIL == ret)
3716 {
3717 goto gup_load_system_exit;
3718 }
3719 GTP_DEBUG("load bank%d length:%d success.", bank, len);
3720 bank++;
3721 length -= len;
3722 }
3723
3724 ret = gtp_fw_startup(i2c_client_point);
3725
3726 gup_load_system_exit:
3727 #if GTP_ESD_PROTECT
3728 #if FLASHLESS_FLASH_WORKROUND
3729
3730 #else
3731 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3732 #endif
3733 #endif
3734
3735 #ifdef CONFIG_OF_TOUCH
3736 enable_irq(touch_irq);
3737 #else
3738 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3739 #endif
3740
3741 return ret;
3742 }
3743
3744 s32 gup_load_fx_system(void)
3745 {
3746 s32 ret = -1;
3747 char *firmware = NULL;
3748 u32 is_load_from_file = 0;
3749 u32 length = 0;
3750
3751 GTP_INFO("[load_fx_system] Load authorization system.");
3752
3753 firmware = gtp_default_FW_hotknot2;
3754
3755 #if GTP_AUTO_UPDATE
3756 firmware = gup_load_fw_from_file( FX_SYSTEM_PATH );
3757 if(firmware == NULL)
3758 {
3759 firmware = gtp_default_FW_hotknot2;
3760 GTP_INFO("[load_fx_system] Use default firmware.");
3761 }
3762 else
3763 {
3764 is_load_from_file = 1;
3765 }
3766 #endif
3767
3768 length = firmware[0]*256*256*256+
3769 firmware[1]*256*256+
3770 firmware[2]*256+
3771 firmware[3];
3772
3773 if(length > 32*1024 || length < 4*1024 )
3774 {
3775 GTP_ERROR("[load_fx_system]firmware's length is invalid.");
3776 goto load_fx_exit;
3777 }
3778
3779 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3780 if(ret == FAIL)
3781 {
3782 GTP_ERROR("[load_fx_system]firmware's checksum is error.");
3783 goto load_fx_exit;
3784 }
3785
3786 current_system_length = length;
3787
3788 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], length, 1);
3789
3790 load_fx_exit:
3791
3792 if(is_load_from_file)
3793 {
3794 kfree(firmware);
3795 }
3796
3797 return ret;
3798 }
3799
3800
3801 s32 gup_load_hotknot_system(void)
3802 {
3803 s32 ret = -1;
3804 char *firmware = NULL;
3805 u32 is_load_from_file = 0;
3806 u32 length = 0;
3807
3808 GTP_INFO("[load_hotknot_system] Load hotknot system.");
3809 load_fw_process = 1;
3810
3811 firmware = gtp_default_FW_hotknot;
3812
3813 #if GTP_AUTO_UPDATE
3814 firmware = gup_load_fw_from_file( HOTKNOT_SYSTEM_PATH );
3815 if(firmware == NULL)
3816 {
3817 firmware = gtp_default_FW_hotknot;
3818 GTP_INFO("[load_hotknot_system] Use default firmware.");
3819 }
3820 else
3821 {
3822 is_load_from_file = 1;
3823 }
3824 #endif
3825
3826 length = firmware[0]*256*256*256+
3827 firmware[1]*256*256+
3828 firmware[2]*256+
3829 firmware[3];
3830 if(length > 32*1024 || length < 4*1024 )
3831 {
3832 GTP_ERROR("[load_hotknot_system]firmware's length is invalid.");
3833 goto load_hotknot_exit;
3834 }
3835
3836 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3837 if(ret == FAIL)
3838 {
3839 GTP_ERROR("[load_hotknot_system]firmware's checksum is error.");
3840 goto load_hotknot_exit;
3841 }
3842
3843 current_system_length = length;
3844
3845 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], length, 0);
3846
3847 load_hotknot_exit:
3848
3849 if(is_load_from_file)
3850 {
3851 kfree(firmware);
3852 }
3853
3854 return ret;
3855
3856 }
3857
3858
3859 s32 gup_recovery_main_system(void)
3860 {
3861 s32 ret = -1;
3862 char *firmware = NULL;
3863 u32 is_load_from_file = 0;
3864 u32 length = 0;
3865
3866 GTP_INFO("[recovery_main_system] Recovery main system.");
3867
3868 if(gtp_chip_type == CHIP_TYPE_GT9)
3869 {
3870 gtp_reset_guitar(i2c_client_point,10);
3871 load_fw_process = 0;
3872 return SUCCESS;
3873 }
3874 firmware = gtp_default_FW_fl;
3875
3876 #if GTP_AUTO_UPDATE
3877 firmware = gup_load_fw_from_file(MAIN_SYSTEM_PATH);
3878 if(firmware == NULL)
3879 {
3880 firmware = gtp_default_FW_fl;
3881 GTP_INFO("[recovery_main_system]Use default firmware.");
3882 }
3883 else
3884 {
3885 is_load_from_file = 1;
3886 }
3887 #endif
3888
3889 if(firmware[0]==0x00&&firmware[1]==0x90&&firmware[2]==0x06&&firmware[3]==0x00)
3890 {
3891 length = 36*1024;
3892 }
3893 else
3894 {
3895 length = firmware[0]*256*256*256+
3896 firmware[1]*256*256+
3897 firmware[2]*256+
3898 firmware[3];
3899 }
3900 if(length > 36*1024 || length < 16*1024 )
3901 {
3902 GTP_ERROR("[recovery_main_system]firmware's length is invalid.");
3903 goto recovery_main_system_exit;
3904 }
3905
3906 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3907 if(ret == FAIL)
3908 {
3909 GTP_ERROR("[recovery_main_system]firmware's checksum is error.");
3910 goto recovery_main_system_exit;
3911 }
3912
3913 if(current_system_length == 0)
3914 {
3915 current_system_length = length;
3916 }
3917
3918 GTP_INFO("[recovery_main_system] Recovery length: %d.", current_system_length);
3919
3920 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], current_system_length, 0);
3921
3922 #if (FLASHLESS_FLASH_WORKROUND && GTP_ESD_PROTECT)
3923 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3924 #endif
3925
3926 recovery_main_system_exit:
3927
3928 if(is_load_from_file)
3929 {
3930 kfree(firmware);
3931 }
3932
3933 load_fw_process = 0;
3934 return ret;
3935
3936 }
3937
3938 s32 gup_load_main_system(char *filepath)
3939 {
3940 s32 ret = -1;
3941 char *firmware = NULL;
3942 u32 is_load_from_file = 0;
3943 u32 length = 0;
3944
3945 GTP_INFO("[load_main_system] Load main system.");
3946
3947 if(filepath != NULL)
3948 {
3949 firmware = gup_load_fw_from_file(filepath);
3950 if(firmware == NULL)
3951 {
3952 GTP_INFO("[load_main_system]can not open file: %s", filepath);
3953 goto load_main_system_exit;
3954 }
3955 else
3956 {
3957 is_load_from_file = 1;
3958 }
3959 }
3960 else
3961 {
3962 firmware = gtp_default_FW_fl;
3963 }
3964 #if GTP_AUTO_UPDATE
3965 firmware = gup_load_fw_from_file(filepath);
3966 if(firmware == NULL)
3967 {
3968 if(gtp_chip_type == CHIP_TYPE_GT9)
3969 firmware = gtp_default_FW;
3970 else
3971 firmware = gtp_default_FW_fl;
3972 GTP_INFO("[load_main_system]Use default firmware. type:%d", gtp_chip_type);
3973 }
3974 else
3975 {
3976 is_load_from_file = 1;
3977 }
3978 #endif
3979
3980 if(firmware[0]==0x00&&firmware[1]==0x90&&firmware[2]==0x06&&firmware[3]==0x00)
3981 {
3982 length = 36*1024;
3983 }
3984 else
3985 {
3986 length = firmware[0]*256*256*256+
3987 firmware[1]*256*256+
3988 firmware[2]*256+
3989 firmware[3];
3990 if(length > 36*1024)
3991 {
3992 length = 36*1024;
3993 }
3994 }
3995 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3996 if(ret == FAIL)
3997 {
3998 GTP_ERROR("[load_main_system]firmware's checksum is error.");
3999 goto load_main_system_exit;
4000 }
4001 GTP_INFO("[load_main_system] Firmware length: %d.", length);
4002
4003 //memcpy(gtp_default_FW_fl, firmware, length);
4004
4005 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], length, 1);
4006 show_len = 100;
4007
4008 #if (FLASHLESS_FLASH_WORKROUND && GTP_ESD_PROTECT)
4009 gtp_esd_switch(i2c_client_point, SWITCH_ON);
4010 #endif
4011
4012 load_main_system_exit:
4013
4014 if(is_load_from_file)
4015 {
4016 kfree(firmware);
4017 }
4018
4019 return ret;
4020 }
4021 #endif
4022 //*************** For GT9XXF End ***********************//
kernel source for telekom puls (alcatel/mediatek)