projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / input / touchscreen / mediatek / GT9XX_2 / gt9xx_update.c
1 /* drivers/input/touchscreen/gt9xx_update.c
2 *
3 * 2010 - 2012 Goodix Technology.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be a reference
11 * to you, when you are integrating the GOODiX's CTP IC into your system,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * Version: 2.0
17 * Revision Record:
18 * V1.0: first release. by Andrew, 2012/08/27.
19 * V1.2: modify gt9110p pid map, by Andrew, 2012/10/15
20 * V1.4:
21 * 1. modify gup_enter_update_mode,
22 * 2. rewrite i2c read/write func
23 * 3. check update file checksum
24 * by Andrew, 2012/12/12
25 * v1.6:
26 * 1. delete GTP_FW_DOWNLOAD related things.
27 * 2. add GTP_HEADER_FW_UPDATE switch to update fw by gtp_default_fw in *.h directly
28 * by Meta, 2013/04/18
29 * V2.0:
30 * 1. GT9XXF main clock calibration
31 * 2. header fw update no fs related
32 * 3. update file searching optimization
33 * 4. config update as module, switchable
34 * by Meta, 2013/08/28
35 */
36 #include "tpd.h"
37 #include <linux/interrupt.h>
38 #include <cust_eint.h>
39 #include <linux/i2c.h>
40 #include <linux/sched.h>
41 #include <linux/kthread.h>
42 #include <linux/rtpm_prio.h>
43 #include <linux/wait.h>
44 #include <linux/time.h>
45 #include <linux/delay.h>
46 #include <linux/namei.h>
47 #include <linux/mount.h>
48 #include "cust_gpio_usage.h"
49 #include <asm/uaccess.h>
50
51 #include "tpd_custom_gt9xx.h"
52
53 #if ( (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE) || GTP_COMPATIBLE_MODE || defined(SELF_APK_UPGRADE) )
54 #include "gt9xx_firmware.h"
55 #endif
56
57 #define GUP_REG_HW_INFO 0x4220
58 #define GUP_REG_FW_MSG 0x41E4
59 #define GUP_REG_PID_VID 0x8140
60
61 #define GUP_SEARCH_FILE_TIMES 50
62 #define UPDATE_FILE_PATH_1 "/data/_goodix_update_.bin"
63 #define UPDATE_FILE_PATH_2 "/sdcard/_goodix_update_.bin"
64
65 #define CONFIG_FILE_PATH_1 "/data/_goodix_config_.cfg"
66 #define CONFIG_FILE_PATH_2 "/sdcard/_goodix_config_.cfg"
67
68 #define FW_HEAD_LENGTH 14
69 #define FW_DOWNLOAD_LENGTH 0x4000
70 #define FW_SECTION_LENGTH 0x2000
71 #define FW_DSP_ISP_LENGTH 0x1000
72 #define FW_DSP_LENGTH 0x1000
73 #define FW_BOOT_LENGTH 0x800
74
75 #define PACK_SIZE 256
76 #define MAX_FRAME_CHECK_TIME 5
77
78 #define _bRW_MISCTL__SRAM_BANK 0x4048
79 #define _bRW_MISCTL__MEM_CD_EN 0x4049
80 #define _bRW_MISCTL__CACHE_EN 0x404B
81 #define _bRW_MISCTL__TMR0_EN 0x40B0
82 #define _rRW_MISCTL__SWRST_B0_ 0x4180
83 #define _bWO_MISCTL__CPU_SWRST_PULSE 0x4184
84 #define _rRW_MISCTL__BOOTCTL_B0_ 0x4190
85 #define _rRW_MISCTL__BOOT_OPT_B0_ 0x4218
86 #define _rRW_MISCTL__BOOT_CTL_ 0x5094
87
88 #define AUTO_SEARCH_BIN 0x01
89 #define AUTO_SEARCH_CFG 0x02
90 #define BIN_FILE_READY 0x80
91 #define CFG_FILE_READY 0x08
92 #define HEADER_FW_READY 0x01
93
94 #define FAIL 0
95 #define SUCCESS 1
96
97 #pragma pack(1)
98 typedef struct
99 {
100 u8 hw_info[4]; //hardware info//
101 u8 pid[8]; //product id //
102 u16 vid; //version id //
103 } st_fw_head;
104 #pragma pack()
105
106 typedef struct
107 {
108 u8 force_update;
109 u8 fw_flag;
110 struct file *file;
111 struct file *cfg_file;
112 st_fw_head ic_fw_msg;
113 mm_segment_t old_fs;
114 } st_update_msg;
115
116 st_update_msg update_msg;
117 extern struct i2c_client *i2c_client_point;
118 u16 show_len;
119 u16 total_len;
120 extern u8 fw_updating;
121 extern u8 cfg_len;
122 u8 searching_file = 0;
123 u8 got_file_flag = 0;
124
125 #if GTP_ESD_PROTECT
126 extern void gtp_esd_switch(struct i2c_client *client, s32 on);
127 #endif
128
129 #if GTP_COMPATIBLE_MODE
130 extern CHIP_TYPE_T gtp_chip_type;
131 extern u8 rqst_processing;
132 extern u8 is_950;
133 extern u8 gtp_fw_startup(struct i2c_client *client);
134 static u8 gup_check_and_repair(struct i2c_client *, s32 , u8 *, u32 );
135 s32 gup_fw_download_proc(void *dir, u8 dwn_mode);
136 #endif
137
138 #define _CLOSE_FILE(p_file) if (p_file && !IS_ERR(p_file)) \
139 { \
140 filp_close(p_file, NULL); \
141 }
142
143 static s32 gup_i2c_read(struct i2c_client *client, u8 *buf, s32 len)
144 {
145 s32 ret = -1;
146 u16 addr = (buf[0] << 8) + buf[1];
147
148 ret = i2c_read_bytes(client, addr, &buf[2], len - 2);
149
150 if (!ret)
151 {
152 return 2;
153 }
154 else
155 {
156 return ret;
157 }
158 }
159
160 static s32 gup_i2c_write(struct i2c_client *client, u8 *buf, s32 len)
161 {
162 s32 ret = -1;
163 u16 addr = (buf[0] << 8) + buf[1];
164
165 ret = i2c_write_bytes(client, addr, &buf[2], len - 2);
166
167 if (!ret)
168 {
169 return 1;
170 }
171 else
172 {
173 return ret;
174 }
175 }
176
177 static u8 gup_get_ic_msg(struct i2c_client *client, u16 addr, u8 *msg, s32 len)
178 {
179 s32 i = 0;
180
181 msg[0] = (addr >> 8) & 0xff;
182 msg[1] = addr & 0xff;
183
184 for (i = 0; i < 5; i++)
185 {
186 if (gup_i2c_read(client, msg, GTP_ADDR_LENGTH + len) > 0)
187 {
188 break;
189 }
190 }
191
192 if (i >= 5)
193 {
194 GTP_ERROR("Read data from 0x%02x%02x failed!", msg[0], msg[1]);
195 return FAIL;
196 }
197
198 return SUCCESS;
199 }
200
201 static u8 gup_set_ic_msg(struct i2c_client *client, u16 addr, u8 val)
202 {
203 s32 i = 0;
204 u8 msg[3];
205
206 msg[0] = (addr >> 8) & 0xff;
207 msg[1] = addr & 0xff;
208 msg[2] = val;
209
210 for (i = 0; i < 5; i++)
211 {
212 if (gup_i2c_write(client, msg, GTP_ADDR_LENGTH + 1) > 0)
213 {
214 break;
215 }
216 }
217
218 if (i >= 5)
219 {
220 GTP_ERROR("Set data to 0x%02x%02x failed!", msg[0], msg[1]);
221 return FAIL;
222 }
223
224 return SUCCESS;
225 }
226
227 static u8 gup_get_ic_fw_msg(struct i2c_client *client)
228 {
229 s32 ret = -1;
230 u8 retry = 0;
231 u8 buf[16];
232 u8 i;
233
234 //step1:get hardware info
235 ret = gtp_i2c_read_dbl_check(client, GUP_REG_HW_INFO, &buf[GTP_ADDR_LENGTH], 4);
236 if (FAIL == ret)
237 {
238 GTP_ERROR("[get_ic_fw_msg]get hw_info failed,exit");
239 return FAIL;
240 }
241
242 // buf[2~5]: 00 06 90 00
243 // hw_info: 00 90 06 00
244 for (i = 0; i < 4; i++)
245 {
246 update_msg.ic_fw_msg.hw_info[i] = buf[GTP_ADDR_LENGTH + 3 - i];
247 }
248
249 GTP_INFO("IC Hardware info:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
250 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
251
252 //step2:get firmware message
253 for (retry = 0; retry < 2; retry++)
254 {
255 ret = gup_get_ic_msg(client, GUP_REG_FW_MSG, buf, 1);
256
257 if (FAIL == ret)
258 {
259 GTP_ERROR("Read firmware message fail.");
260 return ret;
261 }
262
263 update_msg.force_update = buf[GTP_ADDR_LENGTH];
264
265 if ((0xBE != update_msg.force_update) && (!retry))
266 {
267 GTP_INFO("The check sum in ic is error.");
268 GTP_INFO("The IC will be updated by force.");
269 continue;
270 }
271 break;
272 }
273
274 GTP_INFO("IC force update flag:0x%x", update_msg.force_update);
275
276 //step3:get pid & vid
277 ret = gtp_i2c_read_dbl_check(client, GUP_REG_PID_VID, &buf[GTP_ADDR_LENGTH], 6);
278 if (FAIL == ret)
279 {
280 GTP_ERROR("[get_ic_fw_msg]get pid & vid failed,exit");
281 return FAIL;
282 }
283
284 memset(update_msg.ic_fw_msg.pid, 0, sizeof(update_msg.ic_fw_msg.pid));
285 memcpy(update_msg.ic_fw_msg.pid, &buf[GTP_ADDR_LENGTH], 4);
286
287
288 //GT9XX PID MAPPING
289 /*|-----FLASH-----RAM-----|
290 |------918------918-----|
291 |------968------968-----|
292 |------913------913-----|
293 |------913P-----913P----|
294 |------927------927-----|
295 |------927P-----927P----|
296 |------9110-----9110----|
297 |------9110P----9111----|*/
298 if(update_msg.ic_fw_msg.pid[0] != 0)
299 {
300 if (!memcmp(update_msg.ic_fw_msg.pid, "9111", 4))
301 {
302 GTP_INFO("IC Mapping Product id:%s", update_msg.ic_fw_msg.pid);
303 memcpy(update_msg.ic_fw_msg.pid, "9110P", 5);
304 }
305 }
306
307 update_msg.ic_fw_msg.vid = buf[GTP_ADDR_LENGTH + 4] + (buf[GTP_ADDR_LENGTH + 5] << 8);
308 return SUCCESS;
309 }
310
311 // add by anxiang.xiao 20131114
312 /*
313 function : get file firmware version in firmware.h
314 */
315 void get_file_fw_version(u16 *file_fw_version)
316 {
317 st_fw_head file_fw_head;
318
319 if (CHIP_TYPE_GT9F == gtp_chip_type)
320 {
321 memcpy(&file_fw_head, gtp_default_FW_fl, FW_HEAD_LENGTH);
322 }
323 else
324 {
325 memcpy(&file_fw_head, gtp_default_FW, FW_HEAD_LENGTH);
326 }
327 *file_fw_version = ((file_fw_head.vid & 0xFF00) >> 8) + ((file_fw_head.vid & 0x00FF) << 8);
328 }
329 //end
330
331 s32 gup_enter_update_mode(struct i2c_client *client)
332 {
333 s32 ret = -1;
334 s32 retry = 0;
335 u8 rd_buf[3];
336
337 //step1:RST output low last at least 2ms
338 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
339 msleep(2);
340
341 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
342 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
343 msleep(2);
344
345 //step3:RST output high reset guitar
346 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
347
348 //20121211 modify start
349 msleep(5);
350 while(retry++ < 200)
351 {
352 //step4:Hold ss51 & dsp
353 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
354 if(ret <= 0)
355 {
356 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
357 continue;
358 }
359
360 //step5:Confirm hold
361 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
362 if(ret <= 0)
363 {
364 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
365 continue;
366 }
367 if(0x0C == rd_buf[GTP_ADDR_LENGTH])
368 {
369 GTP_DEBUG("Hold ss51 & dsp confirm SUCCESS");
370 break;
371 }
372 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
373 }
374 if(retry >= 200)
375 {
376 GTP_ERROR("Enter update Hold ss51 failed.");
377 return FAIL;
378 }
379
380 //step6:DSP_CK and DSP_ALU_CK PowerOn
381 ret = gup_set_ic_msg(client, 0x4010, 0x00);
382
383 //20121211 modify end
384 return ret;
385 }
386
387 void gup_leave_update_mode(void)
388 {
389 GTP_GPIO_AS_INT(GTP_INT_PORT);
390
391 GTP_DEBUG("[leave_update_mode]reset chip.");
392 gtp_reset_guitar(i2c_client_point, 20);
393 }
394
395 static u8 gup_enter_update_judge(st_fw_head *fw_head)
396 {
397 u16 u16_tmp;
398 s32 i = 0;
399 u8 pid_cmp_len = 0;
400 //Get the correct nvram data
401 //The correct conditions:
402 //1. the hardware info is the same
403 //2. the product id is the same
404 //3. the firmware version in update file is greater than the firmware version in ic
405 //or the check sum in ic is wrong
406
407 u16_tmp = fw_head->vid;
408 fw_head->vid = (u16)(u16_tmp >> 8) + (u16)(u16_tmp << 8);
409
410 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
411 GTP_INFO("FILE PID:%s", fw_head->pid);
412 GTP_INFO("FILE VID:%04x", fw_head->vid);
413 GTP_INFO("IC HARDWARE INFO:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
414 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
415 GTP_INFO("IC PID:%s", update_msg.ic_fw_msg.pid);
416 GTP_INFO("IC VID:%04x", update_msg.ic_fw_msg.vid);
417
418 //First two conditions
419 if (!memcmp(fw_head->hw_info, update_msg.ic_fw_msg.hw_info, sizeof(update_msg.ic_fw_msg.hw_info)))
420 {
421 GTP_INFO("Get the same hardware info.");
422 if (update_msg.force_update != 0xBE)
423 {
424 GTP_INFO("FW chksum error,need enter update.");
425 return SUCCESS;
426 }
427
428 // 20130523 start
429 if (strlen(update_msg.ic_fw_msg.pid) < 3)
430 {
431 GTP_INFO("Illegal IC pid, need enter update");
432 return SUCCESS;
433 }
434 else
435 {
436 for (i = 0; i < 3; i++)
437 {
438 if ((update_msg.ic_fw_msg.pid[i] < 0x30) || (update_msg.ic_fw_msg.pid[i] > 0x39))
439 {
440 GTP_INFO("Illegal IC pid, out of bound, need enter update");
441 return SUCCESS;
442 }
443 }
444 }
445 // 20130523 end
446
447 pid_cmp_len = strlen(fw_head->pid);
448 if (pid_cmp_len < strlen(update_msg.ic_fw_msg.pid))
449 {
450 pid_cmp_len = strlen(update_msg.ic_fw_msg.pid);
451 }
452
453 if ((!memcmp(fw_head->pid, update_msg.ic_fw_msg.pid, pid_cmp_len)) ||
454 (!memcmp(update_msg.ic_fw_msg.pid, "91XX", 4)) ||
455 (!memcmp(fw_head->pid, "91XX", 4)))
456 {
457 if(!memcmp(fw_head->pid, "91XX", 4))
458 {
459 GTP_DEBUG("Force none same pid update mode.");
460 }
461 else
462 {
463 GTP_DEBUG("Get the same pid.");
464 }
465
466 //The third condition
467 if (fw_head->vid > update_msg.ic_fw_msg.vid)
468 {
469
470 GTP_INFO("Need enter update.");
471 return SUCCESS;
472 }
473
474 GTP_INFO("Don't meet the third condition.");
475 GTP_ERROR("File VID <= IC VID, update aborted!");
476 }
477 else
478 {
479 GTP_ERROR("File PID != IC PID, update aborted!");
480 }
481 }
482 else
483 {
484 GTP_ERROR("Different Hardware, update aborted!");
485 }
486
487 return FAIL;
488 }
489
490 #if GTP_AUTO_UPDATE_CFG
491 static s32 gup_update_config(struct i2c_client *client)
492 {
493 struct file *cfg_filp;
494 s32 ret = 0;
495 s32 i = 0;
496 u32 cfg = 0;
497 u8 chksum = 0;
498 u8 gt_config[228] = {0};
499 char *sconfig = NULL;
500 u16 file_len = 0;
501
502 cfg_filp = update_msg.cfg_file;
503
504 if (IS_ERR(cfg_filp))
505 {
506 GTP_ERROR("Config file is Invalid");
507 return FAIL;
508 }
509
510 cfg_filp->f_op->llseek(cfg_filp, 0, SEEK_SET);
511 file_len = cfg_filp->f_op->llseek(cfg_filp, 0, SEEK_END);
512
513 GTP_DEBUG("file len: %d", file_len);
514 if (file_len < (cfg_len * 3))
515 {
516 GTP_ERROR("invalid config file, config update aborted!");
517 _CLOSE_FILE(cfg_filp);
518 return FAIL;
519 }
520
521 sconfig = (char *)kmalloc(sizeof(char) * (file_len + 1), GFP_KERNEL);
522 memset(sconfig, 0, sizeof(char) * (file_len + 1));
523
524 cfg_filp->f_op->llseek(cfg_filp, 0, SEEK_SET);
525 ret = cfg_filp->f_op->read(cfg_filp, sconfig, file_len, &cfg_filp->f_pos);
526 _CLOSE_FILE(cfg_filp);
527 if (ret < 0)
528 {
529 GTP_ERROR("failed to read config file");
530 kfree(sconfig);
531 return FAIL;
532 }
533 GTP_DEBUG("sconfig: %s", sconfig);
534 // clear whitespace
535 for (ret = 0, i = 0; ret < file_len; ++ret)
536 {
537 if ((sconfig[ret] == ' ') ||
538 (sconfig[ret] == '\n') ||
539 (sconfig[ret] == '\r') ||
540 (sconfig[ret] == '\t') ||
541 (sconfig[ret] == '\\')
542 )
543 {
544 continue;
545 }
546 sconfig[i++] = sconfig[ret];
547 }
548 GTP_DEBUG("After cleanup: %d", i);
549 file_len = i;
550
551 sscanf(sconfig, "0x%02X", &cfg);
552 gt_config[0] = (u8)cfg;
553 for (ret = 4, i = 1; ret < file_len; ret += 5)
554 {
555 sscanf(sconfig+ret, ",0x%02X", &cfg);
556 gt_config[i] = (u8)cfg;
557 ++i;
558 }
559
560 kfree(sconfig);
561
562 GTP_INFO("File config len: %d", i);
563 GTP_DEBUG_ARRAY(gt_config, i);
564
565 // check checksum
566 for (ret = 0; ret < (i-2); ++ret)
567 {
568 chksum += gt_config[ret];
569 }
570 chksum = (~chksum) + 1;
571 if (chksum != gt_config[i-2])
572 {
573 GTP_ERROR("Wrong checksum, config update aborted!");
574 return FAIL;
575 }
576 // check update flag
577 if (gt_config[i-1] != 0x01)
578 {
579 GTP_ERROR("Unsetted config update flag, config update aborted!");
580 return FAIL;
581 }
582
583 ret = i2c_write_bytes(client, GTP_REG_CONFIG_DATA, gt_config, i);
584
585 if (ret < 0)
586 {
587 GTP_ERROR("write config data failed, config update failed!");
588 return FAIL;
589 }
590 GTP_INFO("Config update successfully!");
591 msleep(500); // ic store config info into flash
592 return SUCCESS;
593 }
594 #endif
595
596
597
598 #if GTP_AUTO_UPDATE || defined(SELF_APK_UPGRADE)
599 static void gup_search_file(s32 search_type)
600 {
601 s32 i = 0;
602 struct file *pfile = NULL;
603
604 got_file_flag = 0x00;
605
606 searching_file = 1;
607 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
608 {
609 if (0 == searching_file)
610 {
611 GTP_INFO("Force exiting file searching");
612 got_file_flag = 0x00;
613 return;
614 }
615
616 if (search_type & AUTO_SEARCH_BIN)
617 {
618 GTP_DEBUG("Search for %s, %s for fw update.(%d/%d)", UPDATE_FILE_PATH_1, UPDATE_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
619 pfile = filp_open(UPDATE_FILE_PATH_1, O_RDONLY, 0);
620 if (IS_ERR(pfile))
621 {
622 pfile = filp_open(UPDATE_FILE_PATH_2, O_RDONLY, 0);
623 if (!IS_ERR(pfile))
624 {
625 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_2);
626 got_file_flag |= BIN_FILE_READY;
627 update_msg.file = pfile;
628 }
629 }
630 else
631 {
632 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_1);
633 got_file_flag |= BIN_FILE_READY;
634 update_msg.file = pfile;
635 }
636 if (got_file_flag & BIN_FILE_READY)
637 {
638 #if GTP_AUTO_UPDATE_CFG
639 if (search_type & AUTO_SEARCH_CFG)
640 {
641 i = GUP_SEARCH_FILE_TIMES; // Bin & Cfg File required to be in the same directory
642 }
643 else
644 #endif
645 {
646 searching_file = 0;
647 return;
648 }
649 }
650 }
651
652 #if GTP_AUTO_UPDATE_CFG
653 if ( (search_type & AUTO_SEARCH_CFG) && !(got_file_flag & CFG_FILE_READY) )
654 {
655 GTP_DEBUG("Search for %s, %s for config update.(%d/%d)", CONFIG_FILE_PATH_1, CONFIG_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
656 pfile = filp_open(CONFIG_FILE_PATH_1, O_RDONLY, 0);
657 if (IS_ERR(pfile))
658 {
659 pfile = filp_open(CONFIG_FILE_PATH_2, O_RDONLY, 0);
660 if (!IS_ERR(pfile))
661 {
662 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_2);
663 got_file_flag |= CFG_FILE_READY;
664 update_msg.cfg_file = pfile;
665 }
666 }
667 else
668 {
669 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_1);
670 got_file_flag |= CFG_FILE_READY;
671 update_msg.cfg_file = pfile;
672 }
673 if (got_file_flag & CFG_FILE_READY)
674 {
675 searching_file = 0;
676 return;
677 }
678 }
679 #endif
680 msleep(3000);
681 }
682 searching_file = 0;
683 }
684 #endif
685
686 static u8 gup_check_update_file(struct i2c_client *client, st_fw_head *fw_head, u8 *path)
687 {
688 s32 ret = 0;
689 s32 i = 0;
690 s32 fw_checksum = 0;
691 u8 buf[FW_HEAD_LENGTH];
692
693 got_file_flag = 0x00;
694 if (path)
695 {
696 GTP_DEBUG("Update File path:%s, %d", path, strlen(path));
697 update_msg.file = filp_open(path, O_RDONLY, 0);
698
699 if (IS_ERR(update_msg.file))
700 {
701 GTP_ERROR("Open update file(%s) error!", path);
702 return FAIL;
703 }
704 got_file_flag = BIN_FILE_READY;
705 }
706 else
707 {
708 #if GTP_AUTO_UPDATE || defined(SELF_APK_UPGRADE)
709 #if GTP_HEADER_FW_UPDATE
710 GTP_INFO("Update by default firmware array");
711 if (sizeof(gtp_default_FW) < (FW_HEAD_LENGTH + FW_SECTION_LENGTH*4+FW_DSP_ISP_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH))
712 {
713 GTP_INFO("[check_update_file]default firmware array is INVALID!");
714 return FAIL;
715 }
716 memcpy(buf, &gtp_default_FW[0], FW_HEAD_LENGTH);
717 memcpy(fw_head, buf, FW_HEAD_LENGTH);
718 //check firmware legality
719 fw_checksum = 0;
720 for(i=0; i<FW_SECTION_LENGTH*4+FW_DSP_ISP_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH; i+=2)
721 {
722 u16 temp;
723 memcpy(buf, &gtp_default_FW[FW_HEAD_LENGTH + i], 2);
724 temp = (buf[0]<<8) + buf[1];
725 fw_checksum += temp;
726 }
727
728 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
729 if(fw_checksum&0xFFFF)
730 {
731 GTP_ERROR("Illegal firmware file.");
732 return FAIL;
733 }
734 got_file_flag = HEADER_FW_READY;
735 return SUCCESS;
736
737 #else
738 #if GTP_AUTO_UPDATE_CFG
739 gup_search_file(AUTO_SEARCH_BIN | AUTO_SEARCH_CFG);
740 if (got_file_flag & CFG_FILE_READY)
741 {
742 ret = gup_update_config(client);
743 if (FAIL == ret)
744 {
745 GTP_ERROR("Update config failed!");
746 }
747 }
748 #else
749 gup_search_file(AUTO_SEARCH_BIN);
750 #endif
751
752 if (!(got_file_flag & BIN_FILE_READY))
753 {
754 GTP_ERROR("No bin file for fw Update");
755 return FAIL;
756 }
757 #endif
758 #else
759 {
760 GTP_ERROR("NULL file for fw update!");
761 return FAIL;
762 }
763 #endif
764 }
765
766 update_msg.old_fs = get_fs();
767 set_fs(KERNEL_DS);
768
769 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
770
771 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, FW_HEAD_LENGTH, &update_msg.file->f_pos);
772
773 if (ret < 0)
774 {
775 GTP_ERROR("Read firmware head in update file error.");
776 goto load_failed;
777 }
778
779 memcpy(fw_head, buf, FW_HEAD_LENGTH);
780
781 //check firmware legality
782 fw_checksum = 0;
783 for(i=0; i<FW_SECTION_LENGTH*4+FW_DSP_ISP_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH; i+=2)
784 {
785 u16 temp;
786 ret = update_msg.file->f_op->read(update_msg.file, (char*)buf, 2, &update_msg.file->f_pos);
787 if (ret < 0)
788 {
789 GTP_ERROR("Read firmware file error.");
790 goto load_failed;
791 }
792 //GTP_DEBUG("BUF[0]:%x", buf[0]);
793 temp = (buf[0]<<8) + buf[1];
794 fw_checksum += temp;
795 }
796
797 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
798 if(fw_checksum&0xFFFF)
799 {
800 GTP_ERROR("Illegal firmware file.");
801 goto load_failed;
802 }
803
804 return SUCCESS;
805
806 load_failed:
807 set_fs(update_msg.old_fs);
808 _CLOSE_FILE(update_msg.file);
809 return FAIL;
810 }
811
812 static u8 gup_burn_proc(struct i2c_client *client, u8 *burn_buf, u16 start_addr, u16 total_length)
813 {
814 s32 ret = 0;
815 u16 burn_addr = start_addr;
816 u16 frame_length = 0;
817 u16 burn_length = 0;
818 u8 wr_buf[PACK_SIZE + GTP_ADDR_LENGTH];
819 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
820 u8 retry = 0;
821
822 GTP_DEBUG("Begin burn %dk data to addr 0x%x", (total_length / 1024), start_addr);
823
824 while (burn_length < total_length)
825 {
826 GTP_DEBUG("B/T:%04d/%04d", burn_length, total_length);
827 frame_length = ((total_length - burn_length) > PACK_SIZE) ? PACK_SIZE : (total_length - burn_length);
828 wr_buf[0] = (u8)(burn_addr >> 8);
829 rd_buf[0] = wr_buf[0];
830 wr_buf[1] = (u8)burn_addr;
831 rd_buf[1] = wr_buf[1];
832 memcpy(&wr_buf[GTP_ADDR_LENGTH], &burn_buf[burn_length], frame_length);
833
834 for (retry = 0; retry < MAX_FRAME_CHECK_TIME; retry++)
835 {
836 ret = gup_i2c_write(client, wr_buf, GTP_ADDR_LENGTH + frame_length);
837
838 if (ret <= 0)
839 {
840 GTP_ERROR("Write frame data i2c error.");
841 continue;
842 }
843
844 ret = gup_i2c_read(client, rd_buf, GTP_ADDR_LENGTH + frame_length);
845
846 if (ret <= 0)
847 {
848 GTP_ERROR("Read back frame data i2c error.");
849 continue;
850 }
851
852 if (memcmp(&wr_buf[GTP_ADDR_LENGTH], &rd_buf[GTP_ADDR_LENGTH], frame_length))
853 {
854 GTP_ERROR("Check frame data fail,not equal.");
855 GTP_DEBUG("write array:");
856 GTP_DEBUG_ARRAY(&wr_buf[GTP_ADDR_LENGTH], frame_length);
857 GTP_DEBUG("read array:");
858 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
859 continue;
860 }
861 else
862 {
863 //GTP_DEBUG("Check frame data success.");
864 break;
865 }
866 }
867
868 if (retry > MAX_FRAME_CHECK_TIME)
869 {
870 GTP_ERROR("Burn frame data time out,exit.");
871 return FAIL;
872 }
873
874 burn_length += frame_length;
875 burn_addr += frame_length;
876 }
877
878 return SUCCESS;
879 }
880
881 static u8 gup_load_section_file(u8 *buf, u16 offset, u16 length)
882 {
883 #if ((GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE) || defined(SELF_APK_UPGRADE) )
884 if (HEADER_FW_READY == got_file_flag)
885 {
886 memcpy(buf, &gtp_default_FW[FW_HEAD_LENGTH + offset], length);
887 return SUCCESS;
888 }
889 #endif
890 {
891 s32 ret = 0;
892
893 if (update_msg.file == NULL)
894 {
895 GTP_ERROR("cannot find update file,load section file fail.");
896 return FAIL;
897 }
898
899 update_msg.file->f_pos = FW_HEAD_LENGTH + offset;
900
901 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, length, &update_msg.file->f_pos);
902
903 if (ret < 0)
904 {
905 GTP_ERROR("Read update file fail.");
906 return FAIL;
907 }
908
909 return SUCCESS;
910 }
911 }
912
913 static u8 gup_recall_check(struct i2c_client *client, u8 *chk_src, u16 start_rd_addr, u16 chk_length)
914 {
915 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
916 s32 ret = 0;
917 u16 recall_addr = start_rd_addr;
918 u16 recall_length = 0;
919 u16 frame_length = 0;
920
921 while (recall_length < chk_length)
922 {
923 frame_length = ((chk_length - recall_length) > PACK_SIZE) ? PACK_SIZE : (chk_length - recall_length);
924 ret = gup_get_ic_msg(client, recall_addr, rd_buf, frame_length);
925
926 if (ret <= 0)
927 {
928 GTP_ERROR("recall i2c error,exit");
929 return FAIL;
930 }
931
932 if (memcmp(&rd_buf[GTP_ADDR_LENGTH], &chk_src[recall_length], frame_length))
933 {
934 GTP_ERROR("Recall frame data fail,not equal.");
935 GTP_DEBUG("chk_src array:");
936 GTP_DEBUG_ARRAY(&chk_src[recall_length], frame_length);
937 GTP_DEBUG("recall array:");
938 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
939 return FAIL;
940 }
941
942 recall_length += frame_length;
943 recall_addr += frame_length;
944 }
945
946 GTP_DEBUG("Recall check %dk firmware success.", (chk_length / 1024));
947
948 return SUCCESS;
949 }
950
951 static u8 gup_burn_fw_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u8 bank_cmd)
952 {
953 s32 ret = 0;
954 u8 rd_buf[5];
955
956 //step1:hold ss51 & dsp
957 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
958
959 if (ret <= 0)
960 {
961 GTP_ERROR("[burn_fw_section]hold ss51 & dsp fail.");
962 return FAIL;
963 }
964
965 //step2:set scramble
966 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
967
968 if (ret <= 0)
969 {
970 GTP_ERROR("[burn_fw_section]set scramble fail.");
971 return FAIL;
972 }
973
974 //step3:select bank
975 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
976
977 if (ret <= 0)
978 {
979 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
980 return FAIL;
981 }
982
983 //step4:enable accessing code
984 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
985
986 if (ret <= 0)
987 {
988 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
989 return FAIL;
990 }
991
992 //step5:burn 8k fw section
993 ret = gup_burn_proc(client, fw_section, start_addr, FW_SECTION_LENGTH);
994
995 if (FAIL == ret)
996 {
997 GTP_ERROR("[burn_fw_section]burn fw_section fail.");
998 return FAIL;
999 }
1000
1001 //step6:hold ss51 & release dsp
1002 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
1003
1004 if (ret <= 0)
1005 {
1006 GTP_ERROR("[burn_fw_section]hold ss51 & release dsp fail.");
1007 return FAIL;
1008 }
1009
1010 //must delay
1011 msleep(1);
1012
1013 //step7:send burn cmd to move data to flash from sram
1014 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd & 0x0f);
1015
1016 if (ret <= 0)
1017 {
1018 GTP_ERROR("[burn_fw_section]send burn cmd fail.");
1019 return FAIL;
1020 }
1021
1022 GTP_DEBUG("[burn_fw_section]Wait for the burn is complete......");
1023
1024 do
1025 {
1026 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1027
1028 if (ret <= 0)
1029 {
1030 GTP_ERROR("[burn_fw_section]Get burn state fail");
1031 return FAIL;
1032 }
1033
1034 msleep(10);
1035 //GTP_DEBUG("[burn_fw_section]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1036 }
1037 while (rd_buf[GTP_ADDR_LENGTH]);
1038
1039 //step8:select bank
1040 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
1041
1042 if (ret <= 0)
1043 {
1044 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
1045 return FAIL;
1046 }
1047
1048 //step9:enable accessing code
1049 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1050
1051 if (ret <= 0)
1052 {
1053 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
1054 return FAIL;
1055 }
1056
1057 //step10:recall 8k fw section
1058 ret = gup_recall_check(client, fw_section, start_addr, FW_SECTION_LENGTH);
1059
1060 if (FAIL == ret)
1061 {
1062 GTP_ERROR("[burn_fw_section]recall check 8k firmware fail.");
1063 return FAIL;
1064 }
1065
1066 //step11:disable accessing code
1067 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x00);
1068
1069 if (ret <= 0)
1070 {
1071 GTP_ERROR("[burn_fw_section]disable accessing code fail.");
1072 return FAIL;
1073 }
1074
1075 return SUCCESS;
1076 }
1077
1078 static u8 gup_burn_dsp_isp(struct i2c_client *client)
1079 {
1080 s32 ret = 0;
1081 u8 *fw_dsp_isp = NULL;
1082 u8 retry = 0;
1083
1084 GTP_INFO("[burn_dsp_isp]Begin burn dsp isp---->>");
1085
1086 //step1:alloc memory
1087 GTP_DEBUG("[burn_dsp_isp]step1:alloc memory");
1088
1089 while (retry++ < 5)
1090 {
1091 fw_dsp_isp = (u8 *)kzalloc(FW_DSP_ISP_LENGTH, GFP_KERNEL);
1092
1093 if (fw_dsp_isp == NULL)
1094 {
1095 continue;
1096 }
1097 else
1098 {
1099 GTP_INFO("[burn_dsp_isp]Alloc %dk byte memory success.", (FW_DSP_ISP_LENGTH / 1024));
1100 break;
1101 }
1102 }
1103
1104 if (retry >= 5)
1105 {
1106 GTP_ERROR("[burn_dsp_isp]Alloc memory fail,exit.");
1107 return FAIL;
1108 }
1109
1110 //step2:load dsp isp file data
1111 GTP_DEBUG("[burn_dsp_isp]step2:load dsp isp file data");
1112 ret = gup_load_section_file(fw_dsp_isp, (4 * FW_SECTION_LENGTH + FW_DSP_LENGTH + FW_BOOT_LENGTH), FW_DSP_ISP_LENGTH);
1113
1114 if (FAIL == ret)
1115 {
1116 GTP_ERROR("[burn_dsp_isp]load firmware dsp_isp fail.");
1117 goto exit_burn_dsp_isp;
1118 }
1119
1120 //step3:disable wdt,clear cache enable
1121 GTP_DEBUG("[burn_dsp_isp]step3:disable wdt,clear cache enable");
1122 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
1123
1124 if (ret <= 0)
1125 {
1126 GTP_ERROR("[burn_dsp_isp]disable wdt fail.");
1127 ret = FAIL;
1128 goto exit_burn_dsp_isp;
1129 }
1130
1131 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
1132
1133 if (ret <= 0)
1134 {
1135 GTP_ERROR("[burn_dsp_isp]clear cache enable fail.");
1136 ret = FAIL;
1137 goto exit_burn_dsp_isp;
1138 }
1139
1140 //step4:hold ss51 & dsp
1141 GTP_DEBUG("[burn_dsp_isp]step4:hold ss51 & dsp");
1142 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1143
1144 if (ret <= 0)
1145 {
1146 GTP_ERROR("[burn_dsp_isp]hold ss51 & dsp fail.");
1147 ret = FAIL;
1148 goto exit_burn_dsp_isp;
1149 }
1150
1151 //step5:set boot from sram
1152 GTP_DEBUG("[burn_dsp_isp]step5:set boot from sram");
1153 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
1154
1155 if (ret <= 0)
1156 {
1157 GTP_ERROR("[burn_dsp_isp]set boot from sram fail.");
1158 ret = FAIL;
1159 goto exit_burn_dsp_isp;
1160 }
1161
1162 //step6:software reboot
1163 GTP_DEBUG("[burn_dsp_isp]step6:software reboot");
1164 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
1165
1166 if (ret <= 0)
1167 {
1168 GTP_ERROR("[burn_dsp_isp]software reboot fail.");
1169 ret = FAIL;
1170 goto exit_burn_dsp_isp;
1171 }
1172
1173 //step7:select bank2
1174 GTP_DEBUG("[burn_dsp_isp]step7:select bank2");
1175 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
1176
1177 if (ret <= 0)
1178 {
1179 GTP_ERROR("[burn_dsp_isp]select bank2 fail.");
1180 ret = FAIL;
1181 goto exit_burn_dsp_isp;
1182 }
1183
1184 //step8:enable accessing code
1185 GTP_DEBUG("[burn_dsp_isp]step8:enable accessing code");
1186 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1187
1188 if (ret <= 0)
1189 {
1190 GTP_ERROR("[burn_dsp_isp]enable accessing code fail.");
1191 ret = FAIL;
1192 goto exit_burn_dsp_isp;
1193 }
1194
1195 //step9:burn 4k dsp_isp
1196 GTP_DEBUG("[burn_dsp_isp]step9:burn 4k dsp_isp");
1197 ret = gup_burn_proc(client, fw_dsp_isp, 0xC000, FW_DSP_ISP_LENGTH);
1198
1199 if (FAIL == ret)
1200 {
1201 GTP_ERROR("[burn_dsp_isp]burn dsp_isp fail.");
1202 goto exit_burn_dsp_isp;
1203 }
1204
1205 //step10:set scramble
1206 GTP_DEBUG("[burn_dsp_isp]step10:set scramble");
1207 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1208
1209 if (ret <= 0)
1210 {
1211 GTP_ERROR("[burn_dsp_isp]set scramble fail.");
1212 ret = FAIL;
1213 goto exit_burn_dsp_isp;
1214 }
1215
1216 ret = SUCCESS;
1217
1218 exit_burn_dsp_isp:
1219 kfree(fw_dsp_isp);
1220 return ret;
1221 }
1222
1223 static u8 gup_burn_fw_ss51(struct i2c_client *client)
1224 {
1225 u8 *fw_ss51 = NULL;
1226 u8 retry = 0;
1227 s32 ret = 0;
1228
1229 GTP_INFO("[burn_fw_ss51]Begin burn ss51 firmware---->>");
1230
1231 //step1:alloc memory
1232 GTP_DEBUG("[burn_fw_ss51]step1:alloc memory");
1233
1234 while (retry++ < 5)
1235 {
1236 fw_ss51 = (u8 *)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
1237
1238 if (fw_ss51 == NULL)
1239 {
1240 continue;
1241 }
1242 else
1243 {
1244 GTP_INFO("[burn_fw_ss51]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1245 break;
1246 }
1247 }
1248
1249 if (retry >= 5)
1250 {
1251 GTP_ERROR("[burn_fw_ss51]Alloc memory fail,exit.");
1252 return FAIL;
1253 }
1254
1255 //step2:load ss51 firmware section 1 file data
1256 GTP_DEBUG("[burn_fw_ss51]step2:load ss51 firmware section 1 file data");
1257 ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH);
1258
1259 if (FAIL == ret)
1260 {
1261 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 1 fail.");
1262 goto exit_burn_fw_ss51;
1263 }
1264
1265 //step3:clear control flag
1266 GTP_DEBUG("[burn_fw_ss51]step3:clear control flag");
1267 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
1268
1269 if (ret <= 0)
1270 {
1271 GTP_ERROR("[burn_fw_ss51]clear control flag fail.");
1272 ret = FAIL;
1273 goto exit_burn_fw_ss51;
1274 }
1275
1276 //step4:burn ss51 firmware section 1
1277 GTP_DEBUG("[burn_fw_ss51]step4:burn ss51 firmware section 1");
1278 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
1279
1280 if (FAIL == ret)
1281 {
1282 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 1 fail.");
1283 goto exit_burn_fw_ss51;
1284 }
1285
1286 //step5:load ss51 firmware section 2 file data
1287 GTP_DEBUG("[burn_fw_ss51]step5:load ss51 firmware section 2 file data");
1288 ret = gup_load_section_file(fw_ss51, FW_SECTION_LENGTH, FW_SECTION_LENGTH);
1289
1290 if (FAIL == ret)
1291 {
1292 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 2 fail.");
1293 goto exit_burn_fw_ss51;
1294 }
1295
1296 //step6:burn ss51 firmware section 2
1297 GTP_DEBUG("[burn_fw_ss51]step6:burn ss51 firmware section 2");
1298 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x02);
1299
1300 if (FAIL == ret)
1301 {
1302 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 2 fail.");
1303 goto exit_burn_fw_ss51;
1304 }
1305
1306 //step7:load ss51 firmware section 3 file data
1307 GTP_DEBUG("[burn_fw_ss51]step7:load ss51 firmware section 3 file data");
1308 ret = gup_load_section_file(fw_ss51, 2 * FW_SECTION_LENGTH, FW_SECTION_LENGTH);
1309
1310 if (FAIL == ret)
1311 {
1312 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 3 fail.");
1313 goto exit_burn_fw_ss51;
1314 }
1315
1316 //step8:burn ss51 firmware section 3
1317 GTP_DEBUG("[burn_fw_ss51]step8:burn ss51 firmware section 3");
1318 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x13);
1319
1320 if (FAIL == ret)
1321 {
1322 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 3 fail.");
1323 goto exit_burn_fw_ss51;
1324 }
1325
1326 //step9:load ss51 firmware section 4 file data
1327 GTP_DEBUG("[burn_fw_ss51]step9:load ss51 firmware section 4 file data");
1328 ret = gup_load_section_file(fw_ss51, 3 * FW_SECTION_LENGTH, FW_SECTION_LENGTH);
1329
1330 if (FAIL == ret)
1331 {
1332 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 4 fail.");
1333 goto exit_burn_fw_ss51;
1334 }
1335
1336 //step10:burn ss51 firmware section 4
1337 GTP_DEBUG("[burn_fw_ss51]step10:burn ss51 firmware section 4");
1338 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x14);
1339
1340 if (FAIL == ret)
1341 {
1342 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 4 fail.");
1343 goto exit_burn_fw_ss51;
1344 }
1345
1346 ret = SUCCESS;
1347
1348 exit_burn_fw_ss51:
1349 kfree(fw_ss51);
1350 return ret;
1351 }
1352
1353 static u8 gup_burn_fw_dsp(struct i2c_client *client)
1354 {
1355 s32 ret = 0;
1356 u8 *fw_dsp = NULL;
1357 u8 retry = 0;
1358 u8 rd_buf[5];
1359
1360 GTP_INFO("[burn_fw_dsp]Begin burn dsp firmware---->>");
1361 //step1:alloc memory
1362 GTP_DEBUG("[burn_fw_dsp]step1:alloc memory");
1363
1364 while (retry++ < 5)
1365 {
1366 fw_dsp = (u8 *)kzalloc(FW_DSP_LENGTH, GFP_KERNEL);
1367
1368 if (fw_dsp == NULL)
1369 {
1370 continue;
1371 }
1372 else
1373 {
1374 GTP_INFO("[burn_fw_dsp]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1375 break;
1376 }
1377 }
1378
1379 if (retry >= 5)
1380 {
1381 GTP_ERROR("[burn_fw_dsp]Alloc memory fail,exit.");
1382 return FAIL;
1383 }
1384
1385 //step2:load firmware dsp
1386 GTP_DEBUG("[burn_fw_dsp]step2:load firmware dsp");
1387 ret = gup_load_section_file(fw_dsp, 4 * FW_SECTION_LENGTH, FW_DSP_LENGTH);
1388
1389 if (FAIL == ret)
1390 {
1391 GTP_ERROR("[burn_fw_dsp]load firmware dsp fail.");
1392 goto exit_burn_fw_dsp;
1393 }
1394
1395 //step3:select bank3
1396 GTP_DEBUG("[burn_fw_dsp]step3:select bank3");
1397 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1398
1399 if (ret <= 0)
1400 {
1401 GTP_ERROR("[burn_fw_dsp]select bank3 fail.");
1402 ret = FAIL;
1403 goto exit_burn_fw_dsp;
1404 }
1405
1406 //step4:hold ss51 & dsp
1407 GTP_DEBUG("[burn_fw_dsp]step4:hold ss51 & dsp");
1408 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1409
1410 if (ret <= 0)
1411 {
1412 GTP_ERROR("[burn_fw_dsp]hold ss51 & dsp fail.");
1413 ret = FAIL;
1414 goto exit_burn_fw_dsp;
1415 }
1416
1417 //step5:set scramble
1418 GTP_DEBUG("[burn_fw_dsp]step5:set scramble");
1419 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1420
1421 if (ret <= 0)
1422 {
1423 GTP_ERROR("[burn_fw_dsp]set scramble fail.");
1424 ret = FAIL;
1425 goto exit_burn_fw_dsp;
1426 }
1427
1428 //step6:release ss51 & dsp
1429 GTP_DEBUG("[burn_fw_dsp]step6:release ss51 & dsp");
1430 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121212
1431
1432 if (ret <= 0)
1433 {
1434 GTP_ERROR("[burn_fw_dsp]release ss51 & dsp fail.");
1435 ret = FAIL;
1436 goto exit_burn_fw_dsp;
1437 }
1438
1439 //must delay
1440 msleep(1);
1441
1442 //step7:burn 4k dsp firmware
1443 GTP_DEBUG("[burn_fw_dsp]step7:burn 4k dsp firmware");
1444 ret = gup_burn_proc(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1445
1446 if (FAIL == ret)
1447 {
1448 GTP_ERROR("[burn_fw_dsp]burn fw_section fail.");
1449 goto exit_burn_fw_dsp;
1450 }
1451
1452 //step8:send burn cmd to move data to flash from sram
1453 GTP_DEBUG("[burn_fw_dsp]step8:send burn cmd to move data to flash from sram");
1454 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x05);
1455
1456 if (ret <= 0)
1457 {
1458 GTP_ERROR("[burn_fw_dsp]send burn cmd fail.");
1459 goto exit_burn_fw_dsp;
1460 }
1461
1462 GTP_DEBUG("[burn_fw_dsp]Wait for the burn is complete......");
1463
1464 do
1465 {
1466 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1467
1468 if (ret <= 0)
1469 {
1470 GTP_ERROR("[burn_fw_dsp]Get burn state fail");
1471 goto exit_burn_fw_dsp;
1472 }
1473
1474 msleep(10);
1475 //GTP_DEBUG("[burn_fw_dsp]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1476 }
1477 while (rd_buf[GTP_ADDR_LENGTH]);
1478
1479 //step9:recall check 4k dsp firmware
1480 GTP_DEBUG("[burn_fw_dsp]step9:recall check 4k dsp firmware");
1481 ret = gup_recall_check(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1482
1483 if (FAIL == ret)
1484 {
1485 GTP_ERROR("[burn_fw_dsp]recall check 4k dsp firmware fail.");
1486 goto exit_burn_fw_dsp;
1487 }
1488
1489 ret = SUCCESS;
1490
1491 exit_burn_fw_dsp:
1492 kfree(fw_dsp);
1493 return ret;
1494 }
1495
1496 static u8 gup_burn_fw_boot(struct i2c_client *client)
1497 {
1498 s32 ret = 0;
1499 u8 *fw_boot = NULL;
1500 u8 retry = 0;
1501 u8 rd_buf[5];
1502
1503 GTP_INFO("[burn_fw_boot]Begin burn bootloader firmware---->>");
1504
1505 //step1:Alloc memory
1506 GTP_DEBUG("[burn_fw_boot]step1:Alloc memory");
1507
1508 while (retry++ < 5)
1509 {
1510 fw_boot = (u8 *)kzalloc(FW_BOOT_LENGTH, GFP_KERNEL);
1511
1512 if (fw_boot == NULL)
1513 {
1514 continue;
1515 }
1516 else
1517 {
1518 GTP_INFO("[burn_fw_boot]Alloc %dk byte memory success.", (FW_BOOT_LENGTH / 1024));
1519 break;
1520 }
1521 }
1522
1523 if (retry >= 5)
1524 {
1525 GTP_ERROR("[burn_fw_boot]Alloc memory fail,exit.");
1526 return FAIL;
1527 }
1528
1529 //step2:load firmware bootloader
1530 GTP_DEBUG("[burn_fw_boot]step2:load firmware bootloader");
1531 ret = gup_load_section_file(fw_boot, (4 * FW_SECTION_LENGTH + FW_DSP_LENGTH), FW_BOOT_LENGTH);
1532
1533 if (FAIL == ret)
1534 {
1535 GTP_ERROR("[burn_fw_boot]load firmware dsp fail.");
1536 goto exit_burn_fw_boot;
1537 }
1538
1539 //step3:hold ss51 & dsp
1540 GTP_DEBUG("[burn_fw_boot]step3:hold ss51 & dsp");
1541 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1542
1543 if (ret <= 0)
1544 {
1545 GTP_ERROR("[burn_fw_boot]hold ss51 & dsp fail.");
1546 ret = FAIL;
1547 goto exit_burn_fw_boot;
1548 }
1549
1550 //step4:set scramble
1551 GTP_DEBUG("[burn_fw_boot]step4:set scramble");
1552 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1553
1554 if (ret <= 0)
1555 {
1556 GTP_ERROR("[burn_fw_boot]set scramble fail.");
1557 ret = FAIL;
1558 goto exit_burn_fw_boot;
1559 }
1560
1561 //step5:release ss51 & dsp
1562 GTP_DEBUG("[burn_fw_boot]step5:release ss51 & dsp");
1563 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121212
1564
1565 if (ret <= 0)
1566 {
1567 GTP_ERROR("[burn_fw_boot]release ss51 & dsp fail.");
1568 ret = FAIL;
1569 goto exit_burn_fw_boot;
1570 }
1571
1572 //must delay
1573 msleep(1);
1574
1575 //step6:burn 2k bootloader firmware
1576 GTP_DEBUG("[burn_fw_boot]step6:burn 2k bootloader firmware");
1577 ret = gup_burn_proc(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1578
1579 if (FAIL == ret)
1580 {
1581 GTP_ERROR("[burn_fw_boot]burn fw_section fail.");
1582 goto exit_burn_fw_boot;
1583 }
1584
1585 //step7:send burn cmd to move data to flash from sram
1586 GTP_DEBUG("[burn_fw_boot]step7:send burn cmd to move data to flash from sram");
1587 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x06);
1588
1589 if (ret <= 0)
1590 {
1591 GTP_ERROR("[burn_fw_boot]send burn cmd fail.");
1592 goto exit_burn_fw_boot;
1593 }
1594
1595 GTP_DEBUG("[burn_fw_boot]Wait for the burn is complete......");
1596
1597 do
1598 {
1599 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1600
1601 if (ret <= 0)
1602 {
1603 GTP_ERROR("[burn_fw_boot]Get burn state fail");
1604 goto exit_burn_fw_boot;
1605 }
1606
1607 msleep(10);
1608 //GTP_DEBUG("[burn_fw_boot]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1609 }
1610 while (rd_buf[GTP_ADDR_LENGTH]);
1611
1612 //step8:recall check 2k bootloader firmware
1613 GTP_DEBUG("[burn_fw_boot]step8:recall check 2k bootloader firmware");
1614 ret = gup_recall_check(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1615
1616 if (FAIL == ret)
1617 {
1618 GTP_ERROR("[burn_fw_boot]recall check 4k dsp firmware fail.");
1619 goto exit_burn_fw_boot;
1620 }
1621
1622 //step9:enable download DSP code
1623 GTP_DEBUG("[burn_fw_boot]step9:enable download DSP code ");
1624 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x99);
1625
1626 if (ret <= 0)
1627 {
1628 GTP_ERROR("[burn_fw_boot]enable download DSP code fail.");
1629 ret = FAIL;
1630 goto exit_burn_fw_boot;
1631 }
1632
1633 //step10:release ss51 & hold dsp
1634 GTP_DEBUG("[burn_fw_boot]step10:release ss51 & hold dsp");
1635 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x08);
1636
1637 if (ret <= 0)
1638 {
1639 GTP_ERROR("[burn_fw_boot]release ss51 & hold dsp fail.");
1640 ret = FAIL;
1641 goto exit_burn_fw_boot;
1642 }
1643
1644 ret = SUCCESS;
1645
1646 exit_burn_fw_boot:
1647 kfree(fw_boot);
1648 return ret;
1649 }
1650
1651 s32 gup_update_proc(void *dir)
1652 {
1653 s32 ret = 0;
1654 u8 retry = 0;
1655 s32 update_ret = FAIL;
1656 st_fw_head fw_head;
1657
1658 GTP_INFO("[update_proc]Begin update ......");
1659
1660 #if GTP_AUTO_UPDATE || defined(SELF_APK_UPGRADE)
1661 if (1 == searching_file)
1662 {
1663 u8 timeout = 0;
1664 searching_file = 0; // exit .bin update file searching
1665 GTP_INFO("Exiting searching file for auto update.");
1666 while ((show_len != 200) && (show_len != 100) && (timeout++ < 150)) // wait for auto update quitted completely
1667 {
1668 msleep(100);
1669 }
1670 }
1671 #endif
1672
1673 show_len = 1;
1674 total_len = 100;
1675
1676 #if GTP_COMPATIBLE_MODE
1677 if (CHIP_TYPE_GT9F == gtp_chip_type)
1678 {
1679 return gup_fw_download_proc(dir, GTP_FL_FW_BURN);
1680 }
1681 #endif
1682 ret = gup_check_update_file(i2c_client_point, &fw_head, (u8 *)dir); //20121212
1683
1684 if (FAIL == ret)
1685 {
1686 GTP_ERROR("[update_proc]check update file fail.");
1687 goto file_fail;
1688 }
1689
1690 //gtp_reset_guitar(i2c_client_point, 20);
1691 ret = gup_get_ic_fw_msg(i2c_client_point);
1692
1693 if (FAIL == ret)
1694 {
1695 GTP_ERROR("[update_proc]get ic message fail.");
1696 goto file_fail;
1697 }
1698
1699 ret = gup_enter_update_judge(&fw_head); //20121212
1700
1701 if (FAIL == ret)
1702 {
1703 GTP_ERROR("[update_proc]Check *.bin file fail.");
1704 goto file_fail;
1705 }
1706
1707 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
1708 #if GTP_ESD_PROTECT
1709 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
1710 #endif
1711 ret = gup_enter_update_mode(i2c_client_point);
1712
1713 if (FAIL == ret)
1714 {
1715 GTP_ERROR("[update_proc]enter update mode fail.");
1716 goto update_fail;
1717 }
1718
1719 while (retry++ < 5)
1720 {
1721 show_len = 10;
1722 total_len = 100;
1723 ret = gup_burn_dsp_isp(i2c_client_point);
1724
1725 if (FAIL == ret)
1726 {
1727 GTP_ERROR("[update_proc]burn dsp isp fail.");
1728 continue;
1729 }
1730
1731 show_len += 10;
1732 ret = gup_burn_fw_ss51(i2c_client_point);
1733
1734 if (FAIL == ret)
1735 {
1736 GTP_ERROR("[update_proc]burn ss51 firmware fail.");
1737 continue;
1738 }
1739
1740 show_len += 40;
1741 ret = gup_burn_fw_dsp(i2c_client_point);
1742
1743 if (FAIL == ret)
1744 {
1745 GTP_ERROR("[update_proc]burn dsp firmware fail.");
1746 continue;
1747 }
1748
1749 show_len += 20;
1750 ret = gup_burn_fw_boot(i2c_client_point);
1751 if (FAIL == ret)
1752 {
1753 GTP_ERROR("[update_proc]burn bootloader firmware fail.");
1754 continue;
1755 }
1756
1757 show_len += 10;
1758 GTP_INFO("[update_proc]UPDATE SUCCESS.");
1759 break;
1760 }
1761
1762 if (retry >= 5)
1763 {
1764 GTP_ERROR("[update_proc]retry timeout,UPDATE FAIL.");
1765 update_ret = FAIL;
1766 }
1767 else
1768 {
1769 update_ret = SUCCESS;
1770 }
1771
1772 update_fail:
1773 if (got_file_flag & BIN_FILE_READY)
1774 {
1775 if (update_msg.old_fs)
1776 {
1777 set_fs(update_msg.old_fs);
1778 }
1779 }
1780 GTP_DEBUG("[update_proc]leave update mode.");
1781 gup_leave_update_mode();
1782
1783 if (SUCCESS == update_ret)
1784 {
1785 GTP_DEBUG("[update_proc]send config.");
1786 ret = gtp_send_cfg(i2c_client_point);
1787 if (ret < 0)
1788 {
1789 GTP_ERROR("[update_proc]send config fail.");
1790 }
1791 }
1792
1793 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
1794 #if GTP_ESD_PROTECT
1795 gtp_esd_switch(i2c_client_point, SWITCH_ON);
1796 #endif
1797
1798 file_fail:
1799
1800 _CLOSE_FILE(update_msg.file);
1801
1802 #if (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE && GTP_AUTO_UPDATE_CFG)
1803 if (NULL == dir)
1804 {
1805 gup_search_file(AUTO_SEARCH_CFG);
1806 if (got_file_flag & CFG_FILE_READY)
1807 {
1808 ret = gup_update_config(i2c_client_point);
1809 if (FAIL == ret)
1810 {
1811 GTP_ERROR("Update config failed!");
1812 }
1813 }
1814 }
1815 #endif
1816
1817 total_len = 100;
1818 if (SUCCESS == update_ret)
1819 {
1820 show_len = 100;
1821 return SUCCESS;
1822 }
1823 else
1824 {
1825 show_len = 200;
1826 return FAIL;
1827 }
1828 }
1829
1830 u8 gup_init_update_proc(struct i2c_client *client)
1831 {
1832 struct task_struct *thread = NULL;
1833
1834 GTP_INFO("Ready to run auto update thread");
1835
1836 #if GTP_COMPATIBLE_MODE
1837 if (CHIP_TYPE_GT9F == gtp_chip_type)
1838 {
1839 thread = kthread_run(gup_update_proc, "update", "fl_auto_update");
1840 }
1841 else
1842 #endif
1843 {
1844 thread = kthread_run(gup_update_proc, (void *)NULL, "guitar_update");
1845 }
1846 if (IS_ERR(thread))
1847 {
1848 GTP_ERROR("Failed to create update thread.\n");
1849 return -1;
1850 }
1851
1852 return 0;
1853 }
1854
1855
1856 //******************* For GT9XXF Start ********************//
1857
1858 #define FL_UPDATE_PATH "/data/_fl_update_.bin"
1859 #define FL_UPDATE_PATH_SD "/sdcard/_fl_update_.bin"
1860
1861 #define GUP_FW_CHK_SIZE 256
1862 #define MAX_CHECK_TIMES 128 // max: 2 * (16 * 1024) / 256 = 128
1863
1864 //for clk cal
1865 #define PULSE_LENGTH (200)
1866 #define INIT_CLK_DAC (50)
1867 #define MAX_CLK_DAC (120)
1868 #define CLK_AVG_TIME (1)
1869 #define MILLION 1000000
1870
1871 #define _wRW_MISCTL__RG_DMY 0x4282
1872 #define _bRW_MISCTL__RG_OSC_CALIB 0x4268
1873 #define _fRW_MISCTL__GIO0 0x41e9
1874 #define _fRW_MISCTL__GIO1 0x41ed
1875 #define _fRW_MISCTL__GIO2 0x41f1
1876 #define _fRW_MISCTL__GIO3 0x41f5
1877 #define _fRW_MISCTL__GIO4 0x41f9
1878 #define _fRW_MISCTL__GIO5 0x41fd
1879 #define _fRW_MISCTL__GIO6 0x4201
1880 #define _fRW_MISCTL__GIO7 0x4205
1881 #define _fRW_MISCTL__GIO8 0x4209
1882 #define _fRW_MISCTL__GIO9 0x420d
1883 #define _fRW_MISCTL__MEA 0x41a0
1884 #define _bRW_MISCTL__MEA_MODE 0x41a1
1885 #define _wRW_MISCTL__MEA_MAX_NUM 0x41a4
1886 #define _dRO_MISCTL__MEA_VAL 0x41b0
1887 #define _bRW_MISCTL__MEA_SRCSEL 0x41a3
1888 #define _bRO_MISCTL__MEA_RDY 0x41a8
1889 #define _rRW_MISCTL__ANA_RXADC_B0_ 0x4250
1890 #define _bRW_MISCTL__RG_LDO_A18_PWD 0x426f
1891 #define _bRW_MISCTL__RG_BG_PWD 0x426a
1892 #define _bRW_MISCTL__RG_CLKGEN_PWD 0x4269
1893 #define _fRW_MISCTL__RG_RXADC_PWD 0x426a
1894 #define _bRW_MISCTL__OSC_CK_SEL 0x4030
1895 #define _rRW_MISCTL_RG_DMY83 0x4283
1896 #define _rRW_MISCTL__GIO1CTL_B2_ 0x41ee
1897 #define _rRW_MISCTL__GIO1CTL_B1_ 0x41ed
1898
1899 #if GTP_COMPATIBLE_MODE
1900
1901 u8 gup_check_fs_mounted(char *path_name)
1902 {
1903 struct path root_path;
1904 struct path path;
1905 int err;
1906 err = kern_path("/", LOOKUP_FOLLOW, &root_path);
1907
1908 if (err)
1909 return FAIL;
1910
1911 err = kern_path(path_name, LOOKUP_FOLLOW, &path);
1912
1913 if (err)
1914 return FAIL;
1915
1916 if (path.mnt->mnt_sb == root_path.mnt->mnt_sb)
1917 {
1918 //-- not mounted
1919 return FAIL;
1920 }
1921 else
1922 {
1923 return SUCCESS;
1924 }
1925 }
1926
1927 s32 gup_hold_ss51_dsp(struct i2c_client *client)
1928 {
1929 s32 ret = -1;
1930 s32 retry = 0;
1931 u8 rd_buf[3];
1932
1933 while(retry++ < 200)
1934 {
1935 // step4:Hold ss51 & dsp
1936 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1937 if(ret <= 0)
1938 {
1939 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
1940 continue;
1941 }
1942
1943 // step5:Confirm hold
1944 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
1945 if (ret <= 0)
1946 {
1947 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
1948 continue;
1949 }
1950 if (0x0C == rd_buf[GTP_ADDR_LENGTH])
1951 {
1952 GTP_DEBUG("[enter_update_mode]Hold ss51 & dsp confirm SUCCESS");
1953 break;
1954 }
1955 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
1956 }
1957 if(retry >= 200)
1958 {
1959 GTP_ERROR("Enter update Hold ss51 failed.");
1960 return FAIL;
1961 }
1962 //DSP_CK and DSP_ALU_CK PowerOn
1963 ret = gup_set_ic_msg(client, 0x4010, 0x00);
1964 if (ret <= 0)
1965 {
1966 GTP_ERROR("[enter_update_mode]DSP_CK and DSP_ALU_CK PowerOn fail.");
1967 return FAIL;
1968 }
1969
1970 //disable wdt
1971 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
1972
1973 if (ret <= 0)
1974 {
1975 GTP_ERROR("[enter_update_mode]disable wdt fail.");
1976 return FAIL;
1977 }
1978
1979 //clear cache enable
1980 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
1981
1982 if (ret <= 0)
1983 {
1984 GTP_ERROR("[enter_update_mode]clear cache enable fail.");
1985 return FAIL;
1986 }
1987
1988 //set boot from sram
1989 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
1990
1991 if (ret <= 0)
1992 {
1993 GTP_ERROR("[enter_update_mode]set boot from sram fail.");
1994 return FAIL;
1995 }
1996
1997 //software reboot
1998 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
1999 if (ret <= 0)
2000 {
2001 GTP_ERROR("[enter_update_mode]software reboot fail.");
2002 return FAIL;
2003 }
2004
2005 return SUCCESS;
2006 }
2007
2008 s32 gup_enter_update_mode_fl(struct i2c_client *client)
2009 {
2010 s32 ret = -1;
2011 //s32 retry = 0;
2012 //u8 rd_buf[3];
2013
2014 //step1:RST output low last at least 2ms
2015 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
2016 msleep(2);
2017
2018 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
2019 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
2020 msleep(2);
2021
2022 //step3:RST output high reset guitar
2023 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
2024
2025 msleep(5);
2026
2027 //select addr & hold ss51_dsp
2028 ret = gup_hold_ss51_dsp(client);
2029 if (ret <= 0)
2030 {
2031 GTP_ERROR("[enter_update_mode]hold ss51 & dsp failed.");
2032 return FAIL;
2033 }
2034
2035 //clear control flag
2036 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
2037
2038 if (ret <= 0)
2039 {
2040 GTP_ERROR("[enter_update_mode]clear control flag fail.");
2041 return FAIL;
2042 }
2043
2044 //set scramble
2045 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
2046
2047 if (ret <= 0)
2048 {
2049 GTP_ERROR("[enter_update_mode]set scramble fail.");
2050 return FAIL;
2051 }
2052
2053 //enable accessing code
2054 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
2055
2056 if (ret <= 0)
2057 {
2058 GTP_ERROR("[enter_update_mode]enable accessing code fail.");
2059 return FAIL;
2060 }
2061
2062 return SUCCESS;
2063 }
2064
2065
2066 static s32 gup_prepare_fl_fw(char *path, st_fw_head *fw_head)
2067 {
2068 s32 i = 0;
2069 s32 ret = 0;
2070 s32 timeout = 0;
2071
2072 if (!memcmp(path, "update", 6))
2073 {
2074 GTP_INFO("Search for Flashless firmware file to update");
2075 searching_file = 1;
2076 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
2077 {
2078 if (0 == searching_file)
2079 {
2080 GTP_INFO("Force terminate searching file auto update.");
2081 return FAIL;
2082 }
2083 update_msg.file = filp_open(FL_UPDATE_PATH, O_RDONLY, 0);
2084 if (IS_ERR(update_msg.file))
2085 {
2086 update_msg.file = filp_open(FL_UPDATE_PATH_SD, O_RDONLY, 0);
2087 if (IS_ERR(update_msg.file))
2088 {
2089 msleep(2000);
2090 continue;
2091 }
2092 else
2093 {
2094 path = FL_UPDATE_PATH_SD;
2095 break;
2096 }
2097 }
2098 else
2099 {
2100 path = FL_UPDATE_PATH;
2101 break;
2102 }
2103 }
2104 searching_file = 0;
2105 if (i >= 50)
2106 {
2107 GTP_ERROR("Search timeout, update aborted");
2108 return FAIL;
2109 }
2110 else
2111 {
2112 _CLOSE_FILE(update_msg.file);
2113 }
2114 while (rqst_processing && (timeout++ < 15))
2115 {
2116 GTP_INFO("wait for request process completed!");
2117 msleep(1000);
2118 }
2119 }
2120
2121 GTP_INFO("Firmware update file path: %s", path);
2122 update_msg.file = filp_open(path, O_RDONLY, 0);
2123
2124 if (IS_ERR(update_msg.file))
2125 {
2126 GTP_ERROR("Open update file(%s) error!", path);
2127 return FAIL;
2128 }
2129
2130 ret = gup_get_ic_fw_msg(i2c_client_point);
2131 if (FAIL == ret)
2132 {
2133 GTP_ERROR("failed to get ic firmware info");
2134 _CLOSE_FILE(update_msg.file);
2135 return FAIL;
2136 }
2137
2138 update_msg.old_fs = get_fs();
2139 set_fs(KERNEL_DS);
2140 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2141 update_msg.file->f_op->read(update_msg.file, (char*)fw_head, FW_HEAD_LENGTH, &update_msg.file->f_pos);
2142
2143 ret = gup_enter_update_judge(fw_head);
2144 if (FAIL == ret)
2145 {
2146 set_fs(update_msg.old_fs);
2147 _CLOSE_FILE(update_msg.file);
2148 return FAIL;
2149 }
2150
2151 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2152 //copy fw file to gtp_default_FW_fl array
2153 ret = update_msg.file->f_op->read(update_msg.file,
2154 (char*)gtp_default_FW_fl,
2155 FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH+FW_DSP_LENGTH,
2156 &update_msg.file->f_pos);
2157 if (ret < 0)
2158 {
2159 GTP_ERROR("Failed to read firmware data from %s, err-code: %d", path, ret);
2160 ret = FAIL;
2161 }
2162 else
2163 {
2164 ret = SUCCESS;
2165 }
2166 set_fs(update_msg.old_fs);
2167 _CLOSE_FILE(update_msg.file);
2168 return ret;
2169 }
2170
2171 static u8 gup_check_update_file_fl(struct i2c_client *client, st_fw_head *fw_head, char *path)
2172 {
2173 s32 i = 0;
2174 s32 fw_checksum = 0;
2175 s32 ret = 0;
2176
2177 if (NULL != path)
2178 {
2179 ret = gup_prepare_fl_fw(path, fw_head);
2180 if (ret == FAIL)
2181 {
2182 return FAIL;
2183 }
2184 }
2185 else
2186 {
2187 memcpy(fw_head, gtp_default_FW_fl, FW_HEAD_LENGTH);
2188 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
2189 GTP_INFO("FILE PID:%s", fw_head->pid);
2190 fw_head->vid = ((fw_head->vid & 0xFF00) >> 8) + ((fw_head->vid & 0x00FF) << 8);
2191 GTP_INFO("FILE VID:%04x", fw_head->vid);
2192 }
2193
2194 //check firmware legality
2195 fw_checksum = 0;
2196 for(i=FW_HEAD_LENGTH; i<FW_HEAD_LENGTH+FW_SECTION_LENGTH*4+FW_DSP_LENGTH; i+=2)
2197 {
2198 u16 temp;
2199
2200 //GTP_DEBUG("BUF[0]:%x", buf[0]);
2201 temp = (gtp_default_FW_fl[i]<<8) + gtp_default_FW_fl[i+1];
2202 fw_checksum += temp;
2203 }
2204
2205 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
2206 if(fw_checksum&0xFFFF)
2207 {
2208 GTP_ERROR("Illegal firmware file.");
2209 return FAIL;
2210 }
2211
2212 return SUCCESS;
2213 }
2214
2215
2216 static u8 gup_download_fw_ss51(struct i2c_client *client, u8 dwn_mode)
2217 {
2218 s32 ret = 0;
2219
2220 if(GTP_FL_FW_BURN == dwn_mode)
2221 {
2222 GTP_INFO("[download_fw_ss51]Begin download ss51 firmware---->>");
2223 }
2224 else
2225 {
2226 GTP_INFO("[download_fw_ss51]Begin check ss51 firmware----->>");
2227 }
2228 //step1:download FW section 1
2229 GTP_DEBUG("[download_fw_ss51]step1:download FW section 1");
2230 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x00);
2231
2232 if (ret <= 0)
2233 {
2234 GTP_ERROR("[download_fw_ss51]select bank0 fail.");
2235 ret = FAIL;
2236 goto exit_download_fw_ss51;
2237 }
2238
2239
2240 ret = i2c_write_bytes(client, 0xC000,
2241 &gtp_default_FW_fl[FW_HEAD_LENGTH], FW_DOWNLOAD_LENGTH); // write the first bank
2242
2243 if (ret == -1)
2244 {
2245 GTP_ERROR("[download_fw_ss51]download FW section 1 fail.");
2246 ret = FAIL;
2247 goto exit_download_fw_ss51;
2248 }
2249
2250
2251 if (GTP_FL_FW_BURN == dwn_mode)
2252 {
2253 ret = gup_check_and_repair(i2c_client_point,
2254 0xC000,
2255 &gtp_default_FW_fl[FW_HEAD_LENGTH],
2256 FW_DOWNLOAD_LENGTH);
2257 if(FAIL == ret)
2258 {
2259 GTP_ERROR("[download_fw_ss51]Checked FW section 1 fail.");
2260 goto exit_download_fw_ss51;
2261 }
2262 }
2263
2264 //step2:download FW section 2
2265 GTP_DEBUG("[download_fw_ss51]step2:download FW section 1");
2266 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x01);
2267
2268 if (ret <= 0)
2269 {
2270 GTP_ERROR("[download_fw_ss51]select bank1 fail.");
2271 ret = FAIL;
2272 goto exit_download_fw_ss51;
2273 }
2274
2275 ret = i2c_write_bytes(client, 0xC000, &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],FW_DOWNLOAD_LENGTH); // write the second bank
2276
2277 if (ret == -1)
2278 {
2279 GTP_ERROR("[download_fw_ss51]download FW section 2 fail.");
2280 ret = FAIL;
2281 goto exit_download_fw_ss51;
2282 }
2283
2284 if (GTP_FL_FW_BURN == dwn_mode)
2285 {
2286 ret = gup_check_and_repair(i2c_client_point,
2287 0xC000,
2288 &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],
2289 FW_DOWNLOAD_LENGTH);
2290
2291 if(FAIL == ret)
2292 {
2293 GTP_ERROR("[download_fw_ss51]Checked FW section 2 fail.");
2294 goto exit_download_fw_ss51;
2295 }
2296 }
2297 ret = SUCCESS;
2298
2299 exit_download_fw_ss51:
2300
2301 return ret;
2302 }
2303 #if (!GTP_SUPPORT_I2C_DMA)
2304 static s32 i2c_auto_read(struct i2c_client *client,u8 *rxbuf, int len)
2305 {
2306 u8 retry;
2307 u16 left = len;
2308 u16 offset = 0;
2309
2310 struct i2c_msg msg =
2311 {
2312 //.addr = ((client->addr &I2C_MASK_FLAG) | (I2C_ENEXT_FLAG)),
2313 .addr = ((client->addr &I2C_MASK_FLAG) | (I2C_PUSHPULL_FLAG)),
2314 .flags = I2C_M_RD,
2315 .timing = I2C_MASTER_CLOCK
2316 };
2317
2318 if(NULL == rxbuf)
2319 {
2320 return -1;
2321 }
2322
2323 while (left > 0)
2324 {
2325 msg.buf = &rxbuf[offset];
2326
2327 if (left > MAX_TRANSACTION_LENGTH)
2328 {
2329 msg.len = MAX_TRANSACTION_LENGTH;
2330 left -= MAX_TRANSACTION_LENGTH;
2331 offset += MAX_TRANSACTION_LENGTH;
2332 }
2333 else
2334 {
2335 msg.len = left;
2336 left = 0;
2337 }
2338
2339 retry = 0;
2340
2341 while (i2c_transfer(client->adapter, &msg, 1) != 1)
2342 {
2343 retry++;
2344
2345 if (retry == 20)
2346 {
2347 GTP_ERROR("I2C read 0x%X length=%d failed\n", offset, len);
2348 return -1;
2349 }
2350 }
2351 }
2352
2353 return 0;
2354 }
2355 #endif
2356 static u8 gup_check_and_repair(struct i2c_client *client, s32 chk_start_addr, u8 *target_fw, u32 chk_total_length)
2357 {
2358 s32 ret = 0;
2359 u32 chked_len = 0;
2360 u8 chked_times = 0;
2361 u32 chk_addr = 0;
2362 u8 chk_buf[GUP_FW_CHK_SIZE];
2363 u32 rd_size = 0;
2364 u8 flag_err = 0;
2365 s32 i = 0;
2366
2367 chk_addr = chk_start_addr;
2368 while((chked_times < MAX_CHECK_TIMES) && (chked_len < chk_total_length))
2369 {
2370 rd_size = chk_total_length - chked_len;
2371 if(rd_size >= GUP_FW_CHK_SIZE)
2372 {
2373 rd_size = GUP_FW_CHK_SIZE;
2374 }
2375 #if GTP_SUPPORT_I2C_DMA
2376 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
2377 #else
2378 if (!i)
2379 {
2380 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
2381 }
2382 else
2383 {
2384 ret = i2c_auto_read(client, chk_buf, rd_size);
2385 }
2386 #endif
2387
2388 if(-1 == ret)
2389 {
2390 GTP_ERROR("Read chk ram fw i2c error");
2391 chked_times++;
2392 continue;
2393 }
2394
2395 for(i=0; i<rd_size; i++)
2396 {
2397 if(chk_buf[i] != target_fw[i])
2398 {
2399 GTP_ERROR("Ram pos[0x%04x] checked failed,rewrite.", chk_addr + i);
2400 i2c_write_bytes(client, chk_addr+i, &target_fw[i], rd_size-i);
2401 flag_err = 1;
2402 i = 0;
2403 break;
2404 }
2405 }
2406
2407 if(!flag_err)
2408 {
2409 GTP_DEBUG("Ram pos[0x%04X] check pass!", chk_addr);
2410 chked_len += rd_size;
2411 target_fw += rd_size;
2412 chk_addr += rd_size;
2413 }
2414 else
2415 {
2416 flag_err = 0;
2417 chked_times++;
2418 }
2419 }
2420
2421 if(chked_times >= MAX_CHECK_TIMES)
2422 {
2423 GTP_ERROR("Ram data check failed.");
2424 return FAIL;
2425 }
2426 return SUCCESS;
2427 }
2428
2429 static u8 gup_download_fw_dsp(struct i2c_client *client, u8 dwn_mode)
2430 {
2431 s32 ret = 0;
2432
2433 if(GTP_FL_FW_BURN == dwn_mode)
2434 {
2435 GTP_INFO("[download_fw_dsp]Begin download dsp fw---->>");
2436 }
2437 else
2438 {
2439 GTP_INFO("[download_fw_dsp]Begin check dsp fw---->>");
2440 }
2441
2442 //step1:select bank2
2443 GTP_DEBUG("[download_fw_dsp]step1:select bank2");
2444 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
2445
2446 if (ret <= 0)
2447 {
2448 GTP_ERROR("[download_fw_dsp]select bank2 fail.");
2449 ret = FAIL;
2450 goto exit_download_fw_dsp;
2451 }
2452
2453 ret = i2c_write_bytes(client,
2454 0xC000,
2455 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
2456 FW_DSP_LENGTH); // write the second bank
2457 if (ret == -1)
2458 {
2459 GTP_ERROR("[download_fw_dsp]download FW dsp fail.");
2460 ret = FAIL;
2461 goto exit_download_fw_dsp;
2462 }
2463
2464 if (GTP_FL_FW_BURN == dwn_mode)
2465 {
2466 ret = gup_check_and_repair(client,
2467 0xC000,
2468 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
2469 FW_DSP_LENGTH);
2470
2471 if(FAIL == ret)
2472 {
2473 GTP_ERROR("[download_fw_dsp]Checked FW dsp fail.");
2474 goto exit_download_fw_dsp;
2475 }
2476
2477 }
2478 ret = SUCCESS;
2479
2480 exit_download_fw_dsp:
2481
2482 return ret;
2483 }
2484
2485 s32 gup_fw_download_proc(void *dir, u8 dwn_mode)
2486 {
2487 s32 ret = 0;
2488 u8 retry = 0;
2489 st_fw_head fw_head;
2490
2491 if(GTP_FL_FW_BURN == dwn_mode)
2492 {
2493 GTP_INFO("[fw_download_proc]Begin fw download ......");
2494 }
2495 else
2496 {
2497 GTP_INFO("[fw_download_proc]Begin fw check ......");
2498 }
2499 show_len = 0;
2500 total_len = 100;
2501
2502 ret = gup_check_update_file_fl(i2c_client_point, &fw_head, (char *)dir);
2503
2504 show_len = 10;
2505
2506 if (FAIL == ret)
2507 {
2508 GTP_ERROR("[fw_download_proc]check update file fail.");
2509 goto file_fail;
2510 }
2511
2512 if (!memcmp(fw_head.pid, "950", 3))
2513 {
2514 is_950 = 1;
2515 GTP_DEBUG("GT9XXF IC Type: gt950");
2516 }
2517 else
2518 {
2519 is_950 = 0;
2520 }
2521
2522 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
2523 if (NULL != dir)
2524 {
2525 #if GTP_ESD_PROTECT
2526 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
2527 #endif
2528 }
2529
2530 ret = gup_enter_update_mode_fl(i2c_client_point);
2531 show_len = 20;
2532
2533 if (FAIL == ret)
2534 {
2535 GTP_ERROR("[fw_download_proc]enter update mode fail.");
2536 goto download_fail;
2537 }
2538
2539 while (retry++ < 5)
2540 {
2541 ret = gup_download_fw_ss51(i2c_client_point, dwn_mode);
2542 show_len = 60;
2543 if (FAIL == ret)
2544 {
2545 GTP_ERROR("[fw_download_proc]burn ss51 firmware fail.");
2546 continue;
2547 }
2548
2549 ret = gup_download_fw_dsp(i2c_client_point, dwn_mode);
2550 show_len = 80;
2551 if (FAIL == ret)
2552 {
2553 GTP_ERROR("[fw_download_proc]burn dsp firmware fail.");
2554 continue;
2555 }
2556
2557 GTP_INFO("[fw_download_proc]UPDATE SUCCESS.");
2558 break;
2559 }
2560
2561 if (retry >= 5)
2562 {
2563 GTP_ERROR("[fw_download_proc]retry timeout,UPDATE FAIL.");
2564 goto download_fail;
2565 }
2566
2567 if (NULL != dir)
2568 {
2569 gtp_fw_startup(i2c_client_point);
2570 #if GTP_ESD_PROTECT
2571 gtp_esd_switch(i2c_client_point, SWITCH_ON);
2572 #endif
2573 }
2574 show_len = 100;
2575 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
2576 return SUCCESS;
2577
2578 download_fail:
2579 if (NULL != dir)
2580 {
2581 gtp_fw_startup(i2c_client_point);
2582 #if GTP_ESD_PROTECT
2583 gtp_esd_switch(i2c_client_point, SWITCH_ON);
2584 #endif
2585 }
2586
2587 file_fail:
2588 show_len = 200;
2589 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
2590 return FAIL;
2591 }
2592
2593
2594 static void gup_bit_write(s32 addr, s32 bit, s32 val)
2595 {
2596 u8 buf;
2597 i2c_read_bytes(i2c_client_point, addr, &buf, 1);
2598
2599 buf = (buf & (~((u8)1 << bit))) | ((u8)val << bit);
2600
2601 i2c_write_bytes(i2c_client_point, addr, &buf, 1);
2602 }
2603
2604 static void gup_clk_count_init(s32 bCh, s32 bCNT)
2605 {
2606 u8 buf;
2607
2608 //_fRW_MISCTL__MEA_EN = 0; //Frequency measure enable
2609 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
2610 //_fRW_MISCTL__MEA_CLR = 1; //Frequency measure clear
2611 gup_bit_write(_fRW_MISCTL__MEA, 1, 1);
2612 //_bRW_MISCTL__MEA_MODE = 0; //Pulse mode
2613 buf = 0;
2614 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_MODE, &buf, 1);
2615 //_bRW_MISCTL__MEA_SRCSEL = 8 + bCh; //From GIO1
2616 buf = 8 + bCh;
2617 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_SRCSEL, &buf, 1);
2618 //_wRW_MISCTL__MEA_MAX_NUM = bCNT; //Set the Measure Counts = 1
2619 buf = bCNT;
2620 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__MEA_MAX_NUM, &buf, 1);
2621 //_fRW_MISCTL__MEA_CLR = 0; //Frequency measure not clear
2622 gup_bit_write(_fRW_MISCTL__MEA, 1, 0);
2623 //_fRW_MISCTL__MEA_EN = 1;
2624 gup_bit_write(_fRW_MISCTL__MEA, 0, 1);
2625 }
2626
2627 static u32 gup_clk_count_get(void)
2628 {
2629 s32 ready = 0;
2630 s32 temp;
2631 s8 buf[4];
2632
2633 while ((ready == 0)) //Wait for measurement complete
2634 {
2635 i2c_read_bytes(i2c_client_point, _bRO_MISCTL__MEA_RDY, buf, 1);
2636 ready = buf[0];
2637 }
2638
2639 udelay(50);
2640
2641 //_fRW_MISCTL__MEA_EN = 0;
2642 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
2643 i2c_read_bytes(i2c_client_point, _dRO_MISCTL__MEA_VAL, buf, 4);
2644 GTP_INFO("Clk_count 0: %2X", buf[0]);
2645 GTP_INFO("Clk_count 1: %2X", buf[1]);
2646 GTP_INFO("Clk_count 2: %2X", buf[2]);
2647 GTP_INFO("Clk_count 3: %2X", buf[3]);
2648
2649 temp = (s32)buf[0] + ((s32)buf[1] << 8) + ((s32)buf[2] << 16) + ((s32)buf[3] << 24);
2650 GTP_INFO("Clk_count : %d", temp);
2651 return temp;
2652 }
2653 u8 gup_clk_dac_setting(int dac)
2654 {
2655 s8 buf1, buf2;
2656
2657 i2c_read_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
2658 i2c_read_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
2659
2660 buf1 = (buf1 & 0xFFCF) | ((dac & 0x03) << 4);
2661 buf2 = (dac >> 2) & 0x3f;
2662
2663 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
2664 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
2665
2666 return 0;
2667 }
2668
2669 static u8 gup_clk_calibration_pin_select(s32 bCh)
2670 {
2671 s32 i2c_addr;
2672
2673 switch (bCh)
2674 {
2675 case 0:
2676 i2c_addr = _fRW_MISCTL__GIO0;
2677 break;
2678
2679 case 1:
2680 i2c_addr = _fRW_MISCTL__GIO1;
2681 break;
2682
2683 case 2:
2684 i2c_addr = _fRW_MISCTL__GIO2;
2685 break;
2686
2687 case 3:
2688 i2c_addr = _fRW_MISCTL__GIO3;
2689 break;
2690
2691 case 4:
2692 i2c_addr = _fRW_MISCTL__GIO4;
2693 break;
2694
2695 case 5:
2696 i2c_addr = _fRW_MISCTL__GIO5;
2697 break;
2698
2699 case 6:
2700 i2c_addr = _fRW_MISCTL__GIO6;
2701 break;
2702
2703 case 7:
2704 i2c_addr = _fRW_MISCTL__GIO7;
2705 break;
2706
2707 case 8:
2708 i2c_addr = _fRW_MISCTL__GIO8;
2709 break;
2710
2711 case 9:
2712 i2c_addr = _fRW_MISCTL__GIO9;
2713 break;
2714 }
2715
2716 gup_bit_write(i2c_addr, 1, 0);
2717
2718 return 0;
2719 }
2720
2721 void gup_output_pulse(int t)
2722 {
2723 unsigned long flags;
2724 //s32 i;
2725
2726 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
2727 udelay(10);
2728
2729 local_irq_save(flags);
2730
2731 mt_set_gpio_out(GTP_INT_PORT, 1);
2732 udelay(50);
2733 mt_set_gpio_out(GTP_INT_PORT, 0);
2734 udelay(t - 50);
2735 mt_set_gpio_out(GTP_INT_PORT, 1);
2736
2737 local_irq_restore(flags);
2738
2739 udelay(20);
2740 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
2741 }
2742
2743 static void gup_sys_clk_init(void)
2744 {
2745 u8 buf;
2746
2747 //_fRW_MISCTL__RG_RXADC_CKMUX = 0;
2748 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 5, 0);
2749 //_bRW_MISCTL__RG_LDO_A18_PWD = 0; //DrvMISCTL_A18_PowerON
2750 buf = 0;
2751 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_LDO_A18_PWD, &buf, 1);
2752 //_bRW_MISCTL__RG_BG_PWD = 0; //DrvMISCTL_BG_PowerON
2753 buf = 0;
2754 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_BG_PWD, &buf, 1);
2755 //_bRW_MISCTL__RG_CLKGEN_PWD = 0; //DrvMISCTL_CLKGEN_PowerON
2756 buf = 0;
2757 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_CLKGEN_PWD, &buf, 1);
2758 //_fRW_MISCTL__RG_RXADC_PWD = 0; //DrvMISCTL_RX_ADC_PowerON
2759 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 0, 0);
2760 //_fRW_MISCTL__RG_RXADC_REF_PWD = 0; //DrvMISCTL_RX_ADCREF_PowerON
2761 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 1, 0);
2762 //gup_clk_dac_setting(60);
2763 //_bRW_MISCTL__OSC_CK_SEL = 1;;
2764 buf = 1;
2765 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__OSC_CK_SEL, &buf, 1);
2766 }
2767
2768 u8 gup_clk_calibration(void)
2769 {
2770 //u8 buf;
2771 //u8 trigger;
2772 s32 i;
2773 struct timeval start, end;
2774 s32 count;
2775 s32 count_ref;
2776 s32 sec;
2777 s32 usec;
2778 s32 ret = 0;
2779 //unsigned long flags;
2780
2781 //buf = 0x0C; // hold ss51 and dsp
2782 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
2783 ret = gup_hold_ss51_dsp(i2c_client_point);
2784 if (ret <= 0)
2785 {
2786 GTP_ERROR("[gup_clk_calibration]hold ss51 & dsp failed.");
2787 return FAIL;
2788 }
2789
2790 //_fRW_MISCTL__CLK_BIAS = 0; //disable clock bias
2791 gup_bit_write(_rRW_MISCTL_RG_DMY83, 7, 0);
2792
2793 //_fRW_MISCTL__GIO1_PU = 0; //set TOUCH INT PIN MODE as input
2794 gup_bit_write(_rRW_MISCTL__GIO1CTL_B2_, 0, 0);
2795
2796 //_fRW_MISCTL__GIO1_OE = 0; //set TOUCH INT PIN MODE as input
2797 gup_bit_write(_rRW_MISCTL__GIO1CTL_B1_, 1, 0);
2798
2799 //buf = 0x00;
2800 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
2801 //msleep(1000);
2802
2803 GTP_INFO("CLK calibration GO");
2804 gup_sys_clk_init();
2805 gup_clk_calibration_pin_select(1);//use GIO1 to do the calibration
2806
2807 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
2808
2809 for (i = INIT_CLK_DAC; i < MAX_CLK_DAC; i++)
2810 {
2811 if (tpd_halt)
2812 {
2813 i = 80; // if sleeping while calibrating main clock, set it default 80
2814 break;
2815 }
2816 GTP_INFO("CLK calibration DAC %d", i);
2817
2818 gup_clk_dac_setting(i);
2819 gup_clk_count_init(1, CLK_AVG_TIME);
2820
2821 #if 0
2822 gup_output_pulse(PULSE_LENGTH);
2823 count = gup_clk_count_get();
2824
2825 if (count > PULSE_LENGTH * 60)//60= 60Mhz * 1us
2826 {
2827 break;
2828 }
2829
2830 #else
2831 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
2832
2833 //local_irq_save(flags);
2834 do_gettimeofday(&start);
2835 mt_set_gpio_out(GTP_INT_PORT, 1);
2836 //local_irq_restore(flags);
2837
2838 msleep(1);
2839 mt_set_gpio_out(GTP_INT_PORT, 0);
2840 msleep(1);
2841
2842 //local_irq_save(flags);
2843 do_gettimeofday(&end);
2844 mt_set_gpio_out(GTP_INT_PORT, 1);
2845 //local_irq_restore(flags);
2846
2847 count = gup_clk_count_get();
2848 udelay(20);
2849 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
2850
2851 usec = end.tv_usec - start.tv_usec;
2852 sec = end.tv_sec - start.tv_sec;
2853 count_ref = 60 * (usec+ sec * MILLION);//60= 60Mhz * 1us
2854
2855 GTP_DEBUG("== time %d, %d, %d", sec, usec, count_ref);
2856
2857 if (count > count_ref)
2858 {
2859 GTP_DEBUG("== count_diff %d", count - count_ref);
2860 break;
2861 }
2862
2863 #endif
2864 }
2865
2866 //clk_dac = i;
2867
2868 //gtp_reset_guitar(i2c_client_point, 20);
2869
2870 #if 0//for debug
2871 //-- ouput clk to GPIO 4
2872 buf = 0x00;
2873 i2c_write_bytes(i2c_client_point, 0x41FA, &buf, 1);
2874 buf = 0x00;
2875 i2c_write_bytes(i2c_client_point, 0x4104, &buf, 1);
2876 buf = 0x00;
2877 i2c_write_bytes(i2c_client_point, 0x4105, &buf, 1);
2878 buf = 0x00;
2879 i2c_write_bytes(i2c_client_point, 0x4106, &buf, 1);
2880 buf = 0x01;
2881 i2c_write_bytes(i2c_client_point, 0x4107, &buf, 1);
2882 buf = 0x06;
2883 i2c_write_bytes(i2c_client_point, 0x41F8, &buf, 1);
2884 buf = 0x02;
2885 i2c_write_bytes(i2c_client_point, 0x41F9, &buf, 1);
2886 #endif
2887
2888 GTP_GPIO_AS_INT(GTP_INT_PORT);
2889 return i;
2890 }
2891
2892 #endif
2893 //*************** For GT9XXF End ***********************//
kernel source for telekom puls (alcatel/mediatek)