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Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / infiniband / hw / mthca / mthca_qp.c
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 *
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 */
37
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
58 };
59
60 enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83 };
84
85 enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100 };
101
102 struct mthca_qp_path {
103 __be32 port_pkey;
104 u8 rnr_retry;
105 u8 g_mylmc;
106 __be16 rlid;
107 u8 ackto;
108 u8 mgid_index;
109 u8 static_rate;
110 u8 hop_limit;
111 __be32 sl_tclass_flowlabel;
112 u8 rgid[16];
113 } __attribute__((packed));
114
115 struct mthca_qp_context {
116 __be32 flags;
117 __be32 tavor_sched_queue; /* Reserved on Arbel */
118 u8 mtu_msgmax;
119 u8 rq_size_stride; /* Reserved on Tavor */
120 u8 sq_size_stride; /* Reserved on Tavor */
121 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
122 __be32 usr_page;
123 __be32 local_qpn;
124 __be32 remote_qpn;
125 u32 reserved1[2];
126 struct mthca_qp_path pri_path;
127 struct mthca_qp_path alt_path;
128 __be32 rdd;
129 __be32 pd;
130 __be32 wqe_base;
131 __be32 wqe_lkey;
132 __be32 params1;
133 __be32 reserved2;
134 __be32 next_send_psn;
135 __be32 cqn_snd;
136 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
137 __be32 snd_db_index; /* (debugging only entries) */
138 __be32 last_acked_psn;
139 __be32 ssn;
140 __be32 params2;
141 __be32 rnr_nextrecvpsn;
142 __be32 ra_buff_indx;
143 __be32 cqn_rcv;
144 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
145 __be32 rcv_db_index; /* (debugging only entries) */
146 __be32 qkey;
147 __be32 srqn;
148 __be32 rmsn;
149 __be16 rq_wqe_counter; /* reserved on Tavor */
150 __be16 sq_wqe_counter; /* reserved on Tavor */
151 u32 reserved3[18];
152 } __attribute__((packed));
153
154 struct mthca_qp_param {
155 __be32 opt_param_mask;
156 u32 reserved1;
157 struct mthca_qp_context context;
158 u32 reserved2[62];
159 } __attribute__((packed));
160
161 enum {
162 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
163 MTHCA_QP_OPTPAR_RRE = 1 << 1,
164 MTHCA_QP_OPTPAR_RAE = 1 << 2,
165 MTHCA_QP_OPTPAR_RWE = 1 << 3,
166 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
167 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
168 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
169 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
170 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
171 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
172 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
173 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
174 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
175 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
176 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
177 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
178 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
179 };
180
181 static const u8 mthca_opcode[] = {
182 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
183 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
184 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
185 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
186 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
187 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
188 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
189 };
190
191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
192 {
193 return qp->qpn >= dev->qp_table.sqp_start &&
194 qp->qpn <= dev->qp_table.sqp_start + 3;
195 }
196
197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
198 {
199 return qp->qpn >= dev->qp_table.sqp_start &&
200 qp->qpn <= dev->qp_table.sqp_start + 1;
201 }
202
203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
204 {
205 if (qp->is_direct)
206 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
207 else
208 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
209 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
210 }
211
212 static void *get_send_wqe(struct mthca_qp *qp, int n)
213 {
214 if (qp->is_direct)
215 return qp->queue.direct.buf + qp->send_wqe_offset +
216 (n << qp->sq.wqe_shift);
217 else
218 return qp->queue.page_list[(qp->send_wqe_offset +
219 (n << qp->sq.wqe_shift)) >>
220 PAGE_SHIFT].buf +
221 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
222 (PAGE_SIZE - 1));
223 }
224
225 static void mthca_wq_init(struct mthca_wq *wq)
226 {
227 spin_lock_init(&wq->lock);
228 wq->next_ind = 0;
229 wq->last_comp = wq->max - 1;
230 wq->head = 0;
231 wq->tail = 0;
232 }
233
234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
235 enum ib_event_type event_type)
236 {
237 struct mthca_qp *qp;
238 struct ib_event event;
239
240 spin_lock(&dev->qp_table.lock);
241 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
242 if (qp)
243 atomic_inc(&qp->refcount);
244 spin_unlock(&dev->qp_table.lock);
245
246 if (!qp) {
247 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
248 return;
249 }
250
251 event.device = &dev->ib_dev;
252 event.event = event_type;
253 event.element.qp = &qp->ibqp;
254 if (qp->ibqp.event_handler)
255 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
256
257 if (atomic_dec_and_test(&qp->refcount))
258 wake_up(&qp->wait);
259 }
260
261 static int to_mthca_state(enum ib_qp_state ib_state)
262 {
263 switch (ib_state) {
264 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
265 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
266 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
267 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
268 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
269 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
270 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
271 default: return -1;
272 }
273 }
274
275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
276
277 static int to_mthca_st(int transport)
278 {
279 switch (transport) {
280 case RC: return MTHCA_QP_ST_RC;
281 case UC: return MTHCA_QP_ST_UC;
282 case UD: return MTHCA_QP_ST_UD;
283 case RD: return MTHCA_QP_ST_RD;
284 case MLX: return MTHCA_QP_ST_MLX;
285 default: return -1;
286 }
287 }
288
289 static const struct {
290 int trans;
291 u32 req_param[NUM_TRANS];
292 u32 opt_param[NUM_TRANS];
293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
294 [IB_QPS_RESET] = {
295 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
296 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
297 [IB_QPS_INIT] = {
298 .trans = MTHCA_TRANS_RST2INIT,
299 .req_param = {
300 [UD] = (IB_QP_PKEY_INDEX |
301 IB_QP_PORT |
302 IB_QP_QKEY),
303 [UC] = (IB_QP_PKEY_INDEX |
304 IB_QP_PORT |
305 IB_QP_ACCESS_FLAGS),
306 [RC] = (IB_QP_PKEY_INDEX |
307 IB_QP_PORT |
308 IB_QP_ACCESS_FLAGS),
309 [MLX] = (IB_QP_PKEY_INDEX |
310 IB_QP_QKEY),
311 },
312 /* bug-for-bug compatibility with VAPI: */
313 .opt_param = {
314 [MLX] = IB_QP_PORT
315 }
316 },
317 },
318 [IB_QPS_INIT] = {
319 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
320 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
321 [IB_QPS_INIT] = {
322 .trans = MTHCA_TRANS_INIT2INIT,
323 .opt_param = {
324 [UD] = (IB_QP_PKEY_INDEX |
325 IB_QP_PORT |
326 IB_QP_QKEY),
327 [UC] = (IB_QP_PKEY_INDEX |
328 IB_QP_PORT |
329 IB_QP_ACCESS_FLAGS),
330 [RC] = (IB_QP_PKEY_INDEX |
331 IB_QP_PORT |
332 IB_QP_ACCESS_FLAGS),
333 [MLX] = (IB_QP_PKEY_INDEX |
334 IB_QP_QKEY),
335 }
336 },
337 [IB_QPS_RTR] = {
338 .trans = MTHCA_TRANS_INIT2RTR,
339 .req_param = {
340 [UC] = (IB_QP_AV |
341 IB_QP_PATH_MTU |
342 IB_QP_DEST_QPN |
343 IB_QP_RQ_PSN),
344 [RC] = (IB_QP_AV |
345 IB_QP_PATH_MTU |
346 IB_QP_DEST_QPN |
347 IB_QP_RQ_PSN |
348 IB_QP_MAX_DEST_RD_ATOMIC |
349 IB_QP_MIN_RNR_TIMER),
350 },
351 .opt_param = {
352 [UD] = (IB_QP_PKEY_INDEX |
353 IB_QP_QKEY),
354 [UC] = (IB_QP_ALT_PATH |
355 IB_QP_ACCESS_FLAGS |
356 IB_QP_PKEY_INDEX),
357 [RC] = (IB_QP_ALT_PATH |
358 IB_QP_ACCESS_FLAGS |
359 IB_QP_PKEY_INDEX),
360 [MLX] = (IB_QP_PKEY_INDEX |
361 IB_QP_QKEY),
362 }
363 }
364 },
365 [IB_QPS_RTR] = {
366 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
367 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
368 [IB_QPS_RTS] = {
369 .trans = MTHCA_TRANS_RTR2RTS,
370 .req_param = {
371 [UD] = IB_QP_SQ_PSN,
372 [UC] = IB_QP_SQ_PSN,
373 [RC] = (IB_QP_TIMEOUT |
374 IB_QP_RETRY_CNT |
375 IB_QP_RNR_RETRY |
376 IB_QP_SQ_PSN |
377 IB_QP_MAX_QP_RD_ATOMIC),
378 [MLX] = IB_QP_SQ_PSN,
379 },
380 .opt_param = {
381 [UD] = (IB_QP_CUR_STATE |
382 IB_QP_QKEY),
383 [UC] = (IB_QP_CUR_STATE |
384 IB_QP_ALT_PATH |
385 IB_QP_ACCESS_FLAGS |
386 IB_QP_PKEY_INDEX |
387 IB_QP_PATH_MIG_STATE),
388 [RC] = (IB_QP_CUR_STATE |
389 IB_QP_ALT_PATH |
390 IB_QP_ACCESS_FLAGS |
391 IB_QP_PKEY_INDEX |
392 IB_QP_MIN_RNR_TIMER |
393 IB_QP_PATH_MIG_STATE),
394 [MLX] = (IB_QP_CUR_STATE |
395 IB_QP_QKEY),
396 }
397 }
398 },
399 [IB_QPS_RTS] = {
400 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
401 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
402 [IB_QPS_RTS] = {
403 .trans = MTHCA_TRANS_RTS2RTS,
404 .opt_param = {
405 [UD] = (IB_QP_CUR_STATE |
406 IB_QP_QKEY),
407 [UC] = (IB_QP_ACCESS_FLAGS |
408 IB_QP_ALT_PATH |
409 IB_QP_PATH_MIG_STATE),
410 [RC] = (IB_QP_ACCESS_FLAGS |
411 IB_QP_ALT_PATH |
412 IB_QP_PATH_MIG_STATE |
413 IB_QP_MIN_RNR_TIMER),
414 [MLX] = (IB_QP_CUR_STATE |
415 IB_QP_QKEY),
416 }
417 },
418 [IB_QPS_SQD] = {
419 .trans = MTHCA_TRANS_RTS2SQD,
420 },
421 },
422 [IB_QPS_SQD] = {
423 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
424 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
425 [IB_QPS_RTS] = {
426 .trans = MTHCA_TRANS_SQD2RTS,
427 .opt_param = {
428 [UD] = (IB_QP_CUR_STATE |
429 IB_QP_QKEY),
430 [UC] = (IB_QP_CUR_STATE |
431 IB_QP_ALT_PATH |
432 IB_QP_ACCESS_FLAGS |
433 IB_QP_PATH_MIG_STATE),
434 [RC] = (IB_QP_CUR_STATE |
435 IB_QP_ALT_PATH |
436 IB_QP_ACCESS_FLAGS |
437 IB_QP_MIN_RNR_TIMER |
438 IB_QP_PATH_MIG_STATE),
439 [MLX] = (IB_QP_CUR_STATE |
440 IB_QP_QKEY),
441 }
442 },
443 [IB_QPS_SQD] = {
444 .trans = MTHCA_TRANS_SQD2SQD,
445 .opt_param = {
446 [UD] = (IB_QP_PKEY_INDEX |
447 IB_QP_QKEY),
448 [UC] = (IB_QP_AV |
449 IB_QP_CUR_STATE |
450 IB_QP_ALT_PATH |
451 IB_QP_ACCESS_FLAGS |
452 IB_QP_PKEY_INDEX |
453 IB_QP_PATH_MIG_STATE),
454 [RC] = (IB_QP_AV |
455 IB_QP_TIMEOUT |
456 IB_QP_RETRY_CNT |
457 IB_QP_RNR_RETRY |
458 IB_QP_MAX_QP_RD_ATOMIC |
459 IB_QP_MAX_DEST_RD_ATOMIC |
460 IB_QP_CUR_STATE |
461 IB_QP_ALT_PATH |
462 IB_QP_ACCESS_FLAGS |
463 IB_QP_PKEY_INDEX |
464 IB_QP_MIN_RNR_TIMER |
465 IB_QP_PATH_MIG_STATE),
466 [MLX] = (IB_QP_PKEY_INDEX |
467 IB_QP_QKEY),
468 }
469 }
470 },
471 [IB_QPS_SQE] = {
472 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
473 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
474 [IB_QPS_RTS] = {
475 .trans = MTHCA_TRANS_SQERR2RTS,
476 .opt_param = {
477 [UD] = (IB_QP_CUR_STATE |
478 IB_QP_QKEY),
479 [UC] = IB_QP_CUR_STATE,
480 [RC] = (IB_QP_CUR_STATE |
481 IB_QP_MIN_RNR_TIMER),
482 [MLX] = (IB_QP_CUR_STATE |
483 IB_QP_QKEY),
484 }
485 }
486 },
487 [IB_QPS_ERR] = {
488 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
489 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
490 }
491 };
492
493 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
494 int attr_mask)
495 {
496 if (attr_mask & IB_QP_PKEY_INDEX)
497 sqp->pkey_index = attr->pkey_index;
498 if (attr_mask & IB_QP_QKEY)
499 sqp->qkey = attr->qkey;
500 if (attr_mask & IB_QP_SQ_PSN)
501 sqp->send_psn = attr->sq_psn;
502 }
503
504 static void init_port(struct mthca_dev *dev, int port)
505 {
506 int err;
507 u8 status;
508 struct mthca_init_ib_param param;
509
510 memset(&param, 0, sizeof param);
511
512 param.port_width = dev->limits.port_width_cap;
513 param.vl_cap = dev->limits.vl_cap;
514 param.mtu_cap = dev->limits.mtu_cap;
515 param.gid_cap = dev->limits.gid_table_len;
516 param.pkey_cap = dev->limits.pkey_table_len;
517
518 err = mthca_INIT_IB(dev, &param, port, &status);
519 if (err)
520 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
521 if (status)
522 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
523 }
524
525 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
526 {
527 struct mthca_dev *dev = to_mdev(ibqp->device);
528 struct mthca_qp *qp = to_mqp(ibqp);
529 enum ib_qp_state cur_state, new_state;
530 struct mthca_mailbox *mailbox;
531 struct mthca_qp_param *qp_param;
532 struct mthca_qp_context *qp_context;
533 u32 req_param, opt_param;
534 u8 status;
535 int err;
536
537 if (attr_mask & IB_QP_CUR_STATE) {
538 if (attr->cur_qp_state != IB_QPS_RTR &&
539 attr->cur_qp_state != IB_QPS_RTS &&
540 attr->cur_qp_state != IB_QPS_SQD &&
541 attr->cur_qp_state != IB_QPS_SQE)
542 return -EINVAL;
543 else
544 cur_state = attr->cur_qp_state;
545 } else {
546 spin_lock_irq(&qp->sq.lock);
547 spin_lock(&qp->rq.lock);
548 cur_state = qp->state;
549 spin_unlock(&qp->rq.lock);
550 spin_unlock_irq(&qp->sq.lock);
551 }
552
553 if (attr_mask & IB_QP_STATE) {
554 if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
555 return -EINVAL;
556 new_state = attr->qp_state;
557 } else
558 new_state = cur_state;
559
560 if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
561 mthca_dbg(dev, "Illegal QP transition "
562 "%d->%d\n", cur_state, new_state);
563 return -EINVAL;
564 }
565
566 req_param = state_table[cur_state][new_state].req_param[qp->transport];
567 opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
568
569 if ((req_param & attr_mask) != req_param) {
570 mthca_dbg(dev, "QP transition "
571 "%d->%d missing req attr 0x%08x\n",
572 cur_state, new_state,
573 req_param & ~attr_mask);
574 return -EINVAL;
575 }
576
577 if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
578 mthca_dbg(dev, "QP transition (transport %d) "
579 "%d->%d has extra attr 0x%08x\n",
580 qp->transport,
581 cur_state, new_state,
582 attr_mask & ~(req_param | opt_param |
583 IB_QP_STATE));
584 return -EINVAL;
585 }
586
587 if ((attr_mask & IB_QP_PKEY_INDEX) &&
588 attr->pkey_index >= dev->limits.pkey_table_len) {
589 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
590 attr->pkey_index,dev->limits.pkey_table_len-1);
591 return -EINVAL;
592 }
593
594 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
595 if (IS_ERR(mailbox))
596 return PTR_ERR(mailbox);
597 qp_param = mailbox->buf;
598 qp_context = &qp_param->context;
599 memset(qp_param, 0, sizeof *qp_param);
600
601 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
602 (to_mthca_st(qp->transport) << 16));
603 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
604 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
605 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
606 else {
607 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
608 switch (attr->path_mig_state) {
609 case IB_MIG_MIGRATED:
610 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
611 break;
612 case IB_MIG_REARM:
613 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
614 break;
615 case IB_MIG_ARMED:
616 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
617 break;
618 }
619 }
620
621 /* leave tavor_sched_queue as 0 */
622
623 if (qp->transport == MLX || qp->transport == UD)
624 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
625 else if (attr_mask & IB_QP_PATH_MTU)
626 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
627
628 if (mthca_is_memfree(dev)) {
629 if (qp->rq.max)
630 qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
631 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
632
633 if (qp->sq.max)
634 qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
635 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
636 }
637
638 /* leave arbel_sched_queue as 0 */
639
640 if (qp->ibqp.uobject)
641 qp_context->usr_page =
642 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
643 else
644 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
645 qp_context->local_qpn = cpu_to_be32(qp->qpn);
646 if (attr_mask & IB_QP_DEST_QPN) {
647 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
648 }
649
650 if (qp->transport == MLX)
651 qp_context->pri_path.port_pkey |=
652 cpu_to_be32(to_msqp(qp)->port << 24);
653 else {
654 if (attr_mask & IB_QP_PORT) {
655 qp_context->pri_path.port_pkey |=
656 cpu_to_be32(attr->port_num << 24);
657 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
658 }
659 }
660
661 if (attr_mask & IB_QP_PKEY_INDEX) {
662 qp_context->pri_path.port_pkey |=
663 cpu_to_be32(attr->pkey_index);
664 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
665 }
666
667 if (attr_mask & IB_QP_RNR_RETRY) {
668 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
669 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
670 }
671
672 if (attr_mask & IB_QP_AV) {
673 qp_context->pri_path.g_mylmc = attr->ah_attr.src_path_bits & 0x7f;
674 qp_context->pri_path.rlid = cpu_to_be16(attr->ah_attr.dlid);
675 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
676 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
677 qp_context->pri_path.g_mylmc |= 1 << 7;
678 qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
679 qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
680 qp_context->pri_path.sl_tclass_flowlabel =
681 cpu_to_be32((attr->ah_attr.sl << 28) |
682 (attr->ah_attr.grh.traffic_class << 20) |
683 (attr->ah_attr.grh.flow_label));
684 memcpy(qp_context->pri_path.rgid,
685 attr->ah_attr.grh.dgid.raw, 16);
686 } else {
687 qp_context->pri_path.sl_tclass_flowlabel =
688 cpu_to_be32(attr->ah_attr.sl << 28);
689 }
690 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
691 }
692
693 if (attr_mask & IB_QP_TIMEOUT) {
694 qp_context->pri_path.ackto = attr->timeout << 3;
695 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
696 }
697
698 /* XXX alt_path */
699
700 /* leave rdd as 0 */
701 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
702 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
703 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
704 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
705 (MTHCA_FLIGHT_LIMIT << 24) |
706 MTHCA_QP_BIT_SRE |
707 MTHCA_QP_BIT_SWE |
708 MTHCA_QP_BIT_SAE);
709 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
710 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
711 if (attr_mask & IB_QP_RETRY_CNT) {
712 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
713 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
714 }
715
716 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
717 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
718 ffs(attr->max_rd_atomic) - 1 : 0,
719 7) << 21);
720 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
721 }
722
723 if (attr_mask & IB_QP_SQ_PSN)
724 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
725 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
726
727 if (mthca_is_memfree(dev)) {
728 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
729 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
730 }
731
732 if (attr_mask & IB_QP_ACCESS_FLAGS) {
733 /*
734 * Only enable RDMA/atomics if we have responder
735 * resources set to a non-zero value.
736 */
737 if (qp->resp_depth) {
738 qp_context->params2 |=
739 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
740 MTHCA_QP_BIT_RWE : 0);
741 qp_context->params2 |=
742 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
743 MTHCA_QP_BIT_RRE : 0);
744 qp_context->params2 |=
745 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
746 MTHCA_QP_BIT_RAE : 0);
747 }
748
749 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
750 MTHCA_QP_OPTPAR_RRE |
751 MTHCA_QP_OPTPAR_RAE);
752
753 qp->atomic_rd_en = attr->qp_access_flags;
754 }
755
756 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
757 u8 rra_max;
758
759 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
760 /*
761 * Lowering our responder resources to zero.
762 * Turn off RDMA/atomics as responder.
763 * (RWE/RRE/RAE in params2 already zero)
764 */
765 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
766 MTHCA_QP_OPTPAR_RRE |
767 MTHCA_QP_OPTPAR_RAE);
768 }
769
770 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
771 /*
772 * Increasing our responder resources from
773 * zero. Turn on RDMA/atomics as appropriate.
774 */
775 qp_context->params2 |=
776 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
777 MTHCA_QP_BIT_RWE : 0);
778 qp_context->params2 |=
779 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
780 MTHCA_QP_BIT_RRE : 0);
781 qp_context->params2 |=
782 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
783 MTHCA_QP_BIT_RAE : 0);
784
785 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
786 MTHCA_QP_OPTPAR_RRE |
787 MTHCA_QP_OPTPAR_RAE);
788 }
789
790 for (rra_max = 0;
791 1 << rra_max < attr->max_dest_rd_atomic &&
792 rra_max < dev->qp_table.rdb_shift;
793 ++rra_max)
794 ; /* nothing */
795
796 qp_context->params2 |= cpu_to_be32(rra_max << 21);
797 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
798
799 qp->resp_depth = attr->max_dest_rd_atomic;
800 }
801
802 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
803
804 if (ibqp->srq)
805 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
806
807 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
808 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
809 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
810 }
811 if (attr_mask & IB_QP_RQ_PSN)
812 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
813
814 qp_context->ra_buff_indx =
815 cpu_to_be32(dev->qp_table.rdb_base +
816 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
817 dev->qp_table.rdb_shift));
818
819 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
820
821 if (mthca_is_memfree(dev))
822 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
823
824 if (attr_mask & IB_QP_QKEY) {
825 qp_context->qkey = cpu_to_be32(attr->qkey);
826 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
827 }
828
829 if (ibqp->srq)
830 qp_context->srqn = cpu_to_be32(1 << 24 |
831 to_msrq(ibqp->srq)->srqn);
832
833 err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
834 qp->qpn, 0, mailbox, 0, &status);
835 if (status) {
836 mthca_warn(dev, "modify QP %d returned status %02x.\n",
837 state_table[cur_state][new_state].trans, status);
838 err = -EINVAL;
839 }
840
841 if (!err)
842 qp->state = new_state;
843
844 mthca_free_mailbox(dev, mailbox);
845
846 if (is_sqp(dev, qp))
847 store_attrs(to_msqp(qp), attr, attr_mask);
848
849 /*
850 * If we moved QP0 to RTR, bring the IB link up; if we moved
851 * QP0 to RESET or ERROR, bring the link back down.
852 */
853 if (is_qp0(dev, qp)) {
854 if (cur_state != IB_QPS_RTR &&
855 new_state == IB_QPS_RTR)
856 init_port(dev, to_msqp(qp)->port);
857
858 if (cur_state != IB_QPS_RESET &&
859 cur_state != IB_QPS_ERR &&
860 (new_state == IB_QPS_RESET ||
861 new_state == IB_QPS_ERR))
862 mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
863 }
864
865 /*
866 * If we moved a kernel QP to RESET, clean up all old CQ
867 * entries and reinitialize the QP.
868 */
869 if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
870 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
871 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
872 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
873 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
874 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
875
876 mthca_wq_init(&qp->sq);
877 mthca_wq_init(&qp->rq);
878
879 if (mthca_is_memfree(dev)) {
880 *qp->sq.db = 0;
881 *qp->rq.db = 0;
882 }
883 }
884
885 return err;
886 }
887
888 /*
889 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
890 * rq.max_gs and sq.max_gs must all be assigned.
891 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
892 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
893 * queue)
894 */
895 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
896 struct mthca_pd *pd,
897 struct mthca_qp *qp)
898 {
899 int size;
900 int err = -ENOMEM;
901
902 size = sizeof (struct mthca_next_seg) +
903 qp->rq.max_gs * sizeof (struct mthca_data_seg);
904
905 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
906 qp->rq.wqe_shift++)
907 ; /* nothing */
908
909 size = sizeof (struct mthca_next_seg) +
910 qp->sq.max_gs * sizeof (struct mthca_data_seg);
911 switch (qp->transport) {
912 case MLX:
913 size += 2 * sizeof (struct mthca_data_seg);
914 break;
915 case UD:
916 if (mthca_is_memfree(dev))
917 size += sizeof (struct mthca_arbel_ud_seg);
918 else
919 size += sizeof (struct mthca_tavor_ud_seg);
920 break;
921 default:
922 /* bind seg is as big as atomic + raddr segs */
923 size += sizeof (struct mthca_bind_seg);
924 }
925
926 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
927 qp->sq.wqe_shift++)
928 ; /* nothing */
929
930 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
931 1 << qp->sq.wqe_shift);
932
933 /*
934 * If this is a userspace QP, we don't actually have to
935 * allocate anything. All we need is to calculate the WQE
936 * sizes and the send_wqe_offset, so we're done now.
937 */
938 if (pd->ibpd.uobject)
939 return 0;
940
941 size = PAGE_ALIGN(qp->send_wqe_offset +
942 (qp->sq.max << qp->sq.wqe_shift));
943
944 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
945 GFP_KERNEL);
946 if (!qp->wrid)
947 goto err_out;
948
949 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
950 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
951 if (err)
952 goto err_out;
953
954 return 0;
955
956 err_out:
957 kfree(qp->wrid);
958 return err;
959 }
960
961 static void mthca_free_wqe_buf(struct mthca_dev *dev,
962 struct mthca_qp *qp)
963 {
964 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
965 (qp->sq.max << qp->sq.wqe_shift)),
966 &qp->queue, qp->is_direct, &qp->mr);
967 kfree(qp->wrid);
968 }
969
970 static int mthca_map_memfree(struct mthca_dev *dev,
971 struct mthca_qp *qp)
972 {
973 int ret;
974
975 if (mthca_is_memfree(dev)) {
976 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
977 if (ret)
978 return ret;
979
980 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
981 if (ret)
982 goto err_qpc;
983
984 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
985 qp->qpn << dev->qp_table.rdb_shift);
986 if (ret)
987 goto err_eqpc;
988
989 }
990
991 return 0;
992
993 err_eqpc:
994 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
995
996 err_qpc:
997 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
998
999 return ret;
1000 }
1001
1002 static void mthca_unmap_memfree(struct mthca_dev *dev,
1003 struct mthca_qp *qp)
1004 {
1005 mthca_table_put(dev, dev->qp_table.rdb_table,
1006 qp->qpn << dev->qp_table.rdb_shift);
1007 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1008 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1009 }
1010
1011 static int mthca_alloc_memfree(struct mthca_dev *dev,
1012 struct mthca_qp *qp)
1013 {
1014 int ret = 0;
1015
1016 if (mthca_is_memfree(dev)) {
1017 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1018 qp->qpn, &qp->rq.db);
1019 if (qp->rq.db_index < 0)
1020 return ret;
1021
1022 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1023 qp->qpn, &qp->sq.db);
1024 if (qp->sq.db_index < 0)
1025 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1026 }
1027
1028 return ret;
1029 }
1030
1031 static void mthca_free_memfree(struct mthca_dev *dev,
1032 struct mthca_qp *qp)
1033 {
1034 if (mthca_is_memfree(dev)) {
1035 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1036 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1037 }
1038 }
1039
1040 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1041 struct mthca_pd *pd,
1042 struct mthca_cq *send_cq,
1043 struct mthca_cq *recv_cq,
1044 enum ib_sig_type send_policy,
1045 struct mthca_qp *qp)
1046 {
1047 int ret;
1048 int i;
1049
1050 atomic_set(&qp->refcount, 1);
1051 init_waitqueue_head(&qp->wait);
1052 qp->state = IB_QPS_RESET;
1053 qp->atomic_rd_en = 0;
1054 qp->resp_depth = 0;
1055 qp->sq_policy = send_policy;
1056 mthca_wq_init(&qp->sq);
1057 mthca_wq_init(&qp->rq);
1058
1059 ret = mthca_map_memfree(dev, qp);
1060 if (ret)
1061 return ret;
1062
1063 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1064 if (ret) {
1065 mthca_unmap_memfree(dev, qp);
1066 return ret;
1067 }
1068
1069 /*
1070 * If this is a userspace QP, we're done now. The doorbells
1071 * will be allocated and buffers will be initialized in
1072 * userspace.
1073 */
1074 if (pd->ibpd.uobject)
1075 return 0;
1076
1077 ret = mthca_alloc_memfree(dev, qp);
1078 if (ret) {
1079 mthca_free_wqe_buf(dev, qp);
1080 mthca_unmap_memfree(dev, qp);
1081 return ret;
1082 }
1083
1084 if (mthca_is_memfree(dev)) {
1085 struct mthca_next_seg *next;
1086 struct mthca_data_seg *scatter;
1087 int size = (sizeof (struct mthca_next_seg) +
1088 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1089
1090 for (i = 0; i < qp->rq.max; ++i) {
1091 next = get_recv_wqe(qp, i);
1092 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1093 qp->rq.wqe_shift);
1094 next->ee_nds = cpu_to_be32(size);
1095
1096 for (scatter = (void *) (next + 1);
1097 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1098 ++scatter)
1099 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1100 }
1101
1102 for (i = 0; i < qp->sq.max; ++i) {
1103 next = get_send_wqe(qp, i);
1104 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1105 qp->sq.wqe_shift) +
1106 qp->send_wqe_offset);
1107 }
1108 }
1109
1110 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1111 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1112
1113 return 0;
1114 }
1115
1116 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1117 struct mthca_qp *qp)
1118 {
1119 /* Sanity check QP size before proceeding */
1120 if (cap->max_send_wr > dev->limits.max_wqes ||
1121 cap->max_recv_wr > dev->limits.max_wqes ||
1122 cap->max_send_sge > dev->limits.max_sg ||
1123 cap->max_recv_sge > dev->limits.max_sg)
1124 return -EINVAL;
1125
1126 if (mthca_is_memfree(dev)) {
1127 qp->rq.max = cap->max_recv_wr ?
1128 roundup_pow_of_two(cap->max_recv_wr) : 0;
1129 qp->sq.max = cap->max_send_wr ?
1130 roundup_pow_of_two(cap->max_send_wr) : 0;
1131 } else {
1132 qp->rq.max = cap->max_recv_wr;
1133 qp->sq.max = cap->max_send_wr;
1134 }
1135
1136 qp->rq.max_gs = cap->max_recv_sge;
1137 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1138 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1139 MTHCA_INLINE_CHUNK_SIZE) /
1140 sizeof (struct mthca_data_seg));
1141
1142 /*
1143 * For MLX transport we need 2 extra S/G entries:
1144 * one for the header and one for the checksum at the end
1145 */
1146 if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1147 qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1148 return -EINVAL;
1149
1150 return 0;
1151 }
1152
1153 int mthca_alloc_qp(struct mthca_dev *dev,
1154 struct mthca_pd *pd,
1155 struct mthca_cq *send_cq,
1156 struct mthca_cq *recv_cq,
1157 enum ib_qp_type type,
1158 enum ib_sig_type send_policy,
1159 struct ib_qp_cap *cap,
1160 struct mthca_qp *qp)
1161 {
1162 int err;
1163
1164 err = mthca_set_qp_size(dev, cap, qp);
1165 if (err)
1166 return err;
1167
1168 switch (type) {
1169 case IB_QPT_RC: qp->transport = RC; break;
1170 case IB_QPT_UC: qp->transport = UC; break;
1171 case IB_QPT_UD: qp->transport = UD; break;
1172 default: return -EINVAL;
1173 }
1174
1175 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1176 if (qp->qpn == -1)
1177 return -ENOMEM;
1178
1179 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1180 send_policy, qp);
1181 if (err) {
1182 mthca_free(&dev->qp_table.alloc, qp->qpn);
1183 return err;
1184 }
1185
1186 spin_lock_irq(&dev->qp_table.lock);
1187 mthca_array_set(&dev->qp_table.qp,
1188 qp->qpn & (dev->limits.num_qps - 1), qp);
1189 spin_unlock_irq(&dev->qp_table.lock);
1190
1191 return 0;
1192 }
1193
1194 int mthca_alloc_sqp(struct mthca_dev *dev,
1195 struct mthca_pd *pd,
1196 struct mthca_cq *send_cq,
1197 struct mthca_cq *recv_cq,
1198 enum ib_sig_type send_policy,
1199 struct ib_qp_cap *cap,
1200 int qpn,
1201 int port,
1202 struct mthca_sqp *sqp)
1203 {
1204 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1205 int err;
1206
1207 err = mthca_set_qp_size(dev, cap, &sqp->qp);
1208 if (err)
1209 return err;
1210
1211 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1212 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1213 &sqp->header_dma, GFP_KERNEL);
1214 if (!sqp->header_buf)
1215 return -ENOMEM;
1216
1217 spin_lock_irq(&dev->qp_table.lock);
1218 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1219 err = -EBUSY;
1220 else
1221 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1222 spin_unlock_irq(&dev->qp_table.lock);
1223
1224 if (err)
1225 goto err_out;
1226
1227 sqp->port = port;
1228 sqp->qp.qpn = mqpn;
1229 sqp->qp.transport = MLX;
1230
1231 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1232 send_policy, &sqp->qp);
1233 if (err)
1234 goto err_out_free;
1235
1236 atomic_inc(&pd->sqp_count);
1237
1238 return 0;
1239
1240 err_out_free:
1241 /*
1242 * Lock CQs here, so that CQ polling code can do QP lookup
1243 * without taking a lock.
1244 */
1245 spin_lock_irq(&send_cq->lock);
1246 if (send_cq != recv_cq)
1247 spin_lock(&recv_cq->lock);
1248
1249 spin_lock(&dev->qp_table.lock);
1250 mthca_array_clear(&dev->qp_table.qp, mqpn);
1251 spin_unlock(&dev->qp_table.lock);
1252
1253 if (send_cq != recv_cq)
1254 spin_unlock(&recv_cq->lock);
1255 spin_unlock_irq(&send_cq->lock);
1256
1257 err_out:
1258 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1259 sqp->header_buf, sqp->header_dma);
1260
1261 return err;
1262 }
1263
1264 void mthca_free_qp(struct mthca_dev *dev,
1265 struct mthca_qp *qp)
1266 {
1267 u8 status;
1268 struct mthca_cq *send_cq;
1269 struct mthca_cq *recv_cq;
1270
1271 send_cq = to_mcq(qp->ibqp.send_cq);
1272 recv_cq = to_mcq(qp->ibqp.recv_cq);
1273
1274 /*
1275 * Lock CQs here, so that CQ polling code can do QP lookup
1276 * without taking a lock.
1277 */
1278 spin_lock_irq(&send_cq->lock);
1279 if (send_cq != recv_cq)
1280 spin_lock(&recv_cq->lock);
1281
1282 spin_lock(&dev->qp_table.lock);
1283 mthca_array_clear(&dev->qp_table.qp,
1284 qp->qpn & (dev->limits.num_qps - 1));
1285 spin_unlock(&dev->qp_table.lock);
1286
1287 if (send_cq != recv_cq)
1288 spin_unlock(&recv_cq->lock);
1289 spin_unlock_irq(&send_cq->lock);
1290
1291 atomic_dec(&qp->refcount);
1292 wait_event(qp->wait, !atomic_read(&qp->refcount));
1293
1294 if (qp->state != IB_QPS_RESET)
1295 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1296
1297 /*
1298 * If this is a userspace QP, the buffers, MR, CQs and so on
1299 * will be cleaned up in userspace, so all we have to do is
1300 * unref the mem-free tables and free the QPN in our table.
1301 */
1302 if (!qp->ibqp.uobject) {
1303 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1304 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1305 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1306 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1307 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1308
1309 mthca_free_memfree(dev, qp);
1310 mthca_free_wqe_buf(dev, qp);
1311 }
1312
1313 mthca_unmap_memfree(dev, qp);
1314
1315 if (is_sqp(dev, qp)) {
1316 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1317 dma_free_coherent(&dev->pdev->dev,
1318 to_msqp(qp)->header_buf_size,
1319 to_msqp(qp)->header_buf,
1320 to_msqp(qp)->header_dma);
1321 } else
1322 mthca_free(&dev->qp_table.alloc, qp->qpn);
1323 }
1324
1325 /* Create UD header for an MLX send and build a data segment for it */
1326 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1327 int ind, struct ib_send_wr *wr,
1328 struct mthca_mlx_seg *mlx,
1329 struct mthca_data_seg *data)
1330 {
1331 int header_size;
1332 int err;
1333 u16 pkey;
1334
1335 ib_ud_header_init(256, /* assume a MAD */
1336 sqp->ud_header.grh_present,
1337 &sqp->ud_header);
1338
1339 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1340 if (err)
1341 return err;
1342 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1343 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1344 (sqp->ud_header.lrh.destination_lid ==
1345 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1346 (sqp->ud_header.lrh.service_level << 8));
1347 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1348 mlx->vcrc = 0;
1349
1350 switch (wr->opcode) {
1351 case IB_WR_SEND:
1352 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1353 sqp->ud_header.immediate_present = 0;
1354 break;
1355 case IB_WR_SEND_WITH_IMM:
1356 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1357 sqp->ud_header.immediate_present = 1;
1358 sqp->ud_header.immediate_data = wr->imm_data;
1359 break;
1360 default:
1361 return -EINVAL;
1362 }
1363
1364 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1365 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1366 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1367 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1368 if (!sqp->qp.ibqp.qp_num)
1369 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1370 sqp->pkey_index, &pkey);
1371 else
1372 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1373 wr->wr.ud.pkey_index, &pkey);
1374 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1375 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1376 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1377 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1378 sqp->qkey : wr->wr.ud.remote_qkey);
1379 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1380
1381 header_size = ib_ud_header_pack(&sqp->ud_header,
1382 sqp->header_buf +
1383 ind * MTHCA_UD_HEADER_SIZE);
1384
1385 data->byte_count = cpu_to_be32(header_size);
1386 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1387 data->addr = cpu_to_be64(sqp->header_dma +
1388 ind * MTHCA_UD_HEADER_SIZE);
1389
1390 return 0;
1391 }
1392
1393 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1394 struct ib_cq *ib_cq)
1395 {
1396 unsigned cur;
1397 struct mthca_cq *cq;
1398
1399 cur = wq->head - wq->tail;
1400 if (likely(cur + nreq < wq->max))
1401 return 0;
1402
1403 cq = to_mcq(ib_cq);
1404 spin_lock(&cq->lock);
1405 cur = wq->head - wq->tail;
1406 spin_unlock(&cq->lock);
1407
1408 return cur + nreq >= wq->max;
1409 }
1410
1411 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1412 struct ib_send_wr **bad_wr)
1413 {
1414 struct mthca_dev *dev = to_mdev(ibqp->device);
1415 struct mthca_qp *qp = to_mqp(ibqp);
1416 void *wqe;
1417 void *prev_wqe;
1418 unsigned long flags;
1419 int err = 0;
1420 int nreq;
1421 int i;
1422 int size;
1423 int size0 = 0;
1424 u32 f0 = 0;
1425 int ind;
1426 u8 op0 = 0;
1427
1428 spin_lock_irqsave(&qp->sq.lock, flags);
1429
1430 /* XXX check that state is OK to post send */
1431
1432 ind = qp->sq.next_ind;
1433
1434 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1435 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1436 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1437 " %d max, %d nreq)\n", qp->qpn,
1438 qp->sq.head, qp->sq.tail,
1439 qp->sq.max, nreq);
1440 err = -ENOMEM;
1441 *bad_wr = wr;
1442 goto out;
1443 }
1444
1445 wqe = get_send_wqe(qp, ind);
1446 prev_wqe = qp->sq.last;
1447 qp->sq.last = wqe;
1448
1449 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1450 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1451 ((struct mthca_next_seg *) wqe)->flags =
1452 ((wr->send_flags & IB_SEND_SIGNALED) ?
1453 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1454 ((wr->send_flags & IB_SEND_SOLICITED) ?
1455 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1456 cpu_to_be32(1);
1457 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1458 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1459 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1460
1461 wqe += sizeof (struct mthca_next_seg);
1462 size = sizeof (struct mthca_next_seg) / 16;
1463
1464 switch (qp->transport) {
1465 case RC:
1466 switch (wr->opcode) {
1467 case IB_WR_ATOMIC_CMP_AND_SWP:
1468 case IB_WR_ATOMIC_FETCH_AND_ADD:
1469 ((struct mthca_raddr_seg *) wqe)->raddr =
1470 cpu_to_be64(wr->wr.atomic.remote_addr);
1471 ((struct mthca_raddr_seg *) wqe)->rkey =
1472 cpu_to_be32(wr->wr.atomic.rkey);
1473 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1474
1475 wqe += sizeof (struct mthca_raddr_seg);
1476
1477 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1478 ((struct mthca_atomic_seg *) wqe)->swap_add =
1479 cpu_to_be64(wr->wr.atomic.swap);
1480 ((struct mthca_atomic_seg *) wqe)->compare =
1481 cpu_to_be64(wr->wr.atomic.compare_add);
1482 } else {
1483 ((struct mthca_atomic_seg *) wqe)->swap_add =
1484 cpu_to_be64(wr->wr.atomic.compare_add);
1485 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1486 }
1487
1488 wqe += sizeof (struct mthca_atomic_seg);
1489 size += sizeof (struct mthca_raddr_seg) / 16 +
1490 sizeof (struct mthca_atomic_seg);
1491 break;
1492
1493 case IB_WR_RDMA_WRITE:
1494 case IB_WR_RDMA_WRITE_WITH_IMM:
1495 case IB_WR_RDMA_READ:
1496 ((struct mthca_raddr_seg *) wqe)->raddr =
1497 cpu_to_be64(wr->wr.rdma.remote_addr);
1498 ((struct mthca_raddr_seg *) wqe)->rkey =
1499 cpu_to_be32(wr->wr.rdma.rkey);
1500 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1501 wqe += sizeof (struct mthca_raddr_seg);
1502 size += sizeof (struct mthca_raddr_seg) / 16;
1503 break;
1504
1505 default:
1506 /* No extra segments required for sends */
1507 break;
1508 }
1509
1510 break;
1511
1512 case UC:
1513 switch (wr->opcode) {
1514 case IB_WR_RDMA_WRITE:
1515 case IB_WR_RDMA_WRITE_WITH_IMM:
1516 ((struct mthca_raddr_seg *) wqe)->raddr =
1517 cpu_to_be64(wr->wr.rdma.remote_addr);
1518 ((struct mthca_raddr_seg *) wqe)->rkey =
1519 cpu_to_be32(wr->wr.rdma.rkey);
1520 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1521 wqe += sizeof (struct mthca_raddr_seg);
1522 size += sizeof (struct mthca_raddr_seg) / 16;
1523 break;
1524
1525 default:
1526 /* No extra segments required for sends */
1527 break;
1528 }
1529
1530 break;
1531
1532 case UD:
1533 ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1534 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1535 ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1536 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1537 ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1538 cpu_to_be32(wr->wr.ud.remote_qpn);
1539 ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1540 cpu_to_be32(wr->wr.ud.remote_qkey);
1541
1542 wqe += sizeof (struct mthca_tavor_ud_seg);
1543 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1544 break;
1545
1546 case MLX:
1547 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1548 wqe - sizeof (struct mthca_next_seg),
1549 wqe);
1550 if (err) {
1551 *bad_wr = wr;
1552 goto out;
1553 }
1554 wqe += sizeof (struct mthca_data_seg);
1555 size += sizeof (struct mthca_data_seg) / 16;
1556 break;
1557 }
1558
1559 if (wr->num_sge > qp->sq.max_gs) {
1560 mthca_err(dev, "too many gathers\n");
1561 err = -EINVAL;
1562 *bad_wr = wr;
1563 goto out;
1564 }
1565
1566 for (i = 0; i < wr->num_sge; ++i) {
1567 ((struct mthca_data_seg *) wqe)->byte_count =
1568 cpu_to_be32(wr->sg_list[i].length);
1569 ((struct mthca_data_seg *) wqe)->lkey =
1570 cpu_to_be32(wr->sg_list[i].lkey);
1571 ((struct mthca_data_seg *) wqe)->addr =
1572 cpu_to_be64(wr->sg_list[i].addr);
1573 wqe += sizeof (struct mthca_data_seg);
1574 size += sizeof (struct mthca_data_seg) / 16;
1575 }
1576
1577 /* Add one more inline data segment for ICRC */
1578 if (qp->transport == MLX) {
1579 ((struct mthca_data_seg *) wqe)->byte_count =
1580 cpu_to_be32((1 << 31) | 4);
1581 ((u32 *) wqe)[1] = 0;
1582 wqe += sizeof (struct mthca_data_seg);
1583 size += sizeof (struct mthca_data_seg) / 16;
1584 }
1585
1586 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1587
1588 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1589 mthca_err(dev, "opcode invalid\n");
1590 err = -EINVAL;
1591 *bad_wr = wr;
1592 goto out;
1593 }
1594
1595 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1596 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1597 qp->send_wqe_offset) |
1598 mthca_opcode[wr->opcode]);
1599 wmb();
1600 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1601 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1602
1603 if (!size0) {
1604 size0 = size;
1605 op0 = mthca_opcode[wr->opcode];
1606 }
1607
1608 ++ind;
1609 if (unlikely(ind >= qp->sq.max))
1610 ind -= qp->sq.max;
1611 }
1612
1613 out:
1614 if (likely(nreq)) {
1615 __be32 doorbell[2];
1616
1617 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1618 qp->send_wqe_offset) | f0 | op0);
1619 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1620
1621 wmb();
1622
1623 mthca_write64(doorbell,
1624 dev->kar + MTHCA_SEND_DOORBELL,
1625 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1626 }
1627
1628 qp->sq.next_ind = ind;
1629 qp->sq.head += nreq;
1630
1631 spin_unlock_irqrestore(&qp->sq.lock, flags);
1632 return err;
1633 }
1634
1635 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1636 struct ib_recv_wr **bad_wr)
1637 {
1638 struct mthca_dev *dev = to_mdev(ibqp->device);
1639 struct mthca_qp *qp = to_mqp(ibqp);
1640 unsigned long flags;
1641 int err = 0;
1642 int nreq;
1643 int i;
1644 int size;
1645 int size0 = 0;
1646 int ind;
1647 void *wqe;
1648 void *prev_wqe;
1649
1650 spin_lock_irqsave(&qp->rq.lock, flags);
1651
1652 /* XXX check that state is OK to post receive */
1653
1654 ind = qp->rq.next_ind;
1655
1656 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1657 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1658 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1659 " %d max, %d nreq)\n", qp->qpn,
1660 qp->rq.head, qp->rq.tail,
1661 qp->rq.max, nreq);
1662 err = -ENOMEM;
1663 *bad_wr = wr;
1664 goto out;
1665 }
1666
1667 wqe = get_recv_wqe(qp, ind);
1668 prev_wqe = qp->rq.last;
1669 qp->rq.last = wqe;
1670
1671 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1672 ((struct mthca_next_seg *) wqe)->ee_nds =
1673 cpu_to_be32(MTHCA_NEXT_DBD);
1674 ((struct mthca_next_seg *) wqe)->flags = 0;
1675
1676 wqe += sizeof (struct mthca_next_seg);
1677 size = sizeof (struct mthca_next_seg) / 16;
1678
1679 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1680 err = -EINVAL;
1681 *bad_wr = wr;
1682 goto out;
1683 }
1684
1685 for (i = 0; i < wr->num_sge; ++i) {
1686 ((struct mthca_data_seg *) wqe)->byte_count =
1687 cpu_to_be32(wr->sg_list[i].length);
1688 ((struct mthca_data_seg *) wqe)->lkey =
1689 cpu_to_be32(wr->sg_list[i].lkey);
1690 ((struct mthca_data_seg *) wqe)->addr =
1691 cpu_to_be64(wr->sg_list[i].addr);
1692 wqe += sizeof (struct mthca_data_seg);
1693 size += sizeof (struct mthca_data_seg) / 16;
1694 }
1695
1696 qp->wrid[ind] = wr->wr_id;
1697
1698 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1699 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1700 wmb();
1701 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1702 cpu_to_be32(MTHCA_NEXT_DBD | size);
1703
1704 if (!size0)
1705 size0 = size;
1706
1707 ++ind;
1708 if (unlikely(ind >= qp->rq.max))
1709 ind -= qp->rq.max;
1710 }
1711
1712 out:
1713 if (likely(nreq)) {
1714 __be32 doorbell[2];
1715
1716 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1717 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1718
1719 wmb();
1720
1721 mthca_write64(doorbell,
1722 dev->kar + MTHCA_RECEIVE_DOORBELL,
1723 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1724 }
1725
1726 qp->rq.next_ind = ind;
1727 qp->rq.head += nreq;
1728
1729 spin_unlock_irqrestore(&qp->rq.lock, flags);
1730 return err;
1731 }
1732
1733 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1734 struct ib_send_wr **bad_wr)
1735 {
1736 struct mthca_dev *dev = to_mdev(ibqp->device);
1737 struct mthca_qp *qp = to_mqp(ibqp);
1738 void *wqe;
1739 void *prev_wqe;
1740 unsigned long flags;
1741 int err = 0;
1742 int nreq;
1743 int i;
1744 int size;
1745 int size0 = 0;
1746 u32 f0 = 0;
1747 int ind;
1748 u8 op0 = 0;
1749
1750 spin_lock_irqsave(&qp->sq.lock, flags);
1751
1752 /* XXX check that state is OK to post send */
1753
1754 ind = qp->sq.head & (qp->sq.max - 1);
1755
1756 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1757 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1758 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1759 " %d max, %d nreq)\n", qp->qpn,
1760 qp->sq.head, qp->sq.tail,
1761 qp->sq.max, nreq);
1762 err = -ENOMEM;
1763 *bad_wr = wr;
1764 goto out;
1765 }
1766
1767 wqe = get_send_wqe(qp, ind);
1768 prev_wqe = qp->sq.last;
1769 qp->sq.last = wqe;
1770
1771 ((struct mthca_next_seg *) wqe)->flags =
1772 ((wr->send_flags & IB_SEND_SIGNALED) ?
1773 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1774 ((wr->send_flags & IB_SEND_SOLICITED) ?
1775 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1776 cpu_to_be32(1);
1777 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1778 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1779 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1780
1781 wqe += sizeof (struct mthca_next_seg);
1782 size = sizeof (struct mthca_next_seg) / 16;
1783
1784 switch (qp->transport) {
1785 case RC:
1786 switch (wr->opcode) {
1787 case IB_WR_ATOMIC_CMP_AND_SWP:
1788 case IB_WR_ATOMIC_FETCH_AND_ADD:
1789 ((struct mthca_raddr_seg *) wqe)->raddr =
1790 cpu_to_be64(wr->wr.atomic.remote_addr);
1791 ((struct mthca_raddr_seg *) wqe)->rkey =
1792 cpu_to_be32(wr->wr.atomic.rkey);
1793 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1794
1795 wqe += sizeof (struct mthca_raddr_seg);
1796
1797 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1798 ((struct mthca_atomic_seg *) wqe)->swap_add =
1799 cpu_to_be64(wr->wr.atomic.swap);
1800 ((struct mthca_atomic_seg *) wqe)->compare =
1801 cpu_to_be64(wr->wr.atomic.compare_add);
1802 } else {
1803 ((struct mthca_atomic_seg *) wqe)->swap_add =
1804 cpu_to_be64(wr->wr.atomic.compare_add);
1805 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1806 }
1807
1808 wqe += sizeof (struct mthca_atomic_seg);
1809 size += sizeof (struct mthca_raddr_seg) / 16 +
1810 sizeof (struct mthca_atomic_seg);
1811 break;
1812
1813 case IB_WR_RDMA_READ:
1814 case IB_WR_RDMA_WRITE:
1815 case IB_WR_RDMA_WRITE_WITH_IMM:
1816 ((struct mthca_raddr_seg *) wqe)->raddr =
1817 cpu_to_be64(wr->wr.rdma.remote_addr);
1818 ((struct mthca_raddr_seg *) wqe)->rkey =
1819 cpu_to_be32(wr->wr.rdma.rkey);
1820 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1821 wqe += sizeof (struct mthca_raddr_seg);
1822 size += sizeof (struct mthca_raddr_seg) / 16;
1823 break;
1824
1825 default:
1826 /* No extra segments required for sends */
1827 break;
1828 }
1829
1830 break;
1831
1832 case UC:
1833 switch (wr->opcode) {
1834 case IB_WR_RDMA_WRITE:
1835 case IB_WR_RDMA_WRITE_WITH_IMM:
1836 ((struct mthca_raddr_seg *) wqe)->raddr =
1837 cpu_to_be64(wr->wr.rdma.remote_addr);
1838 ((struct mthca_raddr_seg *) wqe)->rkey =
1839 cpu_to_be32(wr->wr.rdma.rkey);
1840 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1841 wqe += sizeof (struct mthca_raddr_seg);
1842 size += sizeof (struct mthca_raddr_seg) / 16;
1843 break;
1844
1845 default:
1846 /* No extra segments required for sends */
1847 break;
1848 }
1849
1850 break;
1851
1852 case UD:
1853 memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1854 to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1855 ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1856 cpu_to_be32(wr->wr.ud.remote_qpn);
1857 ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1858 cpu_to_be32(wr->wr.ud.remote_qkey);
1859
1860 wqe += sizeof (struct mthca_arbel_ud_seg);
1861 size += sizeof (struct mthca_arbel_ud_seg) / 16;
1862 break;
1863
1864 case MLX:
1865 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1866 wqe - sizeof (struct mthca_next_seg),
1867 wqe);
1868 if (err) {
1869 *bad_wr = wr;
1870 goto out;
1871 }
1872 wqe += sizeof (struct mthca_data_seg);
1873 size += sizeof (struct mthca_data_seg) / 16;
1874 break;
1875 }
1876
1877 if (wr->num_sge > qp->sq.max_gs) {
1878 mthca_err(dev, "too many gathers\n");
1879 err = -EINVAL;
1880 *bad_wr = wr;
1881 goto out;
1882 }
1883
1884 for (i = 0; i < wr->num_sge; ++i) {
1885 ((struct mthca_data_seg *) wqe)->byte_count =
1886 cpu_to_be32(wr->sg_list[i].length);
1887 ((struct mthca_data_seg *) wqe)->lkey =
1888 cpu_to_be32(wr->sg_list[i].lkey);
1889 ((struct mthca_data_seg *) wqe)->addr =
1890 cpu_to_be64(wr->sg_list[i].addr);
1891 wqe += sizeof (struct mthca_data_seg);
1892 size += sizeof (struct mthca_data_seg) / 16;
1893 }
1894
1895 /* Add one more inline data segment for ICRC */
1896 if (qp->transport == MLX) {
1897 ((struct mthca_data_seg *) wqe)->byte_count =
1898 cpu_to_be32((1 << 31) | 4);
1899 ((u32 *) wqe)[1] = 0;
1900 wqe += sizeof (struct mthca_data_seg);
1901 size += sizeof (struct mthca_data_seg) / 16;
1902 }
1903
1904 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1905
1906 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1907 mthca_err(dev, "opcode invalid\n");
1908 err = -EINVAL;
1909 *bad_wr = wr;
1910 goto out;
1911 }
1912
1913 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1914 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1915 qp->send_wqe_offset) |
1916 mthca_opcode[wr->opcode]);
1917 wmb();
1918 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1919 cpu_to_be32(MTHCA_NEXT_DBD | size);
1920
1921 if (!size0) {
1922 size0 = size;
1923 op0 = mthca_opcode[wr->opcode];
1924 }
1925
1926 ++ind;
1927 if (unlikely(ind >= qp->sq.max))
1928 ind -= qp->sq.max;
1929 }
1930
1931 out:
1932 if (likely(nreq)) {
1933 __be32 doorbell[2];
1934
1935 doorbell[0] = cpu_to_be32((nreq << 24) |
1936 ((qp->sq.head & 0xffff) << 8) |
1937 f0 | op0);
1938 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1939
1940 qp->sq.head += nreq;
1941
1942 /*
1943 * Make sure that descriptors are written before
1944 * doorbell record.
1945 */
1946 wmb();
1947 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1948
1949 /*
1950 * Make sure doorbell record is written before we
1951 * write MMIO send doorbell.
1952 */
1953 wmb();
1954 mthca_write64(doorbell,
1955 dev->kar + MTHCA_SEND_DOORBELL,
1956 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1957 }
1958
1959 spin_unlock_irqrestore(&qp->sq.lock, flags);
1960 return err;
1961 }
1962
1963 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1964 struct ib_recv_wr **bad_wr)
1965 {
1966 struct mthca_dev *dev = to_mdev(ibqp->device);
1967 struct mthca_qp *qp = to_mqp(ibqp);
1968 unsigned long flags;
1969 int err = 0;
1970 int nreq;
1971 int ind;
1972 int i;
1973 void *wqe;
1974
1975 spin_lock_irqsave(&qp->rq.lock, flags);
1976
1977 /* XXX check that state is OK to post receive */
1978
1979 ind = qp->rq.head & (qp->rq.max - 1);
1980
1981 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1982 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1983 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1984 " %d max, %d nreq)\n", qp->qpn,
1985 qp->rq.head, qp->rq.tail,
1986 qp->rq.max, nreq);
1987 err = -ENOMEM;
1988 *bad_wr = wr;
1989 goto out;
1990 }
1991
1992 wqe = get_recv_wqe(qp, ind);
1993
1994 ((struct mthca_next_seg *) wqe)->flags = 0;
1995
1996 wqe += sizeof (struct mthca_next_seg);
1997
1998 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1999 err = -EINVAL;
2000 *bad_wr = wr;
2001 goto out;
2002 }
2003
2004 for (i = 0; i < wr->num_sge; ++i) {
2005 ((struct mthca_data_seg *) wqe)->byte_count =
2006 cpu_to_be32(wr->sg_list[i].length);
2007 ((struct mthca_data_seg *) wqe)->lkey =
2008 cpu_to_be32(wr->sg_list[i].lkey);
2009 ((struct mthca_data_seg *) wqe)->addr =
2010 cpu_to_be64(wr->sg_list[i].addr);
2011 wqe += sizeof (struct mthca_data_seg);
2012 }
2013
2014 if (i < qp->rq.max_gs) {
2015 ((struct mthca_data_seg *) wqe)->byte_count = 0;
2016 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2017 ((struct mthca_data_seg *) wqe)->addr = 0;
2018 }
2019
2020 qp->wrid[ind] = wr->wr_id;
2021
2022 ++ind;
2023 if (unlikely(ind >= qp->rq.max))
2024 ind -= qp->rq.max;
2025 }
2026 out:
2027 if (likely(nreq)) {
2028 qp->rq.head += nreq;
2029
2030 /*
2031 * Make sure that descriptors are written before
2032 * doorbell record.
2033 */
2034 wmb();
2035 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2036 }
2037
2038 spin_unlock_irqrestore(&qp->rq.lock, flags);
2039 return err;
2040 }
2041
2042 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2043 int index, int *dbd, __be32 *new_wqe)
2044 {
2045 struct mthca_next_seg *next;
2046
2047 /*
2048 * For SRQs, all WQEs generate a CQE, so we're always at the
2049 * end of the doorbell chain.
2050 */
2051 if (qp->ibqp.srq) {
2052 *new_wqe = 0;
2053 return 0;
2054 }
2055
2056 if (is_send)
2057 next = get_send_wqe(qp, index);
2058 else
2059 next = get_recv_wqe(qp, index);
2060
2061 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2062 if (next->ee_nds & cpu_to_be32(0x3f))
2063 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2064 (next->ee_nds & cpu_to_be32(0x3f));
2065 else
2066 *new_wqe = 0;
2067
2068 return 0;
2069 }
2070
2071 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2072 {
2073 int err;
2074 u8 status;
2075 int i;
2076
2077 spin_lock_init(&dev->qp_table.lock);
2078
2079 /*
2080 * We reserve 2 extra QPs per port for the special QPs. The
2081 * special QP for port 1 has to be even, so round up.
2082 */
2083 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2084 err = mthca_alloc_init(&dev->qp_table.alloc,
2085 dev->limits.num_qps,
2086 (1 << 24) - 1,
2087 dev->qp_table.sqp_start +
2088 MTHCA_MAX_PORTS * 2);
2089 if (err)
2090 return err;
2091
2092 err = mthca_array_init(&dev->qp_table.qp,
2093 dev->limits.num_qps);
2094 if (err) {
2095 mthca_alloc_cleanup(&dev->qp_table.alloc);
2096 return err;
2097 }
2098
2099 for (i = 0; i < 2; ++i) {
2100 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2101 dev->qp_table.sqp_start + i * 2,
2102 &status);
2103 if (err)
2104 goto err_out;
2105 if (status) {
2106 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2107 "status %02x, aborting.\n",
2108 status);
2109 err = -EINVAL;
2110 goto err_out;
2111 }
2112 }
2113 return 0;
2114
2115 err_out:
2116 for (i = 0; i < 2; ++i)
2117 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2118
2119 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2120 mthca_alloc_cleanup(&dev->qp_table.alloc);
2121
2122 return err;
2123 }
2124
2125 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2126 {
2127 int i;
2128 u8 status;
2129
2130 for (i = 0; i < 2; ++i)
2131 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2132
2133 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2134 mthca_alloc_cleanup(&dev->qp_table.alloc);
2135 }
kernel source for telekom puls (alcatel/mediatek)