2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/vmalloc.h>
41 #include "ipath_kernel.h"
42 #include "ipath_verbs.h"
43 #include "ipath_common.h"
45 static void ipath_update_pio_bufs(struct ipath_devdata
*);
47 const char *ipath_get_unit_name(int unit
)
49 static char iname
[16];
50 snprintf(iname
, sizeof iname
, "infinipath%u", unit
);
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
61 const char ib_ipath_version
[] = IPATH_IDSTR
"\n";
63 static struct idr unit_table
;
64 DEFINE_SPINLOCK(ipath_devs_lock
);
65 LIST_HEAD(ipath_dev_list
);
67 wait_queue_head_t ipath_state_wait
;
69 unsigned ipath_debug
= __IPATH_INFO
;
71 module_param_named(debug
, ipath_debug
, uint
, S_IWUSR
| S_IRUGO
);
72 MODULE_PARM_DESC(debug
, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug
);
75 MODULE_LICENSE("GPL");
76 MODULE_AUTHOR("QLogic <support@pathscale.com>");
77 MODULE_DESCRIPTION("QLogic InfiniPath driver");
79 const char *ipath_ibcstatus_str
[] = {
86 "LState6", /* unused */
87 "LState7", /* unused */
93 "LState0xD", /* unused */
98 static void __devexit
ipath_remove_one(struct pci_dev
*);
99 static int __devinit
ipath_init_one(struct pci_dev
*,
100 const struct pci_device_id
*);
102 /* Only needed for registration, nothing else needs this info */
103 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
104 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
105 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
107 static const struct pci_device_id ipath_pci_tbl
[] = {
108 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE
, PCI_DEVICE_ID_INFINIPATH_HT
) },
109 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE
, PCI_DEVICE_ID_INFINIPATH_PE800
) },
113 MODULE_DEVICE_TABLE(pci
, ipath_pci_tbl
);
115 static struct pci_driver ipath_driver
= {
116 .name
= IPATH_DRV_NAME
,
117 .probe
= ipath_init_one
,
118 .remove
= __devexit_p(ipath_remove_one
),
119 .id_table
= ipath_pci_tbl
,
123 static inline void read_bars(struct ipath_devdata
*dd
, struct pci_dev
*dev
,
124 u32
*bar0
, u32
*bar1
)
128 ret
= pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
, bar0
);
130 ipath_dev_err(dd
, "failed to read bar0 before enable: "
133 ret
= pci_read_config_dword(dev
, PCI_BASE_ADDRESS_1
, bar1
);
135 ipath_dev_err(dd
, "failed to read bar1 before enable: "
138 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0
, *bar1
);
141 static void ipath_free_devdata(struct pci_dev
*pdev
,
142 struct ipath_devdata
*dd
)
146 pci_set_drvdata(pdev
, NULL
);
148 if (dd
->ipath_unit
!= -1) {
149 spin_lock_irqsave(&ipath_devs_lock
, flags
);
150 idr_remove(&unit_table
, dd
->ipath_unit
);
151 list_del(&dd
->ipath_list
);
152 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
157 static struct ipath_devdata
*ipath_alloc_devdata(struct pci_dev
*pdev
)
160 struct ipath_devdata
*dd
;
163 if (!idr_pre_get(&unit_table
, GFP_KERNEL
)) {
164 dd
= ERR_PTR(-ENOMEM
);
168 dd
= vmalloc(sizeof(*dd
));
170 dd
= ERR_PTR(-ENOMEM
);
173 memset(dd
, 0, sizeof(*dd
));
176 spin_lock_irqsave(&ipath_devs_lock
, flags
);
178 ret
= idr_get_new(&unit_table
, dd
, &dd
->ipath_unit
);
180 printk(KERN_ERR IPATH_DRV_NAME
181 ": Could not allocate unit ID: error %d\n", -ret
);
182 ipath_free_devdata(pdev
, dd
);
188 pci_set_drvdata(pdev
, dd
);
190 list_add(&dd
->ipath_list
, &ipath_dev_list
);
193 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
199 static inline struct ipath_devdata
*__ipath_lookup(int unit
)
201 return idr_find(&unit_table
, unit
);
204 struct ipath_devdata
*ipath_lookup(int unit
)
206 struct ipath_devdata
*dd
;
209 spin_lock_irqsave(&ipath_devs_lock
, flags
);
210 dd
= __ipath_lookup(unit
);
211 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
216 int ipath_count_units(int *npresentp
, int *nupp
, u32
*maxportsp
)
218 int nunits
, npresent
, nup
;
219 struct ipath_devdata
*dd
;
223 nunits
= npresent
= nup
= maxports
= 0;
225 spin_lock_irqsave(&ipath_devs_lock
, flags
);
227 list_for_each_entry(dd
, &ipath_dev_list
, ipath_list
) {
229 if ((dd
->ipath_flags
& IPATH_PRESENT
) && dd
->ipath_kregbase
)
232 !(dd
->ipath_flags
& (IPATH_DISABLED
| IPATH_LINKDOWN
235 if (dd
->ipath_cfgports
> maxports
)
236 maxports
= dd
->ipath_cfgports
;
239 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
242 *npresentp
= npresent
;
246 *maxportsp
= maxports
;
252 * These next two routines are placeholders in case we don't have per-arch
253 * code for controlling write combining. If explicit control of write
254 * combining is not available, performance will probably be awful.
257 int __attribute__((weak
)) ipath_enable_wc(struct ipath_devdata
*dd
)
262 void __attribute__((weak
)) ipath_disable_wc(struct ipath_devdata
*dd
)
266 static int __devinit
ipath_init_one(struct pci_dev
*pdev
,
267 const struct pci_device_id
*ent
)
270 struct ipath_devdata
*dd
;
271 unsigned long long addr
;
272 u32 bar0
= 0, bar1
= 0;
275 dd
= ipath_alloc_devdata(pdev
);
278 printk(KERN_ERR IPATH_DRV_NAME
279 ": Could not allocate devdata: error %d\n", -ret
);
283 ipath_cdbg(VERBOSE
, "initializing unit #%u\n", dd
->ipath_unit
);
285 read_bars(dd
, pdev
, &bar0
, &bar1
);
287 ret
= pci_enable_device(pdev
);
289 /* This can happen iff:
291 * We did a chip reset, and then failed to reprogram the
292 * BAR, or the chip reset due to an internal error. We then
293 * unloaded the driver and reloaded it.
295 * Both reset cases set the BAR back to initial state. For
296 * the latter case, the AER sticky error bit at offset 0x718
297 * should be set, but the Linux kernel doesn't yet know
298 * about that, it appears. If the original BAR was retained
299 * in the kernel data structures, this may be OK.
301 ipath_dev_err(dd
, "enable unit %d failed: error %d\n",
302 dd
->ipath_unit
, -ret
);
305 addr
= pci_resource_start(pdev
, 0);
306 len
= pci_resource_len(pdev
, 0);
307 ipath_cdbg(VERBOSE
, "regbase (0) %llx len %d pdev->irq %d, vend %x/%x "
308 "driver_data %lx\n", addr
, len
, pdev
->irq
, ent
->vendor
,
309 ent
->device
, ent
->driver_data
);
311 read_bars(dd
, pdev
, &bar0
, &bar1
);
313 if (!bar1
&& !(bar0
& ~0xf)) {
315 dev_info(&pdev
->dev
, "BAR is 0 (probable RESET), "
316 "rewriting as %llx\n", addr
);
317 ret
= pci_write_config_dword(
318 pdev
, PCI_BASE_ADDRESS_0
, addr
);
320 ipath_dev_err(dd
, "rewrite of BAR0 "
321 "failed: err %d\n", -ret
);
324 ret
= pci_write_config_dword(
325 pdev
, PCI_BASE_ADDRESS_1
, addr
>> 32);
327 ipath_dev_err(dd
, "rewrite of BAR1 "
328 "failed: err %d\n", -ret
);
332 ipath_dev_err(dd
, "BAR is 0 (probable RESET), "
333 "not usable until reboot\n");
339 ret
= pci_request_regions(pdev
, IPATH_DRV_NAME
);
341 dev_info(&pdev
->dev
, "pci_request_regions unit %u fails: "
342 "err %d\n", dd
->ipath_unit
, -ret
);
346 ret
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
);
349 * if the 64 bit setup fails, try 32 bit. Some systems
350 * do not setup 64 bit maps on systems with 2GB or less
353 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
356 "Unable to set DMA mask for unit %u: %d\n",
357 dd
->ipath_unit
, ret
);
361 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
362 ret
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
365 "Unable to set DMA consistent mask "
367 dd
->ipath_unit
, ret
);
372 ret
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
375 "Unable to set DMA consistent mask "
377 dd
->ipath_unit
, ret
);
380 pci_set_master(pdev
);
383 * Save BARs to rewrite after device reset. Save all 64 bits of
386 dd
->ipath_pcibar0
= addr
;
387 dd
->ipath_pcibar1
= addr
>> 32;
388 dd
->ipath_deviceid
= ent
->device
; /* save for later use */
389 dd
->ipath_vendorid
= ent
->vendor
;
391 /* setup the chip-specific functions, as early as possible. */
392 switch (ent
->device
) {
393 case PCI_DEVICE_ID_INFINIPATH_HT
:
395 ipath_init_iba6110_funcs(dd
);
398 ipath_dev_err(dd
, "QLogic HT device 0x%x cannot work if "
399 "CONFIG_HT_IRQ is not enabled\n", ent
->device
);
402 case PCI_DEVICE_ID_INFINIPATH_PE800
:
403 #ifdef CONFIG_PCI_MSI
404 ipath_init_iba6120_funcs(dd
);
407 ipath_dev_err(dd
, "QLogic PCIE device 0x%x cannot work if "
408 "CONFIG_PCI_MSI is not enabled\n", ent
->device
);
412 ipath_dev_err(dd
, "Found unknown QLogic deviceid 0x%x, "
413 "failing\n", ent
->device
);
417 for (j
= 0; j
< 6; j
++) {
418 if (!pdev
->resource
[j
].start
)
420 ipath_cdbg(VERBOSE
, "BAR %d start %llx, end %llx, len %llx\n",
421 j
, (unsigned long long)pdev
->resource
[j
].start
,
422 (unsigned long long)pdev
->resource
[j
].end
,
423 (unsigned long long)pci_resource_len(pdev
, j
));
427 ipath_dev_err(dd
, "No valid address in BAR 0!\n");
432 dd
->ipath_deviceid
= ent
->device
; /* save for later use */
433 dd
->ipath_vendorid
= ent
->vendor
;
435 ret
= pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
437 ipath_dev_err(dd
, "Failed to read PCI revision ID unit "
438 "%u: err %d\n", dd
->ipath_unit
, -ret
);
439 goto bail_regions
; /* shouldn't ever happen */
441 dd
->ipath_pcirev
= rev
;
443 #if defined(__powerpc__)
444 /* There isn't a generic way to specify writethrough mappings */
445 dd
->ipath_kregbase
= __ioremap(addr
, len
,
446 (_PAGE_NO_CACHE
|_PAGE_WRITETHRU
));
448 dd
->ipath_kregbase
= ioremap_nocache(addr
, len
);
451 if (!dd
->ipath_kregbase
) {
452 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
457 dd
->ipath_kregend
= (u64 __iomem
*)
458 ((void __iomem
*)dd
->ipath_kregbase
+ len
);
459 dd
->ipath_physaddr
= addr
; /* used for io_remap, etc. */
461 ipath_cdbg(VERBOSE
, "mapped io addr %llx to kregbase %p\n",
462 addr
, dd
->ipath_kregbase
);
465 * clear ipath_flags here instead of in ipath_init_chip as it is set
466 * by ipath_setup_htconfig.
469 dd
->ipath_lli_counter
= 0;
470 dd
->ipath_lli_errors
= 0;
472 if (dd
->ipath_f_bus(dd
, pdev
))
473 ipath_dev_err(dd
, "Failed to setup config space; "
474 "continuing anyway\n");
477 * set up our interrupt handler; IRQF_SHARED probably not needed,
478 * since MSI interrupts shouldn't be shared but won't hurt for now.
479 * check 0 irq after we return from chip-specific bus setup, since
480 * that can affect this due to setup
483 ipath_dev_err(dd
, "irq is 0, BIOS error? Interrupts won't "
486 ret
= request_irq(dd
->ipath_irq
, ipath_intr
, IRQF_SHARED
,
489 ipath_dev_err(dd
, "Couldn't setup irq handler, "
490 "irq=%d: %d\n", dd
->ipath_irq
, ret
);
495 ret
= ipath_init_chip(dd
, 0); /* do the chip-specific init */
499 ret
= ipath_enable_wc(dd
);
502 ipath_dev_err(dd
, "Write combining not enabled "
503 "(err %d): performance may be poor\n",
508 ipath_device_create_group(&pdev
->dev
, dd
);
509 ipathfs_add_device(dd
);
512 ipath_register_ib_device(dd
);
517 if (pdev
->irq
) free_irq(pdev
->irq
, dd
);
520 iounmap((volatile void __iomem
*) dd
->ipath_kregbase
);
523 pci_release_regions(pdev
);
526 pci_disable_device(pdev
);
529 ipath_free_devdata(pdev
, dd
);
535 static void __devexit
cleanup_device(struct ipath_devdata
*dd
)
539 if (*dd
->ipath_statusp
& IPATH_STATUS_CHIP_PRESENT
) {
540 /* can't do anything more with chip; needs re-init */
541 *dd
->ipath_statusp
&= ~IPATH_STATUS_CHIP_PRESENT
;
542 if (dd
->ipath_kregbase
) {
544 * if we haven't already cleaned up before these are
545 * to ensure any register reads/writes "fail" until
548 dd
->ipath_kregbase
= NULL
;
549 dd
->ipath_uregbase
= 0;
550 dd
->ipath_sregbase
= 0;
551 dd
->ipath_cregbase
= 0;
552 dd
->ipath_kregsize
= 0;
554 ipath_disable_wc(dd
);
557 if (dd
->ipath_pioavailregs_dma
) {
558 dma_free_coherent(&dd
->pcidev
->dev
, PAGE_SIZE
,
559 (void *) dd
->ipath_pioavailregs_dma
,
560 dd
->ipath_pioavailregs_phys
);
561 dd
->ipath_pioavailregs_dma
= NULL
;
563 if (dd
->ipath_dummy_hdrq
) {
564 dma_free_coherent(&dd
->pcidev
->dev
,
565 dd
->ipath_pd
[0]->port_rcvhdrq_size
,
566 dd
->ipath_dummy_hdrq
, dd
->ipath_dummy_hdrq_phys
);
567 dd
->ipath_dummy_hdrq
= NULL
;
570 if (dd
->ipath_pageshadow
) {
571 struct page
**tmpp
= dd
->ipath_pageshadow
;
572 dma_addr_t
*tmpd
= dd
->ipath_physshadow
;
575 ipath_cdbg(VERBOSE
, "Unlocking any expTID pages still "
577 for (port
= 0; port
< dd
->ipath_cfgports
; port
++) {
578 int port_tidbase
= port
* dd
->ipath_rcvtidcnt
;
579 int maxtid
= port_tidbase
+ dd
->ipath_rcvtidcnt
;
580 for (i
= port_tidbase
; i
< maxtid
; i
++) {
583 pci_unmap_page(dd
->pcidev
, tmpd
[i
],
584 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
585 ipath_release_user_pages(&tmpp
[i
], 1);
591 ipath_stats
.sps_pageunlocks
+= cnt
;
592 ipath_cdbg(VERBOSE
, "There were still %u expTID "
593 "entries locked\n", cnt
);
595 if (ipath_stats
.sps_pagelocks
||
596 ipath_stats
.sps_pageunlocks
)
597 ipath_cdbg(VERBOSE
, "%llu pages locked, %llu "
598 "unlocked via ipath_m{un}lock\n",
600 ipath_stats
.sps_pagelocks
,
602 ipath_stats
.sps_pageunlocks
);
604 ipath_cdbg(VERBOSE
, "Free shadow page tid array at %p\n",
605 dd
->ipath_pageshadow
);
606 tmpp
= dd
->ipath_pageshadow
;
607 dd
->ipath_pageshadow
= NULL
;
612 * free any resources still in use (usually just kernel ports)
613 * at unload; we do for portcnt, not cfgports, because cfgports
614 * could have changed while we were loaded.
616 for (port
= 0; port
< dd
->ipath_portcnt
; port
++) {
617 struct ipath_portdata
*pd
= dd
->ipath_pd
[port
];
618 dd
->ipath_pd
[port
] = NULL
;
619 ipath_free_pddata(dd
, pd
);
623 * debuggability, in case some cleanup path tries to use it
629 static void __devexit
ipath_remove_one(struct pci_dev
*pdev
)
631 struct ipath_devdata
*dd
= pci_get_drvdata(pdev
);
633 ipath_cdbg(VERBOSE
, "removing, pdev=%p, dd=%p\n", pdev
, dd
);
636 * disable the IB link early, to be sure no new packets arrive, which
637 * complicates the shutdown process
639 ipath_shutdown_device(dd
);
642 ipath_unregister_ib_device(dd
->verbs_dev
);
644 ipath_diag_remove(dd
);
645 ipath_user_remove(dd
);
646 ipathfs_remove_device(dd
);
647 ipath_device_remove_group(&pdev
->dev
, dd
);
649 ipath_cdbg(VERBOSE
, "Releasing pci memory regions, dd %p, "
650 "unit %u\n", dd
, (u32
) dd
->ipath_unit
);
655 * turn off rcv, send, and interrupts for all ports, all drivers
656 * should also hard reset the chip here?
657 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
658 * for all versions of the driver, if they were allocated
661 ipath_cdbg(VERBOSE
, "unit %u free irq %d\n",
662 dd
->ipath_unit
, dd
->ipath_irq
);
663 dd
->ipath_f_free_irq(dd
);
665 ipath_dbg("irq is 0, not doing free_irq "
666 "for unit %u\n", dd
->ipath_unit
);
668 * we check for NULL here, because it's outside
669 * the kregbase check, and we need to call it
670 * after the free_irq. Thus it's possible that
671 * the function pointers were never initialized.
673 if (dd
->ipath_f_cleanup
)
674 /* clean up chip-specific stuff */
675 dd
->ipath_f_cleanup(dd
);
677 ipath_cdbg(VERBOSE
, "Unmapping kregbase %p\n", dd
->ipath_kregbase
);
678 iounmap((volatile void __iomem
*) dd
->ipath_kregbase
);
679 pci_release_regions(pdev
);
680 ipath_cdbg(VERBOSE
, "calling pci_disable_device\n");
681 pci_disable_device(pdev
);
683 ipath_free_devdata(pdev
, dd
);
686 /* general driver use */
687 DEFINE_MUTEX(ipath_mutex
);
689 static DEFINE_SPINLOCK(ipath_pioavail_lock
);
692 * ipath_disarm_piobufs - cancel a range of PIO buffers
693 * @dd: the infinipath device
694 * @first: the first PIO buffer to cancel
695 * @cnt: the number of PIO buffers to cancel
697 * cancel a range of PIO buffers, used when they might be armed, but
698 * not triggered. Used at init to ensure buffer state, and also user
699 * process close, in case it died while writing to a PIO buffer
702 void ipath_disarm_piobufs(struct ipath_devdata
*dd
, unsigned first
,
705 unsigned i
, last
= first
+ cnt
;
706 u64 sendctrl
, sendorig
;
708 ipath_cdbg(PKT
, "disarm %u PIObufs first=%u\n", cnt
, first
);
709 sendorig
= dd
->ipath_sendctrl
;
710 for (i
= first
; i
< last
; i
++) {
711 sendctrl
= sendorig
| INFINIPATH_S_DISARM
|
712 (i
<< INFINIPATH_S_DISARMPIOBUF_SHIFT
);
713 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
718 * Write it again with current value, in case ipath_sendctrl changed
719 * while we were looping; no critical bits that would require
722 * disable PIOAVAILUPD, then re-enable, reading scratch in
723 * between. This seems to avoid a chip timing race that causes
724 * pioavail updates to memory to stop.
726 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
727 sendorig
& ~IPATH_S_PIOBUFAVAILUPD
);
728 sendorig
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
729 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
734 * ipath_wait_linkstate - wait for an IB link state change to occur
735 * @dd: the infinipath device
736 * @state: the state to wait for
737 * @msecs: the number of milliseconds to wait
739 * wait up to msecs milliseconds for IB link state change to occur for
740 * now, take the easy polling route. Currently used only by
741 * ipath_set_linkstate. Returns 0 if state reached, otherwise
742 * -ETIMEDOUT state can have multiple states set, for any of several
745 static int ipath_wait_linkstate(struct ipath_devdata
*dd
, u32 state
,
748 dd
->ipath_state_wanted
= state
;
749 wait_event_interruptible_timeout(ipath_state_wait
,
750 (dd
->ipath_flags
& state
),
751 msecs_to_jiffies(msecs
));
752 dd
->ipath_state_wanted
= 0;
754 if (!(dd
->ipath_flags
& state
)) {
756 ipath_cdbg(VERBOSE
, "Didn't reach linkstate %s within %u"
758 /* test INIT ahead of DOWN, both can be set */
759 (state
& IPATH_LINKINIT
) ? "INIT" :
760 ((state
& IPATH_LINKDOWN
) ? "DOWN" :
761 ((state
& IPATH_LINKARMED
) ? "ARM" : "ACTIVE")),
763 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_ibcstatus
);
764 ipath_cdbg(VERBOSE
, "ibcc=%llx ibcstatus=%llx (%s)\n",
765 (unsigned long long) ipath_read_kreg64(
766 dd
, dd
->ipath_kregs
->kr_ibcctrl
),
767 (unsigned long long) val
,
768 ipath_ibcstatus_str
[val
& 0xf]);
770 return (dd
->ipath_flags
& state
) ? 0 : -ETIMEDOUT
;
774 * Decode the error status into strings, deciding whether to always
775 * print * it or not depending on "normal packet errors" vs everything
776 * else. Return 1 if "real" errors, otherwise 0 if only packet
777 * errors, so caller can decide what to print with the string.
779 int ipath_decode_err(char *buf
, size_t blen
, ipath_err_t err
)
783 if (err
& INFINIPATH_E_PKTERRS
) {
784 if (!(err
& ~INFINIPATH_E_PKTERRS
))
785 iserr
= 0; // if only packet errors.
786 if (ipath_debug
& __IPATH_ERRPKTDBG
) {
787 if (err
& INFINIPATH_E_REBP
)
788 strlcat(buf
, "EBP ", blen
);
789 if (err
& INFINIPATH_E_RVCRC
)
790 strlcat(buf
, "VCRC ", blen
);
791 if (err
& INFINIPATH_E_RICRC
) {
792 strlcat(buf
, "CRC ", blen
);
793 // clear for check below, so only once
794 err
&= INFINIPATH_E_RICRC
;
796 if (err
& INFINIPATH_E_RSHORTPKTLEN
)
797 strlcat(buf
, "rshortpktlen ", blen
);
798 if (err
& INFINIPATH_E_SDROPPEDDATAPKT
)
799 strlcat(buf
, "sdroppeddatapkt ", blen
);
800 if (err
& INFINIPATH_E_SPKTLEN
)
801 strlcat(buf
, "spktlen ", blen
);
803 if ((err
& INFINIPATH_E_RICRC
) &&
804 !(err
&(INFINIPATH_E_RVCRC
|INFINIPATH_E_REBP
)))
805 strlcat(buf
, "CRC ", blen
);
809 if (err
& INFINIPATH_E_RHDRLEN
)
810 strlcat(buf
, "rhdrlen ", blen
);
811 if (err
& INFINIPATH_E_RBADTID
)
812 strlcat(buf
, "rbadtid ", blen
);
813 if (err
& INFINIPATH_E_RBADVERSION
)
814 strlcat(buf
, "rbadversion ", blen
);
815 if (err
& INFINIPATH_E_RHDR
)
816 strlcat(buf
, "rhdr ", blen
);
817 if (err
& INFINIPATH_E_RLONGPKTLEN
)
818 strlcat(buf
, "rlongpktlen ", blen
);
819 if (err
& INFINIPATH_E_RMAXPKTLEN
)
820 strlcat(buf
, "rmaxpktlen ", blen
);
821 if (err
& INFINIPATH_E_RMINPKTLEN
)
822 strlcat(buf
, "rminpktlen ", blen
);
823 if (err
& INFINIPATH_E_SMINPKTLEN
)
824 strlcat(buf
, "sminpktlen ", blen
);
825 if (err
& INFINIPATH_E_RFORMATERR
)
826 strlcat(buf
, "rformaterr ", blen
);
827 if (err
& INFINIPATH_E_RUNSUPVL
)
828 strlcat(buf
, "runsupvl ", blen
);
829 if (err
& INFINIPATH_E_RUNEXPCHAR
)
830 strlcat(buf
, "runexpchar ", blen
);
831 if (err
& INFINIPATH_E_RIBFLOW
)
832 strlcat(buf
, "ribflow ", blen
);
833 if (err
& INFINIPATH_E_SUNDERRUN
)
834 strlcat(buf
, "sunderrun ", blen
);
835 if (err
& INFINIPATH_E_SPIOARMLAUNCH
)
836 strlcat(buf
, "spioarmlaunch ", blen
);
837 if (err
& INFINIPATH_E_SUNEXPERRPKTNUM
)
838 strlcat(buf
, "sunexperrpktnum ", blen
);
839 if (err
& INFINIPATH_E_SDROPPEDSMPPKT
)
840 strlcat(buf
, "sdroppedsmppkt ", blen
);
841 if (err
& INFINIPATH_E_SMAXPKTLEN
)
842 strlcat(buf
, "smaxpktlen ", blen
);
843 if (err
& INFINIPATH_E_SUNSUPVL
)
844 strlcat(buf
, "sunsupVL ", blen
);
845 if (err
& INFINIPATH_E_INVALIDADDR
)
846 strlcat(buf
, "invalidaddr ", blen
);
847 if (err
& INFINIPATH_E_RRCVEGRFULL
)
848 strlcat(buf
, "rcvegrfull ", blen
);
849 if (err
& INFINIPATH_E_RRCVHDRFULL
)
850 strlcat(buf
, "rcvhdrfull ", blen
);
851 if (err
& INFINIPATH_E_IBSTATUSCHANGED
)
852 strlcat(buf
, "ibcstatuschg ", blen
);
853 if (err
& INFINIPATH_E_RIBLOSTLINK
)
854 strlcat(buf
, "riblostlink ", blen
);
855 if (err
& INFINIPATH_E_HARDWARE
)
856 strlcat(buf
, "hardware ", blen
);
857 if (err
& INFINIPATH_E_RESET
)
858 strlcat(buf
, "reset ", blen
);
864 * get_rhf_errstring - decode RHF errors
865 * @err: the err number
866 * @msg: the output buffer
867 * @len: the length of the output buffer
869 * only used one place now, may want more later
871 static void get_rhf_errstring(u32 err
, char *msg
, size_t len
)
873 /* if no errors, and so don't need to check what's first */
876 if (err
& INFINIPATH_RHF_H_ICRCERR
)
877 strlcat(msg
, "icrcerr ", len
);
878 if (err
& INFINIPATH_RHF_H_VCRCERR
)
879 strlcat(msg
, "vcrcerr ", len
);
880 if (err
& INFINIPATH_RHF_H_PARITYERR
)
881 strlcat(msg
, "parityerr ", len
);
882 if (err
& INFINIPATH_RHF_H_LENERR
)
883 strlcat(msg
, "lenerr ", len
);
884 if (err
& INFINIPATH_RHF_H_MTUERR
)
885 strlcat(msg
, "mtuerr ", len
);
886 if (err
& INFINIPATH_RHF_H_IHDRERR
)
887 /* infinipath hdr checksum error */
888 strlcat(msg
, "ipathhdrerr ", len
);
889 if (err
& INFINIPATH_RHF_H_TIDERR
)
890 strlcat(msg
, "tiderr ", len
);
891 if (err
& INFINIPATH_RHF_H_MKERR
)
892 /* bad port, offset, etc. */
893 strlcat(msg
, "invalid ipathhdr ", len
);
894 if (err
& INFINIPATH_RHF_H_IBERR
)
895 strlcat(msg
, "iberr ", len
);
896 if (err
& INFINIPATH_RHF_L_SWA
)
897 strlcat(msg
, "swA ", len
);
898 if (err
& INFINIPATH_RHF_L_SWB
)
899 strlcat(msg
, "swB ", len
);
903 * ipath_get_egrbuf - get an eager buffer
904 * @dd: the infinipath device
905 * @bufnum: the eager buffer to get
908 * must only be called if ipath_pd[port] is known to be allocated
910 static inline void *ipath_get_egrbuf(struct ipath_devdata
*dd
, u32 bufnum
,
913 return dd
->ipath_port0_skbinfo
?
914 (void *) dd
->ipath_port0_skbinfo
[bufnum
].skb
->data
: NULL
;
918 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
919 * @dd: the infinipath device
920 * @gfp_mask: the sk_buff SFP mask
922 struct sk_buff
*ipath_alloc_skb(struct ipath_devdata
*dd
,
929 * Only fully supported way to handle this is to allocate lots
930 * extra, align as needed, and then do skb_reserve(). That wastes
931 * a lot of memory... I'll have to hack this into infinipath_copy
936 * We need 2 extra bytes for ipath_ether data sent in the
937 * key header. In order to keep everything dword aligned,
938 * we'll reserve 4 bytes.
940 len
= dd
->ipath_ibmaxlen
+ 4;
942 if (dd
->ipath_flags
& IPATH_4BYTE_TID
) {
943 /* We need a 2KB multiple alignment, and there is no way
944 * to do it except to allocate extra and then skb_reserve
945 * enough to bring it up to the right alignment.
950 skb
= __dev_alloc_skb(len
, gfp_mask
);
952 ipath_dev_err(dd
, "Failed to allocate skbuff, length %u\n",
959 if (dd
->ipath_flags
& IPATH_4BYTE_TID
) {
960 u32 una
= (unsigned long)skb
->data
& 2047;
962 skb_reserve(skb
, 2048 - una
);
969 static void ipath_rcv_hdrerr(struct ipath_devdata
*dd
,
976 struct ipath_message_header
*hdr
;
978 get_rhf_errstring(eflags
, emsg
, sizeof emsg
);
979 hdr
= (struct ipath_message_header
*)&rc
[1];
980 ipath_cdbg(PKT
, "RHFerrs %x hdrqtail=%x typ=%u "
981 "tlen=%x opcode=%x egridx=%x: %s\n",
983 ipath_hdrget_rcv_type((__le32
*) rc
),
984 ipath_hdrget_length_in_bytes((__le32
*) rc
),
985 be32_to_cpu(hdr
->bth
[0]) >> 24,
988 /* Count local link integrity errors. */
989 if (eflags
& (INFINIPATH_RHF_H_ICRCERR
| INFINIPATH_RHF_H_VCRCERR
)) {
990 u8 n
= (dd
->ipath_ibcctrl
>>
991 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT
) &
992 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK
;
994 if (++dd
->ipath_lli_counter
> n
) {
995 dd
->ipath_lli_counter
= 0;
996 dd
->ipath_lli_errors
++;
1002 * ipath_kreceive - receive a packet
1003 * @dd: the infinipath device
1005 * called from interrupt handler for errors or receive interrupt
1007 void ipath_kreceive(struct ipath_devdata
*dd
)
1011 const u32 rsize
= dd
->ipath_rcvhdrentsize
; /* words */
1012 const u32 maxcnt
= dd
->ipath_rcvhdrcnt
* rsize
; /* words */
1013 u32 etail
= -1, l
, hdrqtail
;
1014 struct ipath_message_header
*hdr
;
1015 u32 eflags
, i
, etype
, tlen
, pkttot
= 0, updegr
=0, reloop
=0;
1016 static u64 totcalls
; /* stats, may eventually remove */
1018 if (!dd
->ipath_hdrqtailptr
) {
1020 "hdrqtailptr not set, can't do receives\n");
1024 l
= dd
->ipath_port0head
;
1025 hdrqtail
= (u32
) le64_to_cpu(*dd
->ipath_hdrqtailptr
);
1030 for (i
= 0; l
!= hdrqtail
; i
++) {
1034 rc
= (u64
*) (dd
->ipath_pd
[0]->port_rcvhdrq
+ (l
<< 2));
1035 hdr
= (struct ipath_message_header
*)&rc
[1];
1037 * could make a network order version of IPATH_KD_QP, and
1038 * do the obvious shift before masking to speed this up.
1040 qp
= ntohl(hdr
->bth
[1]) & 0xffffff;
1041 bthbytes
= (u8
*) hdr
->bth
;
1043 eflags
= ipath_hdrget_err_flags((__le32
*) rc
);
1044 etype
= ipath_hdrget_rcv_type((__le32
*) rc
);
1046 tlen
= ipath_hdrget_length_in_bytes((__le32
*) rc
);
1048 if (etype
!= RCVHQ_RCV_TYPE_EXPECTED
) {
1050 * it turns out that the chips uses an eager buffer
1051 * for all non-expected packets, whether it "needs"
1052 * one or not. So always get the index, but don't
1053 * set ebuf (so we try to copy data) unless the
1054 * length requires it.
1056 etail
= ipath_hdrget_index((__le32
*) rc
);
1057 if (tlen
> sizeof(*hdr
) ||
1058 etype
== RCVHQ_RCV_TYPE_NON_KD
)
1059 ebuf
= ipath_get_egrbuf(dd
, etail
, 0);
1063 * both tiderr and ipathhdrerr are set for all plain IB
1064 * packets; only ipathhdrerr should be set.
1067 if (etype
!= RCVHQ_RCV_TYPE_NON_KD
&& etype
!=
1068 RCVHQ_RCV_TYPE_ERROR
&& ipath_hdrget_ipath_ver(
1069 hdr
->iph
.ver_port_tid_offset
) !=
1070 IPS_PROTO_VERSION
) {
1071 ipath_cdbg(PKT
, "Bad InfiniPath protocol version "
1075 if (unlikely(eflags
))
1076 ipath_rcv_hdrerr(dd
, eflags
, l
, etail
, rc
);
1077 else if (etype
== RCVHQ_RCV_TYPE_NON_KD
) {
1078 ipath_ib_rcv(dd
->verbs_dev
, rc
+ 1, ebuf
, tlen
);
1079 if (dd
->ipath_lli_counter
)
1080 dd
->ipath_lli_counter
--;
1081 ipath_cdbg(PKT
, "typ %x, opcode %x (eager, "
1082 "qp=%x), len %x; ignored\n",
1083 etype
, bthbytes
[0], qp
, tlen
);
1085 else if (etype
== RCVHQ_RCV_TYPE_EAGER
)
1086 ipath_cdbg(PKT
, "typ %x, opcode %x (eager, "
1087 "qp=%x), len %x; ignored\n",
1088 etype
, bthbytes
[0], qp
, tlen
);
1089 else if (etype
== RCVHQ_RCV_TYPE_EXPECTED
)
1090 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1091 be32_to_cpu(hdr
->bth
[0]) & 0xff);
1094 * error packet, type of error unknown.
1095 * Probably type 3, but we don't know, so don't
1096 * even try to print the opcode, etc.
1098 ipath_dbg("Error Pkt, but no eflags! egrbuf %x, "
1099 "len %x\nhdrq@%lx;hdrq+%x rhf: %llx; "
1100 "hdr %llx %llx %llx %llx %llx\n",
1101 etail
, tlen
, (unsigned long) rc
, l
,
1102 (unsigned long long) rc
[0],
1103 (unsigned long long) rc
[1],
1104 (unsigned long long) rc
[2],
1105 (unsigned long long) rc
[3],
1106 (unsigned long long) rc
[4],
1107 (unsigned long long) rc
[5]);
1112 if (etype
!= RCVHQ_RCV_TYPE_EXPECTED
)
1115 * update head regs on last packet, and every 16 packets.
1116 * Reduce bus traffic, while still trying to prevent
1117 * rcvhdrq overflows, for when the queue is nearly full
1119 if (l
== hdrqtail
|| (i
&& !(i
&0xf))) {
1122 /* request IBA6120 interrupt only on last */
1123 lval
= dd
->ipath_rhdrhead_intr_off
| l
;
1126 (void)ipath_write_ureg(dd
, ur_rcvhdrhead
, lval
, 0);
1128 (void)ipath_write_ureg(dd
, ur_rcvegrindexhead
,
1135 if (!dd
->ipath_rhdrhead_intr_off
&& !reloop
) {
1136 /* IBA6110 workaround; we can have a race clearing chip
1137 * interrupt with another interrupt about to be delivered,
1138 * and can clear it before it is delivered on the GPIO
1139 * workaround. By doing the extra check here for the
1140 * in-memory tail register updating while we were doing
1141 * earlier packets, we "almost" guarantee we have covered
1144 u32 hqtail
= (u32
)le64_to_cpu(*dd
->ipath_hdrqtailptr
);
1145 if (hqtail
!= hdrqtail
) {
1147 reloop
= 1; /* loop 1 extra time at most */
1154 dd
->ipath_port0head
= l
;
1156 if (pkttot
> ipath_stats
.sps_maxpkts_call
)
1157 ipath_stats
.sps_maxpkts_call
= pkttot
;
1158 ipath_stats
.sps_port0pkts
+= pkttot
;
1159 ipath_stats
.sps_avgpkts_call
=
1160 ipath_stats
.sps_port0pkts
/ ++totcalls
;
1166 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1167 * @dd: the infinipath device
1169 * called whenever our local copy indicates we have run out of send buffers
1170 * NOTE: This can be called from interrupt context by some code
1171 * and from non-interrupt context by ipath_getpiobuf().
1174 static void ipath_update_pio_bufs(struct ipath_devdata
*dd
)
1176 unsigned long flags
;
1178 const unsigned piobregs
= (unsigned)dd
->ipath_pioavregs
;
1180 /* If the generation (check) bits have changed, then we update the
1181 * busy bit for the corresponding PIO buffer. This algorithm will
1182 * modify positions to the value they already have in some cases
1183 * (i.e., no change), but it's faster than changing only the bits
1184 * that have changed.
1186 * We would like to do this atomicly, to avoid spinlocks in the
1187 * critical send path, but that's not really possible, given the
1188 * type of changes, and that this routine could be called on
1189 * multiple cpu's simultaneously, so we lock in this routine only,
1190 * to avoid conflicting updates; all we change is the shadow, and
1191 * it's a single 64 bit memory location, so by definition the update
1192 * is atomic in terms of what other cpu's can see in testing the
1193 * bits. The spin_lock overhead isn't too bad, since it only
1194 * happens when all buffers are in use, so only cpu overhead, not
1195 * latency or bandwidth is affected.
1197 #define _IPATH_ALL_CHECKBITS 0x5555555555555555ULL
1198 if (!dd
->ipath_pioavailregs_dma
) {
1199 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1202 if (ipath_debug
& __IPATH_VERBDBG
) {
1203 /* only if packet debug and verbose */
1204 volatile __le64
*dma
= dd
->ipath_pioavailregs_dma
;
1205 unsigned long *shadow
= dd
->ipath_pioavailshadow
;
1207 ipath_cdbg(PKT
, "Refill avail, dma0=%llx shad0=%lx, "
1208 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1210 (unsigned long long) le64_to_cpu(dma
[0]),
1212 (unsigned long long) le64_to_cpu(dma
[1]),
1214 (unsigned long long) le64_to_cpu(dma
[2]),
1216 (unsigned long long) le64_to_cpu(dma
[3]),
1220 PKT
, "2nd group, dma4=%llx shad4=%lx, "
1221 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1223 (unsigned long long) le64_to_cpu(dma
[4]),
1225 (unsigned long long) le64_to_cpu(dma
[5]),
1227 (unsigned long long) le64_to_cpu(dma
[6]),
1229 (unsigned long long) le64_to_cpu(dma
[7]),
1232 spin_lock_irqsave(&ipath_pioavail_lock
, flags
);
1233 for (i
= 0; i
< piobregs
; i
++) {
1234 u64 pchbusy
, pchg
, piov
, pnew
;
1236 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1241 dd
->ipath_pioavailregs_dma
[i
- 1]);
1244 dd
->ipath_pioavailregs_dma
[i
+ 1]);
1246 piov
= le64_to_cpu(dd
->ipath_pioavailregs_dma
[i
]);
1247 pchg
= _IPATH_ALL_CHECKBITS
&
1248 ~(dd
->ipath_pioavailshadow
[i
] ^ piov
);
1249 pchbusy
= pchg
<< INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
;
1250 if (pchg
&& (pchbusy
& dd
->ipath_pioavailshadow
[i
])) {
1251 pnew
= dd
->ipath_pioavailshadow
[i
] & ~pchbusy
;
1252 pnew
|= piov
& pchbusy
;
1253 dd
->ipath_pioavailshadow
[i
] = pnew
;
1256 spin_unlock_irqrestore(&ipath_pioavail_lock
, flags
);
1260 * ipath_setrcvhdrsize - set the receive header size
1261 * @dd: the infinipath device
1262 * @rhdrsize: the receive header size
1264 * called from user init code, and also layered driver init
1266 int ipath_setrcvhdrsize(struct ipath_devdata
*dd
, unsigned rhdrsize
)
1270 if (dd
->ipath_flags
& IPATH_RCVHDRSZ_SET
) {
1271 if (dd
->ipath_rcvhdrsize
!= rhdrsize
) {
1272 dev_info(&dd
->pcidev
->dev
,
1273 "Error: can't set protocol header "
1274 "size %u, already %u\n",
1275 rhdrsize
, dd
->ipath_rcvhdrsize
);
1278 ipath_cdbg(VERBOSE
, "Reuse same protocol header "
1279 "size %u\n", dd
->ipath_rcvhdrsize
);
1280 } else if (rhdrsize
> (dd
->ipath_rcvhdrentsize
-
1281 (sizeof(u64
) / sizeof(u32
)))) {
1282 ipath_dbg("Error: can't set protocol header size %u "
1283 "(> max %u)\n", rhdrsize
,
1284 dd
->ipath_rcvhdrentsize
-
1285 (u32
) (sizeof(u64
) / sizeof(u32
)));
1288 dd
->ipath_flags
|= IPATH_RCVHDRSZ_SET
;
1289 dd
->ipath_rcvhdrsize
= rhdrsize
;
1290 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvhdrsize
,
1291 dd
->ipath_rcvhdrsize
);
1292 ipath_cdbg(VERBOSE
, "Set protocol header size to %u\n",
1293 dd
->ipath_rcvhdrsize
);
1299 * ipath_getpiobuf - find an available pio buffer
1300 * @dd: the infinipath device
1301 * @pbufnum: the buffer number is placed here
1303 * do appropriate marking as busy, etc.
1304 * returns buffer number if one found (>=0), negative number is error.
1305 * Used by ipath_layer_send
1307 u32 __iomem
*ipath_getpiobuf(struct ipath_devdata
*dd
, u32
* pbufnum
)
1309 int i
, j
, starti
, updated
= 0;
1310 unsigned piobcnt
, iter
;
1311 unsigned long flags
;
1312 unsigned long *shadow
= dd
->ipath_pioavailshadow
;
1315 piobcnt
= (unsigned)(dd
->ipath_piobcnt2k
1316 + dd
->ipath_piobcnt4k
);
1317 starti
= dd
->ipath_lastport_piobuf
;
1318 iter
= piobcnt
- starti
;
1319 if (dd
->ipath_upd_pio_shadow
) {
1321 * Minor optimization. If we had no buffers on last call,
1322 * start out by doing the update; continue and do scan even
1323 * if no buffers were updated, to be paranoid
1325 ipath_update_pio_bufs(dd
);
1326 /* we scanned here, don't do it at end of scan */
1330 i
= dd
->ipath_lastpioindex
;
1334 * while test_and_set_bit() is atomic, we do that and then the
1335 * change_bit(), and the pair is not. See if this is the cause
1336 * of the remaining armlaunch errors.
1338 spin_lock_irqsave(&ipath_pioavail_lock
, flags
);
1339 for (j
= 0; j
< iter
; j
++, i
++) {
1343 * To avoid bus lock overhead, we first find a candidate
1344 * buffer, then do the test and set, and continue if that
1347 if (test_bit((2 * i
) + 1, shadow
) ||
1348 test_and_set_bit((2 * i
) + 1, shadow
))
1350 /* flip generation bit */
1351 change_bit(2 * i
, shadow
);
1354 spin_unlock_irqrestore(&ipath_pioavail_lock
, flags
);
1357 volatile __le64
*dma
= dd
->ipath_pioavailregs_dma
;
1360 * first time through; shadow exhausted, but may be real
1361 * buffers available, so go see; if any updated, rescan
1365 ipath_update_pio_bufs(dd
);
1370 dd
->ipath_upd_pio_shadow
= 1;
1372 * not atomic, but if we lose one once in a while, that's OK
1374 ipath_stats
.sps_nopiobufs
++;
1375 if (!(++dd
->ipath_consec_nopiobuf
% 100000)) {
1377 "%u pio sends with no bufavail; dmacopy: "
1378 "%llx %llx %llx %llx; shadow: "
1379 "%lx %lx %lx %lx\n",
1380 dd
->ipath_consec_nopiobuf
,
1381 (unsigned long long) le64_to_cpu(dma
[0]),
1382 (unsigned long long) le64_to_cpu(dma
[1]),
1383 (unsigned long long) le64_to_cpu(dma
[2]),
1384 (unsigned long long) le64_to_cpu(dma
[3]),
1385 shadow
[0], shadow
[1], shadow
[2],
1388 * 4 buffers per byte, 4 registers above, cover rest
1391 if ((dd
->ipath_piobcnt2k
+ dd
->ipath_piobcnt4k
) >
1392 (sizeof(shadow
[0]) * 4 * 4))
1393 ipath_dbg("2nd group: dmacopy: %llx %llx "
1394 "%llx %llx; shadow: %lx %lx "
1396 (unsigned long long)
1397 le64_to_cpu(dma
[4]),
1398 (unsigned long long)
1399 le64_to_cpu(dma
[5]),
1400 (unsigned long long)
1401 le64_to_cpu(dma
[6]),
1402 (unsigned long long)
1403 le64_to_cpu(dma
[7]),
1404 shadow
[4], shadow
[5],
1405 shadow
[6], shadow
[7]);
1412 * set next starting place. Since it's just an optimization,
1413 * it doesn't matter who wins on this, so no locking
1415 dd
->ipath_lastpioindex
= i
+ 1;
1416 if (dd
->ipath_upd_pio_shadow
)
1417 dd
->ipath_upd_pio_shadow
= 0;
1418 if (dd
->ipath_consec_nopiobuf
)
1419 dd
->ipath_consec_nopiobuf
= 0;
1420 if (i
< dd
->ipath_piobcnt2k
)
1421 buf
= (u32 __iomem
*) (dd
->ipath_pio2kbase
+
1422 i
* dd
->ipath_palign
);
1424 buf
= (u32 __iomem
*)
1425 (dd
->ipath_pio4kbase
+
1426 (i
- dd
->ipath_piobcnt2k
) * dd
->ipath_4kalign
);
1427 ipath_cdbg(VERBOSE
, "Return piobuf%u %uk @ %p\n",
1428 i
, (i
< dd
->ipath_piobcnt2k
) ? 2 : 4, buf
);
1437 * ipath_create_rcvhdrq - create a receive header queue
1438 * @dd: the infinipath device
1439 * @pd: the port data
1441 * this must be contiguous memory (from an i/o perspective), and must be
1442 * DMA'able (which means for some systems, it will go through an IOMMU,
1443 * or be forced into a low address range).
1445 int ipath_create_rcvhdrq(struct ipath_devdata
*dd
,
1446 struct ipath_portdata
*pd
)
1450 if (!pd
->port_rcvhdrq
) {
1451 dma_addr_t phys_hdrqtail
;
1452 gfp_t gfp_flags
= GFP_USER
| __GFP_COMP
;
1453 int amt
= ALIGN(dd
->ipath_rcvhdrcnt
* dd
->ipath_rcvhdrentsize
*
1454 sizeof(u32
), PAGE_SIZE
);
1456 pd
->port_rcvhdrq
= dma_alloc_coherent(
1457 &dd
->pcidev
->dev
, amt
, &pd
->port_rcvhdrq_phys
,
1460 if (!pd
->port_rcvhdrq
) {
1461 ipath_dev_err(dd
, "attempt to allocate %d bytes "
1462 "for port %u rcvhdrq failed\n",
1463 amt
, pd
->port_port
);
1467 pd
->port_rcvhdrtail_kvaddr
= dma_alloc_coherent(
1468 &dd
->pcidev
->dev
, PAGE_SIZE
, &phys_hdrqtail
, GFP_KERNEL
);
1469 if (!pd
->port_rcvhdrtail_kvaddr
) {
1470 ipath_dev_err(dd
, "attempt to allocate 1 page "
1471 "for port %u rcvhdrqtailaddr failed\n",
1474 dma_free_coherent(&dd
->pcidev
->dev
, amt
,
1475 pd
->port_rcvhdrq
, pd
->port_rcvhdrq_phys
);
1476 pd
->port_rcvhdrq
= NULL
;
1479 pd
->port_rcvhdrqtailaddr_phys
= phys_hdrqtail
;
1481 pd
->port_rcvhdrq_size
= amt
;
1483 ipath_cdbg(VERBOSE
, "%d pages at %p (phys %lx) size=%lu "
1484 "for port %u rcvhdr Q\n",
1485 amt
>> PAGE_SHIFT
, pd
->port_rcvhdrq
,
1486 (unsigned long) pd
->port_rcvhdrq_phys
,
1487 (unsigned long) pd
->port_rcvhdrq_size
,
1490 ipath_cdbg(VERBOSE
, "port %d hdrtailaddr, %llx physical\n",
1492 (unsigned long long) phys_hdrqtail
);
1495 ipath_cdbg(VERBOSE
, "reuse port %d rcvhdrq @%p %llx phys; "
1496 "hdrtailaddr@%p %llx physical\n",
1497 pd
->port_port
, pd
->port_rcvhdrq
,
1498 (unsigned long long) pd
->port_rcvhdrq_phys
,
1499 pd
->port_rcvhdrtail_kvaddr
, (unsigned long long)
1500 pd
->port_rcvhdrqtailaddr_phys
);
1502 /* clear for security and sanity on each use */
1503 memset(pd
->port_rcvhdrq
, 0, pd
->port_rcvhdrq_size
);
1504 memset(pd
->port_rcvhdrtail_kvaddr
, 0, PAGE_SIZE
);
1507 * tell chip each time we init it, even if we are re-using previous
1508 * memory (we zero the register at process close)
1510 ipath_write_kreg_port(dd
, dd
->ipath_kregs
->kr_rcvhdrtailaddr
,
1511 pd
->port_port
, pd
->port_rcvhdrqtailaddr_phys
);
1512 ipath_write_kreg_port(dd
, dd
->ipath_kregs
->kr_rcvhdraddr
,
1513 pd
->port_port
, pd
->port_rcvhdrq_phys
);
1520 int ipath_waitfor_complete(struct ipath_devdata
*dd
, ipath_kreg reg_id
,
1521 u64 bits_to_wait_for
, u64
* valp
)
1523 unsigned long timeout
;
1527 lastval
= ipath_read_kreg64(dd
, reg_id
);
1528 /* wait a ridiculously long time */
1529 timeout
= jiffies
+ msecs_to_jiffies(5);
1531 val
= ipath_read_kreg64(dd
, reg_id
);
1532 /* set so they have something, even on failures. */
1534 if ((val
& bits_to_wait_for
) == bits_to_wait_for
) {
1539 ipath_cdbg(VERBOSE
, "Changed from %llx to %llx, "
1540 "waiting for %llx bits\n",
1541 (unsigned long long) lastval
,
1542 (unsigned long long) val
,
1543 (unsigned long long) bits_to_wait_for
);
1545 if (time_after(jiffies
, timeout
)) {
1546 ipath_dbg("Didn't get bits %llx in register 0x%x, "
1548 (unsigned long long) bits_to_wait_for
,
1549 reg_id
, (unsigned long long) *valp
);
1559 * ipath_waitfor_mdio_cmdready - wait for last command to complete
1560 * @dd: the infinipath device
1562 * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go
1563 * away indicating the last command has completed. It doesn't return data
1565 int ipath_waitfor_mdio_cmdready(struct ipath_devdata
*dd
)
1567 unsigned long timeout
;
1571 /* wait a ridiculously long time */
1572 timeout
= jiffies
+ msecs_to_jiffies(5);
1574 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_mdio
);
1575 if (!(val
& IPATH_MDIO_CMDVALID
)) {
1580 if (time_after(jiffies
, timeout
)) {
1581 ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n",
1582 (unsigned long long) val
);
1593 * Flush all sends that might be in the ready to send state, as well as any
1594 * that are in the process of being sent. Used whenever we need to be
1595 * sure the send side is idle. Cleans up all buffer state by canceling
1596 * all pio buffers, and issuing an abort, which cleans up anything in the
1597 * launch fifo. The cancel is superfluous on some chip versions, but
1598 * it's safer to always do it.
1599 * PIOAvail bits are updated by the chip as if normal send had happened.
1601 void ipath_cancel_sends(struct ipath_devdata
*dd
)
1603 ipath_dbg("Cancelling all in-progress send buffers\n");
1604 dd
->ipath_lastcancel
= jiffies
+HZ
/2; /* skip armlaunch errs a bit */
1606 * the abort bit is auto-clearing. We read scratch to be sure
1607 * that cancels and the abort have taken effect in the chip.
1609 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
1610 INFINIPATH_S_ABORT
);
1611 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
1612 ipath_disarm_piobufs(dd
, 0,
1613 (unsigned)(dd
->ipath_piobcnt2k
+ dd
->ipath_piobcnt4k
));
1615 /* and again, be sure all have hit the chip */
1616 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
1620 static void ipath_set_ib_lstate(struct ipath_devdata
*dd
, int which
)
1622 static const char *what
[4] = {
1624 [INFINIPATH_IBCC_LINKCMD_INIT
] = "INIT",
1625 [INFINIPATH_IBCC_LINKCMD_ARMED
] = "ARMED",
1626 [INFINIPATH_IBCC_LINKCMD_ACTIVE
] = "ACTIVE"
1628 int linkcmd
= (which
>> INFINIPATH_IBCC_LINKCMD_SHIFT
) &
1629 INFINIPATH_IBCC_LINKCMD_MASK
;
1631 ipath_cdbg(VERBOSE
, "Trying to move unit %u to %s, current ltstate "
1632 "is %s\n", dd
->ipath_unit
,
1634 ipath_ibcstatus_str
[
1636 (dd
, dd
->ipath_kregs
->kr_ibcstatus
) >>
1637 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT
) &
1638 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK
]);
1639 /* flush all queued sends when going to DOWN or INIT, to be sure that
1640 * they don't block MAD packets */
1641 if (!linkcmd
|| linkcmd
== INFINIPATH_IBCC_LINKCMD_INIT
)
1642 ipath_cancel_sends(dd
);
1644 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1645 dd
->ipath_ibcctrl
| which
);
1648 int ipath_set_linkstate(struct ipath_devdata
*dd
, u8 newstate
)
1654 case IPATH_IB_LINKDOWN
:
1655 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKINITCMD_POLL
<<
1656 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
1661 case IPATH_IB_LINKDOWN_SLEEP
:
1662 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKINITCMD_SLEEP
<<
1663 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
1668 case IPATH_IB_LINKDOWN_DISABLE
:
1669 ipath_set_ib_lstate(dd
,
1670 INFINIPATH_IBCC_LINKINITCMD_DISABLE
<<
1671 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
1676 case IPATH_IB_LINKINIT
:
1677 if (dd
->ipath_flags
& IPATH_LINKINIT
) {
1681 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKCMD_INIT
<<
1682 INFINIPATH_IBCC_LINKCMD_SHIFT
);
1683 lstate
= IPATH_LINKINIT
;
1686 case IPATH_IB_LINKARM
:
1687 if (dd
->ipath_flags
& IPATH_LINKARMED
) {
1691 if (!(dd
->ipath_flags
&
1692 (IPATH_LINKINIT
| IPATH_LINKACTIVE
))) {
1696 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKCMD_ARMED
<<
1697 INFINIPATH_IBCC_LINKCMD_SHIFT
);
1699 * Since the port can transition to ACTIVE by receiving
1700 * a non VL 15 packet, wait for either state.
1702 lstate
= IPATH_LINKARMED
| IPATH_LINKACTIVE
;
1705 case IPATH_IB_LINKACTIVE
:
1706 if (dd
->ipath_flags
& IPATH_LINKACTIVE
) {
1710 if (!(dd
->ipath_flags
& IPATH_LINKARMED
)) {
1714 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKCMD_ACTIVE
<<
1715 INFINIPATH_IBCC_LINKCMD_SHIFT
);
1716 lstate
= IPATH_LINKACTIVE
;
1719 case IPATH_IB_LINK_LOOPBACK
:
1720 dev_info(&dd
->pcidev
->dev
, "Enabling IB local loopback\n");
1721 dd
->ipath_ibcctrl
|= INFINIPATH_IBCC_LOOPBACK
;
1722 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1725 goto bail
; // no state change to wait for
1727 case IPATH_IB_LINK_EXTERNAL
:
1728 dev_info(&dd
->pcidev
->dev
, "Disabling IB local loopback (normal)\n");
1729 dd
->ipath_ibcctrl
&= ~INFINIPATH_IBCC_LOOPBACK
;
1730 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1733 goto bail
; // no state change to wait for
1736 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate
);
1740 ret
= ipath_wait_linkstate(dd
, lstate
, 2000);
1747 * ipath_set_mtu - set the MTU
1748 * @dd: the infinipath device
1751 * we can handle "any" incoming size, the issue here is whether we
1752 * need to restrict our outgoing size. For now, we don't do any
1753 * sanity checking on this, and we don't deal with what happens to
1754 * programs that are already running when the size changes.
1755 * NOTE: changing the MTU will usually cause the IBC to go back to
1756 * link initialize (IPATH_IBSTATE_INIT) state...
1758 int ipath_set_mtu(struct ipath_devdata
*dd
, u16 arg
)
1765 * mtu is IB data payload max. It's the largest power of 2 less
1766 * than piosize (or even larger, since it only really controls the
1767 * largest we can receive; we can send the max of the mtu and
1768 * piosize). We check that it's one of the valid IB sizes.
1770 if (arg
!= 256 && arg
!= 512 && arg
!= 1024 && arg
!= 2048 &&
1772 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg
);
1776 if (dd
->ipath_ibmtu
== arg
) {
1777 ret
= 0; /* same as current */
1781 piosize
= dd
->ipath_ibmaxlen
;
1782 dd
->ipath_ibmtu
= arg
;
1784 if (arg
>= (piosize
- IPATH_PIO_MAXIBHDR
)) {
1785 /* Only if it's not the initial value (or reset to it) */
1786 if (piosize
!= dd
->ipath_init_ibmaxlen
) {
1787 dd
->ipath_ibmaxlen
= piosize
;
1790 } else if ((arg
+ IPATH_PIO_MAXIBHDR
) != dd
->ipath_ibmaxlen
) {
1791 piosize
= arg
+ IPATH_PIO_MAXIBHDR
;
1792 ipath_cdbg(VERBOSE
, "ibmaxlen was 0x%x, setting to 0x%x "
1793 "(mtu 0x%x)\n", dd
->ipath_ibmaxlen
, piosize
,
1795 dd
->ipath_ibmaxlen
= piosize
;
1801 * set the IBC maxpktlength to the size of our pio
1804 u64 ibc
= dd
->ipath_ibcctrl
;
1805 ibc
&= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK
<<
1806 INFINIPATH_IBCC_MAXPKTLEN_SHIFT
);
1808 piosize
= piosize
- 2 * sizeof(u32
); /* ignore pbc */
1809 dd
->ipath_ibmaxlen
= piosize
;
1810 piosize
/= sizeof(u32
); /* in words */
1812 * for ICRC, which we only send in diag test pkt mode, and
1813 * we don't need to worry about that for mtu
1817 ibc
|= piosize
<< INFINIPATH_IBCC_MAXPKTLEN_SHIFT
;
1818 dd
->ipath_ibcctrl
= ibc
;
1819 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1821 dd
->ipath_f_tidtemplate(dd
);
1830 int ipath_set_lid(struct ipath_devdata
*dd
, u32 arg
, u8 lmc
)
1832 dd
->ipath_lid
= arg
;
1833 dd
->ipath_lmc
= lmc
;
1840 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
1841 * @dd: the infinipath device
1842 * @regno: the register number to write
1843 * @port: the port containing the register
1844 * @value: the value to write
1846 * Registers that vary with the chip implementation constants (port)
1849 void ipath_write_kreg_port(const struct ipath_devdata
*dd
, ipath_kreg regno
,
1850 unsigned port
, u64 value
)
1854 if (port
< dd
->ipath_portcnt
&&
1855 (regno
== dd
->ipath_kregs
->kr_rcvhdraddr
||
1856 regno
== dd
->ipath_kregs
->kr_rcvhdrtailaddr
))
1857 where
= regno
+ port
;
1861 ipath_write_kreg(dd
, where
, value
);
1865 * Following deal with the "obviously simple" task of overriding the state
1866 * of the LEDS, which normally indicate link physical and logical status.
1867 * The complications arise in dealing with different hardware mappings
1868 * and the board-dependent routine being called from interrupts.
1869 * and then there's the requirement to _flash_ them.
1871 #define LED_OVER_FREQ_SHIFT 8
1872 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
1873 /* Below is "non-zero" to force override, but both actual LEDs are off */
1874 #define LED_OVER_BOTH_OFF (8)
1876 void ipath_run_led_override(unsigned long opaque
)
1878 struct ipath_devdata
*dd
= (struct ipath_devdata
*)opaque
;
1881 u64 lstate
, ltstate
, val
;
1883 if (!(dd
->ipath_flags
& IPATH_INITTED
))
1886 pidx
= dd
->ipath_led_override_phase
++ & 1;
1887 dd
->ipath_led_override
= dd
->ipath_led_override_vals
[pidx
];
1888 timeoff
= dd
->ipath_led_override_timeoff
;
1891 * below potentially restores the LED values per current status,
1892 * should also possibly setup the traffic-blink register,
1893 * but leave that to per-chip functions.
1895 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_ibcstatus
);
1896 ltstate
= (val
>> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT
) &
1897 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK
;
1898 lstate
= (val
>> INFINIPATH_IBCS_LINKSTATE_SHIFT
) &
1899 INFINIPATH_IBCS_LINKSTATE_MASK
;
1901 dd
->ipath_f_setextled(dd
, lstate
, ltstate
);
1902 mod_timer(&dd
->ipath_led_override_timer
, jiffies
+ timeoff
);
1905 void ipath_set_led_override(struct ipath_devdata
*dd
, unsigned int val
)
1909 if (!(dd
->ipath_flags
& IPATH_INITTED
))
1912 /* First check if we are blinking. If not, use 1HZ polling */
1914 freq
= (val
& LED_OVER_FREQ_MASK
) >> LED_OVER_FREQ_SHIFT
;
1917 /* For blink, set each phase from one nybble of val */
1918 dd
->ipath_led_override_vals
[0] = val
& 0xF;
1919 dd
->ipath_led_override_vals
[1] = (val
>> 4) & 0xF;
1920 timeoff
= (HZ
<< 4)/freq
;
1922 /* Non-blink set both phases the same. */
1923 dd
->ipath_led_override_vals
[0] = val
& 0xF;
1924 dd
->ipath_led_override_vals
[1] = val
& 0xF;
1926 dd
->ipath_led_override_timeoff
= timeoff
;
1929 * If the timer has not already been started, do so. Use a "quick"
1930 * timeout so the function will be called soon, to look at our request.
1932 if (atomic_inc_return(&dd
->ipath_led_override_timer_active
) == 1) {
1933 /* Need to start timer */
1934 init_timer(&dd
->ipath_led_override_timer
);
1935 dd
->ipath_led_override_timer
.function
=
1936 ipath_run_led_override
;
1937 dd
->ipath_led_override_timer
.data
= (unsigned long) dd
;
1938 dd
->ipath_led_override_timer
.expires
= jiffies
+ 1;
1939 add_timer(&dd
->ipath_led_override_timer
);
1941 atomic_dec(&dd
->ipath_led_override_timer_active
);
1946 * ipath_shutdown_device - shut down a device
1947 * @dd: the infinipath device
1949 * This is called to make the device quiet when we are about to
1950 * unload the driver, and also when the device is administratively
1951 * disabled. It does not free any data structures.
1952 * Everything it does has to be setup again by ipath_init_chip(dd,1)
1954 void ipath_shutdown_device(struct ipath_devdata
*dd
)
1956 ipath_dbg("Shutting down the device\n");
1958 dd
->ipath_flags
|= IPATH_LINKUNK
;
1959 dd
->ipath_flags
&= ~(IPATH_INITTED
| IPATH_LINKDOWN
|
1960 IPATH_LINKINIT
| IPATH_LINKARMED
|
1962 *dd
->ipath_statusp
&= ~(IPATH_STATUS_IB_CONF
|
1963 IPATH_STATUS_IB_READY
);
1965 /* mask interrupts, but not errors */
1966 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intmask
, 0ULL);
1968 dd
->ipath_rcvctrl
= 0;
1969 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvctrl
,
1973 * gracefully stop all sends allowing any in progress to trickle out
1976 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
, 0ULL);
1978 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
1980 * enough for anything that's going to trickle out to have actually
1985 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKINITCMD_DISABLE
<<
1986 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
1987 ipath_cancel_sends(dd
);
1990 dd
->ipath_control
&= ~INFINIPATH_C_LINKENABLE
;
1991 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
,
1992 dd
->ipath_control
| INFINIPATH_C_FREEZEMODE
);
1995 * clear SerdesEnable and turn the leds off; do this here because
1996 * we are unloading, so don't count on interrupts to move along
1997 * Turn the LEDs off explictly for the same reason.
1999 dd
->ipath_f_quiet_serdes(dd
);
2001 if (dd
->ipath_stats_timer_active
) {
2002 del_timer_sync(&dd
->ipath_stats_timer
);
2003 dd
->ipath_stats_timer_active
= 0;
2007 * clear all interrupts and errors, so that the next time the driver
2008 * is loaded or device is enabled, we know that whatever is set
2009 * happened while we were unloaded
2011 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrclear
,
2012 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED
);
2013 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errorclear
, -1LL);
2014 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intclear
, -1LL);
2016 ipath_cdbg(VERBOSE
, "Flush time and errors to EEPROM\n");
2017 ipath_update_eeprom_log(dd
);
2021 * ipath_free_pddata - free a port's allocated data
2022 * @dd: the infinipath device
2023 * @pd: the portdata structure
2025 * free up any allocated data for a port
2026 * This should not touch anything that would affect a simultaneous
2027 * re-allocation of port data, because it is called after ipath_mutex
2028 * is released (and can be called from reinit as well).
2029 * It should never change any chip state, or global driver state.
2030 * (The only exception to global state is freeing the port0 port0_skbs.)
2032 void ipath_free_pddata(struct ipath_devdata
*dd
, struct ipath_portdata
*pd
)
2037 if (pd
->port_rcvhdrq
) {
2038 ipath_cdbg(VERBOSE
, "free closed port %d rcvhdrq @ %p "
2039 "(size=%lu)\n", pd
->port_port
, pd
->port_rcvhdrq
,
2040 (unsigned long) pd
->port_rcvhdrq_size
);
2041 dma_free_coherent(&dd
->pcidev
->dev
, pd
->port_rcvhdrq_size
,
2042 pd
->port_rcvhdrq
, pd
->port_rcvhdrq_phys
);
2043 pd
->port_rcvhdrq
= NULL
;
2044 if (pd
->port_rcvhdrtail_kvaddr
) {
2045 dma_free_coherent(&dd
->pcidev
->dev
, PAGE_SIZE
,
2046 pd
->port_rcvhdrtail_kvaddr
,
2047 pd
->port_rcvhdrqtailaddr_phys
);
2048 pd
->port_rcvhdrtail_kvaddr
= NULL
;
2051 if (pd
->port_port
&& pd
->port_rcvegrbuf
) {
2054 for (e
= 0; e
< pd
->port_rcvegrbuf_chunks
; e
++) {
2055 void *base
= pd
->port_rcvegrbuf
[e
];
2056 size_t size
= pd
->port_rcvegrbuf_size
;
2058 ipath_cdbg(VERBOSE
, "egrbuf free(%p, %lu), "
2059 "chunk %u/%u\n", base
,
2060 (unsigned long) size
,
2061 e
, pd
->port_rcvegrbuf_chunks
);
2062 dma_free_coherent(&dd
->pcidev
->dev
, size
,
2063 base
, pd
->port_rcvegrbuf_phys
[e
]);
2065 kfree(pd
->port_rcvegrbuf
);
2066 pd
->port_rcvegrbuf
= NULL
;
2067 kfree(pd
->port_rcvegrbuf_phys
);
2068 pd
->port_rcvegrbuf_phys
= NULL
;
2069 pd
->port_rcvegrbuf_chunks
= 0;
2070 } else if (pd
->port_port
== 0 && dd
->ipath_port0_skbinfo
) {
2072 struct ipath_skbinfo
*skbinfo
= dd
->ipath_port0_skbinfo
;
2074 dd
->ipath_port0_skbinfo
= NULL
;
2075 ipath_cdbg(VERBOSE
, "free closed port %d "
2076 "ipath_port0_skbinfo @ %p\n", pd
->port_port
,
2078 for (e
= 0; e
< dd
->ipath_rcvegrcnt
; e
++)
2079 if (skbinfo
[e
].skb
) {
2080 pci_unmap_single(dd
->pcidev
, skbinfo
[e
].phys
,
2082 PCI_DMA_FROMDEVICE
);
2083 dev_kfree_skb(skbinfo
[e
].skb
);
2087 kfree(pd
->port_tid_pg_list
);
2088 vfree(pd
->subport_uregbase
);
2089 vfree(pd
->subport_rcvegrbuf
);
2090 vfree(pd
->subport_rcvhdr_base
);
2094 static int __init
infinipath_init(void)
2098 if (ipath_debug
& __IPATH_DBG
)
2099 printk(KERN_INFO DRIVER_LOAD_MSG
"%s", ib_ipath_version
);
2102 * These must be called before the driver is registered with
2103 * the PCI subsystem.
2105 idr_init(&unit_table
);
2106 if (!idr_pre_get(&unit_table
, GFP_KERNEL
)) {
2111 ret
= pci_register_driver(&ipath_driver
);
2113 printk(KERN_ERR IPATH_DRV_NAME
2114 ": Unable to register driver: error %d\n", -ret
);
2118 ret
= ipath_driver_create_group(&ipath_driver
.driver
);
2120 printk(KERN_ERR IPATH_DRV_NAME
": Unable to create driver "
2121 "sysfs entries: error %d\n", -ret
);
2125 ret
= ipath_init_ipathfs();
2127 printk(KERN_ERR IPATH_DRV_NAME
": Unable to create "
2128 "ipathfs: error %d\n", -ret
);
2135 ipath_driver_remove_group(&ipath_driver
.driver
);
2138 pci_unregister_driver(&ipath_driver
);
2141 idr_destroy(&unit_table
);
2147 static void __exit
infinipath_cleanup(void)
2149 ipath_exit_ipathfs();
2151 ipath_driver_remove_group(&ipath_driver
.driver
);
2153 ipath_cdbg(VERBOSE
, "Unregistering pci driver\n");
2154 pci_unregister_driver(&ipath_driver
);
2156 idr_destroy(&unit_table
);
2160 * ipath_reset_device - reset the chip if possible
2161 * @unit: the device to reset
2163 * Whether or not reset is successful, we attempt to re-initialize the chip
2164 * (that is, much like a driver unload/reload). We clear the INITTED flag
2165 * so that the various entry points will fail until we reinitialize. For
2166 * now, we only allow this if no user ports are open that use chip resources
2168 int ipath_reset_device(int unit
)
2171 struct ipath_devdata
*dd
= ipath_lookup(unit
);
2178 if (atomic_read(&dd
->ipath_led_override_timer_active
)) {
2179 /* Need to stop LED timer, _then_ shut off LEDs */
2180 del_timer_sync(&dd
->ipath_led_override_timer
);
2181 atomic_set(&dd
->ipath_led_override_timer_active
, 0);
2184 /* Shut off LEDs after we are sure timer is not running */
2185 dd
->ipath_led_override
= LED_OVER_BOTH_OFF
;
2186 dd
->ipath_f_setextled(dd
, 0, 0);
2188 dev_info(&dd
->pcidev
->dev
, "Reset on unit %u requested\n", unit
);
2190 if (!dd
->ipath_kregbase
|| !(dd
->ipath_flags
& IPATH_PRESENT
)) {
2191 dev_info(&dd
->pcidev
->dev
, "Invalid unit number %u or "
2192 "not initialized or not present\n", unit
);
2198 for (i
= 1; i
< dd
->ipath_cfgports
; i
++) {
2199 if (dd
->ipath_pd
[i
] && dd
->ipath_pd
[i
]->port_cnt
) {
2200 ipath_dbg("unit %u port %d is in use "
2201 "(PID %u cmd %s), can't reset\n",
2203 dd
->ipath_pd
[i
]->port_pid
,
2204 dd
->ipath_pd
[i
]->port_comm
);
2210 dd
->ipath_flags
&= ~IPATH_INITTED
;
2211 ret
= dd
->ipath_f_reset(dd
);
2213 ipath_dbg("reset was not successful\n");
2214 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2216 ret
= ipath_init_chip(dd
, 1);
2218 ipath_dev_err(dd
, "Reinitialize unit %u after "
2219 "reset failed with %d\n", unit
, ret
);
2221 dev_info(&dd
->pcidev
->dev
, "Reinitialized unit %u after "
2222 "resetting\n", unit
);
2228 int ipath_set_rx_pol_inv(struct ipath_devdata
*dd
, u8 new_pol_inv
)
2231 if ( new_pol_inv
> INFINIPATH_XGXS_RX_POL_MASK
) {
2234 if ( dd
->ipath_rx_pol_inv
!= new_pol_inv
) {
2235 dd
->ipath_rx_pol_inv
= new_pol_inv
;
2236 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_xgxsconfig
);
2237 val
&= ~(INFINIPATH_XGXS_RX_POL_MASK
<<
2238 INFINIPATH_XGXS_RX_POL_SHIFT
);
2239 val
|= ((u64
)dd
->ipath_rx_pol_inv
) <<
2240 INFINIPATH_XGXS_RX_POL_SHIFT
;
2241 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_xgxsconfig
, val
);
2245 module_init(infinipath_init
);
2246 module_exit(infinipath_cleanup
);