2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/vmalloc.h>
42 #include "ipath_kernel.h"
43 #include "ipath_verbs.h"
44 #include "ipath_common.h"
46 static void ipath_update_pio_bufs(struct ipath_devdata
*);
48 const char *ipath_get_unit_name(int unit
)
50 static char iname
[16];
51 snprintf(iname
, sizeof iname
, "infinipath%u", unit
);
55 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
56 #define PFX IPATH_DRV_NAME ": "
59 * The size has to be longer than this string, so we can append
60 * board/chip information to it in the init code.
62 const char ib_ipath_version
[] = IPATH_IDSTR
"\n";
64 static struct idr unit_table
;
65 DEFINE_SPINLOCK(ipath_devs_lock
);
66 LIST_HEAD(ipath_dev_list
);
68 wait_queue_head_t ipath_state_wait
;
70 unsigned ipath_debug
= __IPATH_INFO
;
72 module_param_named(debug
, ipath_debug
, uint
, S_IWUSR
| S_IRUGO
);
73 MODULE_PARM_DESC(debug
, "mask for debug prints");
74 EXPORT_SYMBOL_GPL(ipath_debug
);
76 unsigned ipath_mtu4096
= 1; /* max 4KB IB mtu by default, if supported */
77 module_param_named(mtu4096
, ipath_mtu4096
, uint
, S_IRUGO
);
78 MODULE_PARM_DESC(mtu4096
, "enable MTU of 4096 bytes, if supported");
80 MODULE_LICENSE("GPL");
81 MODULE_AUTHOR("QLogic <support@pathscale.com>");
82 MODULE_DESCRIPTION("QLogic InfiniPath driver");
84 const char *ipath_ibcstatus_str
[] = {
91 "LState6", /* unused */
92 "LState7", /* unused */
98 "LState0xD", /* unused */
103 static void __devexit
ipath_remove_one(struct pci_dev
*);
104 static int __devinit
ipath_init_one(struct pci_dev
*,
105 const struct pci_device_id
*);
107 /* Only needed for registration, nothing else needs this info */
108 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
109 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
110 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
112 /* Number of seconds before our card status check... */
113 #define STATUS_TIMEOUT 60
115 static const struct pci_device_id ipath_pci_tbl
[] = {
116 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE
, PCI_DEVICE_ID_INFINIPATH_HT
) },
117 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE
, PCI_DEVICE_ID_INFINIPATH_PE800
) },
121 MODULE_DEVICE_TABLE(pci
, ipath_pci_tbl
);
123 static struct pci_driver ipath_driver
= {
124 .name
= IPATH_DRV_NAME
,
125 .probe
= ipath_init_one
,
126 .remove
= __devexit_p(ipath_remove_one
),
127 .id_table
= ipath_pci_tbl
,
129 .groups
= ipath_driver_attr_groups
,
133 static void ipath_check_status(struct work_struct
*work
)
135 struct ipath_devdata
*dd
= container_of(work
, struct ipath_devdata
,
139 * If we don't have any interrupts, let the user know and
140 * don't bother checking again.
142 if (dd
->ipath_int_counter
== 0)
143 dev_err(&dd
->pcidev
->dev
, "No interrupts detected.\n");
146 static inline void read_bars(struct ipath_devdata
*dd
, struct pci_dev
*dev
,
147 u32
*bar0
, u32
*bar1
)
151 ret
= pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
, bar0
);
153 ipath_dev_err(dd
, "failed to read bar0 before enable: "
156 ret
= pci_read_config_dword(dev
, PCI_BASE_ADDRESS_1
, bar1
);
158 ipath_dev_err(dd
, "failed to read bar1 before enable: "
161 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0
, *bar1
);
164 static void ipath_free_devdata(struct pci_dev
*pdev
,
165 struct ipath_devdata
*dd
)
169 pci_set_drvdata(pdev
, NULL
);
171 if (dd
->ipath_unit
!= -1) {
172 spin_lock_irqsave(&ipath_devs_lock
, flags
);
173 idr_remove(&unit_table
, dd
->ipath_unit
);
174 list_del(&dd
->ipath_list
);
175 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
180 static struct ipath_devdata
*ipath_alloc_devdata(struct pci_dev
*pdev
)
183 struct ipath_devdata
*dd
;
186 if (!idr_pre_get(&unit_table
, GFP_KERNEL
)) {
187 dd
= ERR_PTR(-ENOMEM
);
191 dd
= vmalloc(sizeof(*dd
));
193 dd
= ERR_PTR(-ENOMEM
);
196 memset(dd
, 0, sizeof(*dd
));
199 spin_lock_irqsave(&ipath_devs_lock
, flags
);
201 ret
= idr_get_new(&unit_table
, dd
, &dd
->ipath_unit
);
203 printk(KERN_ERR IPATH_DRV_NAME
204 ": Could not allocate unit ID: error %d\n", -ret
);
205 ipath_free_devdata(pdev
, dd
);
211 pci_set_drvdata(pdev
, dd
);
213 INIT_DELAYED_WORK(&dd
->status_work
, ipath_check_status
);
215 list_add(&dd
->ipath_list
, &ipath_dev_list
);
218 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
224 static inline struct ipath_devdata
*__ipath_lookup(int unit
)
226 return idr_find(&unit_table
, unit
);
229 struct ipath_devdata
*ipath_lookup(int unit
)
231 struct ipath_devdata
*dd
;
234 spin_lock_irqsave(&ipath_devs_lock
, flags
);
235 dd
= __ipath_lookup(unit
);
236 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
241 int ipath_count_units(int *npresentp
, int *nupp
, int *maxportsp
)
243 int nunits
, npresent
, nup
;
244 struct ipath_devdata
*dd
;
248 nunits
= npresent
= nup
= maxports
= 0;
250 spin_lock_irqsave(&ipath_devs_lock
, flags
);
252 list_for_each_entry(dd
, &ipath_dev_list
, ipath_list
) {
254 if ((dd
->ipath_flags
& IPATH_PRESENT
) && dd
->ipath_kregbase
)
257 !(dd
->ipath_flags
& (IPATH_DISABLED
| IPATH_LINKDOWN
260 if (dd
->ipath_cfgports
> maxports
)
261 maxports
= dd
->ipath_cfgports
;
264 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);
267 *npresentp
= npresent
;
271 *maxportsp
= maxports
;
277 * These next two routines are placeholders in case we don't have per-arch
278 * code for controlling write combining. If explicit control of write
279 * combining is not available, performance will probably be awful.
282 int __attribute__((weak
)) ipath_enable_wc(struct ipath_devdata
*dd
)
287 void __attribute__((weak
)) ipath_disable_wc(struct ipath_devdata
*dd
)
292 * Perform a PIO buffer bandwidth write test, to verify proper system
293 * configuration. Even when all the setup calls work, occasionally
294 * BIOS or other issues can prevent write combining from working, or
295 * can cause other bandwidth problems to the chip.
297 * This test simply writes the same buffer over and over again, and
298 * measures close to the peak bandwidth to the chip (not testing
299 * data bandwidth to the wire). On chips that use an address-based
300 * trigger to send packets to the wire, this is easy. On chips that
301 * use a count to trigger, we want to make sure that the packet doesn't
302 * go out on the wire, or trigger flow control checks.
304 static void ipath_verify_pioperf(struct ipath_devdata
*dd
)
306 u32 pbnum
, cnt
, lcnt
;
311 piobuf
= ipath_getpiobuf(dd
, &pbnum
);
313 dev_info(&dd
->pcidev
->dev
,
314 "No PIObufs for checking perf, skipping\n");
319 * Enough to give us a reasonable test, less than piobuf size, and
320 * likely multiple of store buffer length.
326 dev_info(&dd
->pcidev
->dev
,
327 "Couldn't get memory for checking PIO perf,"
332 preempt_disable(); /* we want reasonably accurate elapsed time */
333 msecs
= 1 + jiffies_to_msecs(jiffies
);
334 for (lcnt
= 0; lcnt
< 10000U; lcnt
++) {
335 /* wait until we cross msec boundary */
336 if (jiffies_to_msecs(jiffies
) >= msecs
)
341 ipath_disable_armlaunch(dd
);
343 writeq(0, piobuf
); /* length 0, no dwords actually sent */
347 * this is only roughly accurate, since even with preempt we
348 * still take interrupts that could take a while. Running for
349 * >= 5 msec seems to get us "close enough" to accurate values
351 msecs
= jiffies_to_msecs(jiffies
);
352 for (emsecs
= lcnt
= 0; emsecs
<= 5UL; lcnt
++) {
353 __iowrite32_copy(piobuf
+ 64, addr
, cnt
>> 2);
354 emsecs
= jiffies_to_msecs(jiffies
) - msecs
;
357 /* 1 GiB/sec, slightly over IB SDR line rate */
358 if (lcnt
< (emsecs
* 1024U))
360 "Performance problem: bandwidth to PIO buffers is "
362 lcnt
/ (u32
) emsecs
);
364 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
365 lcnt
/ (u32
) emsecs
);
372 /* disarm piobuf, so it's available again */
373 ipath_disarm_piobufs(dd
, pbnum
, 1);
374 ipath_enable_armlaunch(dd
);
377 static int __devinit
ipath_init_one(struct pci_dev
*pdev
,
378 const struct pci_device_id
*ent
)
381 struct ipath_devdata
*dd
;
382 unsigned long long addr
;
383 u32 bar0
= 0, bar1
= 0;
385 dd
= ipath_alloc_devdata(pdev
);
388 printk(KERN_ERR IPATH_DRV_NAME
389 ": Could not allocate devdata: error %d\n", -ret
);
393 ipath_cdbg(VERBOSE
, "initializing unit #%u\n", dd
->ipath_unit
);
395 ret
= pci_enable_device(pdev
);
397 /* This can happen iff:
399 * We did a chip reset, and then failed to reprogram the
400 * BAR, or the chip reset due to an internal error. We then
401 * unloaded the driver and reloaded it.
403 * Both reset cases set the BAR back to initial state. For
404 * the latter case, the AER sticky error bit at offset 0x718
405 * should be set, but the Linux kernel doesn't yet know
406 * about that, it appears. If the original BAR was retained
407 * in the kernel data structures, this may be OK.
409 ipath_dev_err(dd
, "enable unit %d failed: error %d\n",
410 dd
->ipath_unit
, -ret
);
413 addr
= pci_resource_start(pdev
, 0);
414 len
= pci_resource_len(pdev
, 0);
415 ipath_cdbg(VERBOSE
, "regbase (0) %llx len %d pdev->irq %d, vend %x/%x "
416 "driver_data %lx\n", addr
, len
, pdev
->irq
, ent
->vendor
,
417 ent
->device
, ent
->driver_data
);
419 read_bars(dd
, pdev
, &bar0
, &bar1
);
421 if (!bar1
&& !(bar0
& ~0xf)) {
423 dev_info(&pdev
->dev
, "BAR is 0 (probable RESET), "
424 "rewriting as %llx\n", addr
);
425 ret
= pci_write_config_dword(
426 pdev
, PCI_BASE_ADDRESS_0
, addr
);
428 ipath_dev_err(dd
, "rewrite of BAR0 "
429 "failed: err %d\n", -ret
);
432 ret
= pci_write_config_dword(
433 pdev
, PCI_BASE_ADDRESS_1
, addr
>> 32);
435 ipath_dev_err(dd
, "rewrite of BAR1 "
436 "failed: err %d\n", -ret
);
440 ipath_dev_err(dd
, "BAR is 0 (probable RESET), "
441 "not usable until reboot\n");
447 ret
= pci_request_regions(pdev
, IPATH_DRV_NAME
);
449 dev_info(&pdev
->dev
, "pci_request_regions unit %u fails: "
450 "err %d\n", dd
->ipath_unit
, -ret
);
454 ret
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
);
457 * if the 64 bit setup fails, try 32 bit. Some systems
458 * do not setup 64 bit maps on systems with 2GB or less
461 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
464 "Unable to set DMA mask for unit %u: %d\n",
465 dd
->ipath_unit
, ret
);
469 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
470 ret
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
473 "Unable to set DMA consistent mask "
475 dd
->ipath_unit
, ret
);
480 ret
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
483 "Unable to set DMA consistent mask "
485 dd
->ipath_unit
, ret
);
488 pci_set_master(pdev
);
491 * Save BARs to rewrite after device reset. Save all 64 bits of
494 dd
->ipath_pcibar0
= addr
;
495 dd
->ipath_pcibar1
= addr
>> 32;
496 dd
->ipath_deviceid
= ent
->device
; /* save for later use */
497 dd
->ipath_vendorid
= ent
->vendor
;
499 /* setup the chip-specific functions, as early as possible. */
500 switch (ent
->device
) {
501 case PCI_DEVICE_ID_INFINIPATH_HT
:
503 ipath_init_iba6110_funcs(dd
);
506 ipath_dev_err(dd
, "QLogic HT device 0x%x cannot work if "
507 "CONFIG_HT_IRQ is not enabled\n", ent
->device
);
510 case PCI_DEVICE_ID_INFINIPATH_PE800
:
511 #ifdef CONFIG_PCI_MSI
512 ipath_init_iba6120_funcs(dd
);
515 ipath_dev_err(dd
, "QLogic PCIE device 0x%x cannot work if "
516 "CONFIG_PCI_MSI is not enabled\n", ent
->device
);
520 ipath_dev_err(dd
, "Found unknown QLogic deviceid 0x%x, "
521 "failing\n", ent
->device
);
525 for (j
= 0; j
< 6; j
++) {
526 if (!pdev
->resource
[j
].start
)
528 ipath_cdbg(VERBOSE
, "BAR %d start %llx, end %llx, len %llx\n",
529 j
, (unsigned long long)pdev
->resource
[j
].start
,
530 (unsigned long long)pdev
->resource
[j
].end
,
531 (unsigned long long)pci_resource_len(pdev
, j
));
535 ipath_dev_err(dd
, "No valid address in BAR 0!\n");
540 dd
->ipath_pcirev
= pdev
->revision
;
542 #if defined(__powerpc__)
543 /* There isn't a generic way to specify writethrough mappings */
544 dd
->ipath_kregbase
= __ioremap(addr
, len
,
545 (_PAGE_NO_CACHE
|_PAGE_WRITETHRU
));
547 dd
->ipath_kregbase
= ioremap_nocache(addr
, len
);
550 if (!dd
->ipath_kregbase
) {
551 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
556 dd
->ipath_kregend
= (u64 __iomem
*)
557 ((void __iomem
*)dd
->ipath_kregbase
+ len
);
558 dd
->ipath_physaddr
= addr
; /* used for io_remap, etc. */
560 ipath_cdbg(VERBOSE
, "mapped io addr %llx to kregbase %p\n",
561 addr
, dd
->ipath_kregbase
);
564 * clear ipath_flags here instead of in ipath_init_chip as it is set
565 * by ipath_setup_htconfig.
568 dd
->ipath_lli_counter
= 0;
569 dd
->ipath_lli_errors
= 0;
571 if (dd
->ipath_f_bus(dd
, pdev
))
572 ipath_dev_err(dd
, "Failed to setup config space; "
573 "continuing anyway\n");
576 * set up our interrupt handler; IRQF_SHARED probably not needed,
577 * since MSI interrupts shouldn't be shared but won't hurt for now.
578 * check 0 irq after we return from chip-specific bus setup, since
579 * that can affect this due to setup
582 ipath_dev_err(dd
, "irq is 0, BIOS error? Interrupts won't "
585 ret
= request_irq(dd
->ipath_irq
, ipath_intr
, IRQF_SHARED
,
588 ipath_dev_err(dd
, "Couldn't setup irq handler, "
589 "irq=%d: %d\n", dd
->ipath_irq
, ret
);
594 ret
= ipath_init_chip(dd
, 0); /* do the chip-specific init */
598 ret
= ipath_enable_wc(dd
);
601 ipath_dev_err(dd
, "Write combining not enabled "
602 "(err %d): performance may be poor\n",
607 ipath_verify_pioperf(dd
);
609 ipath_device_create_group(&pdev
->dev
, dd
);
610 ipathfs_add_device(dd
);
613 ipath_register_ib_device(dd
);
615 /* Check that card status in STATUS_TIMEOUT seconds. */
616 schedule_delayed_work(&dd
->status_work
, HZ
* STATUS_TIMEOUT
);
621 if (pdev
->irq
) free_irq(pdev
->irq
, dd
);
624 iounmap((volatile void __iomem
*) dd
->ipath_kregbase
);
627 pci_release_regions(pdev
);
630 pci_disable_device(pdev
);
633 ipath_free_devdata(pdev
, dd
);
639 static void __devexit
cleanup_device(struct ipath_devdata
*dd
)
643 if (*dd
->ipath_statusp
& IPATH_STATUS_CHIP_PRESENT
) {
644 /* can't do anything more with chip; needs re-init */
645 *dd
->ipath_statusp
&= ~IPATH_STATUS_CHIP_PRESENT
;
646 if (dd
->ipath_kregbase
) {
648 * if we haven't already cleaned up before these are
649 * to ensure any register reads/writes "fail" until
652 dd
->ipath_kregbase
= NULL
;
653 dd
->ipath_uregbase
= 0;
654 dd
->ipath_sregbase
= 0;
655 dd
->ipath_cregbase
= 0;
656 dd
->ipath_kregsize
= 0;
658 ipath_disable_wc(dd
);
661 if (dd
->ipath_pioavailregs_dma
) {
662 dma_free_coherent(&dd
->pcidev
->dev
, PAGE_SIZE
,
663 (void *) dd
->ipath_pioavailregs_dma
,
664 dd
->ipath_pioavailregs_phys
);
665 dd
->ipath_pioavailregs_dma
= NULL
;
667 if (dd
->ipath_dummy_hdrq
) {
668 dma_free_coherent(&dd
->pcidev
->dev
,
669 dd
->ipath_pd
[0]->port_rcvhdrq_size
,
670 dd
->ipath_dummy_hdrq
, dd
->ipath_dummy_hdrq_phys
);
671 dd
->ipath_dummy_hdrq
= NULL
;
674 if (dd
->ipath_pageshadow
) {
675 struct page
**tmpp
= dd
->ipath_pageshadow
;
676 dma_addr_t
*tmpd
= dd
->ipath_physshadow
;
679 ipath_cdbg(VERBOSE
, "Unlocking any expTID pages still "
681 for (port
= 0; port
< dd
->ipath_cfgports
; port
++) {
682 int port_tidbase
= port
* dd
->ipath_rcvtidcnt
;
683 int maxtid
= port_tidbase
+ dd
->ipath_rcvtidcnt
;
684 for (i
= port_tidbase
; i
< maxtid
; i
++) {
687 pci_unmap_page(dd
->pcidev
, tmpd
[i
],
688 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
689 ipath_release_user_pages(&tmpp
[i
], 1);
695 ipath_stats
.sps_pageunlocks
+= cnt
;
696 ipath_cdbg(VERBOSE
, "There were still %u expTID "
697 "entries locked\n", cnt
);
699 if (ipath_stats
.sps_pagelocks
||
700 ipath_stats
.sps_pageunlocks
)
701 ipath_cdbg(VERBOSE
, "%llu pages locked, %llu "
702 "unlocked via ipath_m{un}lock\n",
704 ipath_stats
.sps_pagelocks
,
706 ipath_stats
.sps_pageunlocks
);
708 ipath_cdbg(VERBOSE
, "Free shadow page tid array at %p\n",
709 dd
->ipath_pageshadow
);
710 tmpp
= dd
->ipath_pageshadow
;
711 dd
->ipath_pageshadow
= NULL
;
716 * free any resources still in use (usually just kernel ports)
717 * at unload; we do for portcnt, not cfgports, because cfgports
718 * could have changed while we were loaded.
720 for (port
= 0; port
< dd
->ipath_portcnt
; port
++) {
721 struct ipath_portdata
*pd
= dd
->ipath_pd
[port
];
722 dd
->ipath_pd
[port
] = NULL
;
723 ipath_free_pddata(dd
, pd
);
727 * debuggability, in case some cleanup path tries to use it
733 static void __devexit
ipath_remove_one(struct pci_dev
*pdev
)
735 struct ipath_devdata
*dd
= pci_get_drvdata(pdev
);
737 ipath_cdbg(VERBOSE
, "removing, pdev=%p, dd=%p\n", pdev
, dd
);
740 * disable the IB link early, to be sure no new packets arrive, which
741 * complicates the shutdown process
743 ipath_shutdown_device(dd
);
745 cancel_delayed_work(&dd
->status_work
);
746 flush_scheduled_work();
749 ipath_unregister_ib_device(dd
->verbs_dev
);
751 ipath_diag_remove(dd
);
752 ipath_user_remove(dd
);
753 ipathfs_remove_device(dd
);
754 ipath_device_remove_group(&pdev
->dev
, dd
);
756 ipath_cdbg(VERBOSE
, "Releasing pci memory regions, dd %p, "
757 "unit %u\n", dd
, (u32
) dd
->ipath_unit
);
762 * turn off rcv, send, and interrupts for all ports, all drivers
763 * should also hard reset the chip here?
764 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
765 * for all versions of the driver, if they were allocated
768 ipath_cdbg(VERBOSE
, "unit %u free irq %d\n",
769 dd
->ipath_unit
, dd
->ipath_irq
);
770 dd
->ipath_f_free_irq(dd
);
772 ipath_dbg("irq is 0, not doing free_irq "
773 "for unit %u\n", dd
->ipath_unit
);
775 * we check for NULL here, because it's outside
776 * the kregbase check, and we need to call it
777 * after the free_irq. Thus it's possible that
778 * the function pointers were never initialized.
780 if (dd
->ipath_f_cleanup
)
781 /* clean up chip-specific stuff */
782 dd
->ipath_f_cleanup(dd
);
784 ipath_cdbg(VERBOSE
, "Unmapping kregbase %p\n", dd
->ipath_kregbase
);
785 iounmap((volatile void __iomem
*) dd
->ipath_kregbase
);
786 pci_release_regions(pdev
);
787 ipath_cdbg(VERBOSE
, "calling pci_disable_device\n");
788 pci_disable_device(pdev
);
790 ipath_free_devdata(pdev
, dd
);
793 /* general driver use */
794 DEFINE_MUTEX(ipath_mutex
);
796 static DEFINE_SPINLOCK(ipath_pioavail_lock
);
799 * ipath_disarm_piobufs - cancel a range of PIO buffers
800 * @dd: the infinipath device
801 * @first: the first PIO buffer to cancel
802 * @cnt: the number of PIO buffers to cancel
804 * cancel a range of PIO buffers, used when they might be armed, but
805 * not triggered. Used at init to ensure buffer state, and also user
806 * process close, in case it died while writing to a PIO buffer
809 void ipath_disarm_piobufs(struct ipath_devdata
*dd
, unsigned first
,
812 unsigned i
, last
= first
+ cnt
;
815 ipath_cdbg(PKT
, "disarm %u PIObufs first=%u\n", cnt
, first
);
816 for (i
= first
; i
< last
; i
++) {
817 spin_lock_irqsave(&dd
->ipath_sendctrl_lock
, flags
);
819 * The disarm-related bits are write-only, so it
820 * is ok to OR them in with our copy of sendctrl
821 * while we hold the lock.
823 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
824 dd
->ipath_sendctrl
| INFINIPATH_S_DISARM
|
825 (i
<< INFINIPATH_S_DISARMPIOBUF_SHIFT
));
826 /* can't disarm bufs back-to-back per iba7220 spec */
827 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
828 spin_unlock_irqrestore(&dd
->ipath_sendctrl_lock
, flags
);
832 * Disable PIOAVAILUPD, then re-enable, reading scratch in
833 * between. This seems to avoid a chip timing race that causes
834 * pioavail updates to memory to stop. We xor as we don't
835 * know the state of the bit when we're called.
837 spin_lock_irqsave(&dd
->ipath_sendctrl_lock
, flags
);
838 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
839 dd
->ipath_sendctrl
^ INFINIPATH_S_PIOBUFAVAILUPD
);
840 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
841 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
843 spin_unlock_irqrestore(&dd
->ipath_sendctrl_lock
, flags
);
847 * ipath_wait_linkstate - wait for an IB link state change to occur
848 * @dd: the infinipath device
849 * @state: the state to wait for
850 * @msecs: the number of milliseconds to wait
852 * wait up to msecs milliseconds for IB link state change to occur for
853 * now, take the easy polling route. Currently used only by
854 * ipath_set_linkstate. Returns 0 if state reached, otherwise
855 * -ETIMEDOUT state can have multiple states set, for any of several
858 int ipath_wait_linkstate(struct ipath_devdata
*dd
, u32 state
, int msecs
)
860 dd
->ipath_state_wanted
= state
;
861 wait_event_interruptible_timeout(ipath_state_wait
,
862 (dd
->ipath_flags
& state
),
863 msecs_to_jiffies(msecs
));
864 dd
->ipath_state_wanted
= 0;
866 if (!(dd
->ipath_flags
& state
)) {
868 ipath_cdbg(VERBOSE
, "Didn't reach linkstate %s within %u"
870 /* test INIT ahead of DOWN, both can be set */
871 (state
& IPATH_LINKINIT
) ? "INIT" :
872 ((state
& IPATH_LINKDOWN
) ? "DOWN" :
873 ((state
& IPATH_LINKARMED
) ? "ARM" : "ACTIVE")),
875 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_ibcstatus
);
876 ipath_cdbg(VERBOSE
, "ibcc=%llx ibcstatus=%llx (%s)\n",
877 (unsigned long long) ipath_read_kreg64(
878 dd
, dd
->ipath_kregs
->kr_ibcctrl
),
879 (unsigned long long) val
,
880 ipath_ibcstatus_str
[val
& 0xf]);
882 return (dd
->ipath_flags
& state
) ? 0 : -ETIMEDOUT
;
886 * Decode the error status into strings, deciding whether to always
887 * print * it or not depending on "normal packet errors" vs everything
888 * else. Return 1 if "real" errors, otherwise 0 if only packet
889 * errors, so caller can decide what to print with the string.
891 int ipath_decode_err(char *buf
, size_t blen
, ipath_err_t err
)
895 if (err
& INFINIPATH_E_PKTERRS
) {
896 if (!(err
& ~INFINIPATH_E_PKTERRS
))
897 iserr
= 0; // if only packet errors.
898 if (ipath_debug
& __IPATH_ERRPKTDBG
) {
899 if (err
& INFINIPATH_E_REBP
)
900 strlcat(buf
, "EBP ", blen
);
901 if (err
& INFINIPATH_E_RVCRC
)
902 strlcat(buf
, "VCRC ", blen
);
903 if (err
& INFINIPATH_E_RICRC
) {
904 strlcat(buf
, "CRC ", blen
);
905 // clear for check below, so only once
906 err
&= INFINIPATH_E_RICRC
;
908 if (err
& INFINIPATH_E_RSHORTPKTLEN
)
909 strlcat(buf
, "rshortpktlen ", blen
);
910 if (err
& INFINIPATH_E_SDROPPEDDATAPKT
)
911 strlcat(buf
, "sdroppeddatapkt ", blen
);
912 if (err
& INFINIPATH_E_SPKTLEN
)
913 strlcat(buf
, "spktlen ", blen
);
915 if ((err
& INFINIPATH_E_RICRC
) &&
916 !(err
&(INFINIPATH_E_RVCRC
|INFINIPATH_E_REBP
)))
917 strlcat(buf
, "CRC ", blen
);
921 if (err
& INFINIPATH_E_RHDRLEN
)
922 strlcat(buf
, "rhdrlen ", blen
);
923 if (err
& INFINIPATH_E_RBADTID
)
924 strlcat(buf
, "rbadtid ", blen
);
925 if (err
& INFINIPATH_E_RBADVERSION
)
926 strlcat(buf
, "rbadversion ", blen
);
927 if (err
& INFINIPATH_E_RHDR
)
928 strlcat(buf
, "rhdr ", blen
);
929 if (err
& INFINIPATH_E_RLONGPKTLEN
)
930 strlcat(buf
, "rlongpktlen ", blen
);
931 if (err
& INFINIPATH_E_RMAXPKTLEN
)
932 strlcat(buf
, "rmaxpktlen ", blen
);
933 if (err
& INFINIPATH_E_RMINPKTLEN
)
934 strlcat(buf
, "rminpktlen ", blen
);
935 if (err
& INFINIPATH_E_SMINPKTLEN
)
936 strlcat(buf
, "sminpktlen ", blen
);
937 if (err
& INFINIPATH_E_RFORMATERR
)
938 strlcat(buf
, "rformaterr ", blen
);
939 if (err
& INFINIPATH_E_RUNSUPVL
)
940 strlcat(buf
, "runsupvl ", blen
);
941 if (err
& INFINIPATH_E_RUNEXPCHAR
)
942 strlcat(buf
, "runexpchar ", blen
);
943 if (err
& INFINIPATH_E_RIBFLOW
)
944 strlcat(buf
, "ribflow ", blen
);
945 if (err
& INFINIPATH_E_SUNDERRUN
)
946 strlcat(buf
, "sunderrun ", blen
);
947 if (err
& INFINIPATH_E_SPIOARMLAUNCH
)
948 strlcat(buf
, "spioarmlaunch ", blen
);
949 if (err
& INFINIPATH_E_SUNEXPERRPKTNUM
)
950 strlcat(buf
, "sunexperrpktnum ", blen
);
951 if (err
& INFINIPATH_E_SDROPPEDSMPPKT
)
952 strlcat(buf
, "sdroppedsmppkt ", blen
);
953 if (err
& INFINIPATH_E_SMAXPKTLEN
)
954 strlcat(buf
, "smaxpktlen ", blen
);
955 if (err
& INFINIPATH_E_SUNSUPVL
)
956 strlcat(buf
, "sunsupVL ", blen
);
957 if (err
& INFINIPATH_E_INVALIDADDR
)
958 strlcat(buf
, "invalidaddr ", blen
);
959 if (err
& INFINIPATH_E_RRCVEGRFULL
)
960 strlcat(buf
, "rcvegrfull ", blen
);
961 if (err
& INFINIPATH_E_RRCVHDRFULL
)
962 strlcat(buf
, "rcvhdrfull ", blen
);
963 if (err
& INFINIPATH_E_IBSTATUSCHANGED
)
964 strlcat(buf
, "ibcstatuschg ", blen
);
965 if (err
& INFINIPATH_E_RIBLOSTLINK
)
966 strlcat(buf
, "riblostlink ", blen
);
967 if (err
& INFINIPATH_E_HARDWARE
)
968 strlcat(buf
, "hardware ", blen
);
969 if (err
& INFINIPATH_E_RESET
)
970 strlcat(buf
, "reset ", blen
);
976 * get_rhf_errstring - decode RHF errors
977 * @err: the err number
978 * @msg: the output buffer
979 * @len: the length of the output buffer
981 * only used one place now, may want more later
983 static void get_rhf_errstring(u32 err
, char *msg
, size_t len
)
985 /* if no errors, and so don't need to check what's first */
988 if (err
& INFINIPATH_RHF_H_ICRCERR
)
989 strlcat(msg
, "icrcerr ", len
);
990 if (err
& INFINIPATH_RHF_H_VCRCERR
)
991 strlcat(msg
, "vcrcerr ", len
);
992 if (err
& INFINIPATH_RHF_H_PARITYERR
)
993 strlcat(msg
, "parityerr ", len
);
994 if (err
& INFINIPATH_RHF_H_LENERR
)
995 strlcat(msg
, "lenerr ", len
);
996 if (err
& INFINIPATH_RHF_H_MTUERR
)
997 strlcat(msg
, "mtuerr ", len
);
998 if (err
& INFINIPATH_RHF_H_IHDRERR
)
999 /* infinipath hdr checksum error */
1000 strlcat(msg
, "ipathhdrerr ", len
);
1001 if (err
& INFINIPATH_RHF_H_TIDERR
)
1002 strlcat(msg
, "tiderr ", len
);
1003 if (err
& INFINIPATH_RHF_H_MKERR
)
1004 /* bad port, offset, etc. */
1005 strlcat(msg
, "invalid ipathhdr ", len
);
1006 if (err
& INFINIPATH_RHF_H_IBERR
)
1007 strlcat(msg
, "iberr ", len
);
1008 if (err
& INFINIPATH_RHF_L_SWA
)
1009 strlcat(msg
, "swA ", len
);
1010 if (err
& INFINIPATH_RHF_L_SWB
)
1011 strlcat(msg
, "swB ", len
);
1015 * ipath_get_egrbuf - get an eager buffer
1016 * @dd: the infinipath device
1017 * @bufnum: the eager buffer to get
1019 * must only be called if ipath_pd[port] is known to be allocated
1021 static inline void *ipath_get_egrbuf(struct ipath_devdata
*dd
, u32 bufnum
)
1023 return dd
->ipath_port0_skbinfo
?
1024 (void *) dd
->ipath_port0_skbinfo
[bufnum
].skb
->data
: NULL
;
1028 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1029 * @dd: the infinipath device
1030 * @gfp_mask: the sk_buff SFP mask
1032 struct sk_buff
*ipath_alloc_skb(struct ipath_devdata
*dd
,
1035 struct sk_buff
*skb
;
1039 * Only fully supported way to handle this is to allocate lots
1040 * extra, align as needed, and then do skb_reserve(). That wastes
1041 * a lot of memory... I'll have to hack this into infinipath_copy
1046 * We need 2 extra bytes for ipath_ether data sent in the
1047 * key header. In order to keep everything dword aligned,
1048 * we'll reserve 4 bytes.
1050 len
= dd
->ipath_ibmaxlen
+ 4;
1052 if (dd
->ipath_flags
& IPATH_4BYTE_TID
) {
1053 /* We need a 2KB multiple alignment, and there is no way
1054 * to do it except to allocate extra and then skb_reserve
1055 * enough to bring it up to the right alignment.
1060 skb
= __dev_alloc_skb(len
, gfp_mask
);
1062 ipath_dev_err(dd
, "Failed to allocate skbuff, length %u\n",
1067 skb_reserve(skb
, 4);
1069 if (dd
->ipath_flags
& IPATH_4BYTE_TID
) {
1070 u32 una
= (unsigned long)skb
->data
& 2047;
1072 skb_reserve(skb
, 2048 - una
);
1079 static void ipath_rcv_hdrerr(struct ipath_devdata
*dd
,
1086 struct ipath_message_header
*hdr
;
1088 get_rhf_errstring(eflags
, emsg
, sizeof emsg
);
1089 hdr
= (struct ipath_message_header
*)&rc
[1];
1090 ipath_cdbg(PKT
, "RHFerrs %x hdrqtail=%x typ=%u "
1091 "tlen=%x opcode=%x egridx=%x: %s\n",
1093 ipath_hdrget_rcv_type((__le32
*) rc
),
1094 ipath_hdrget_length_in_bytes((__le32
*) rc
),
1095 be32_to_cpu(hdr
->bth
[0]) >> 24,
1098 /* Count local link integrity errors. */
1099 if (eflags
& (INFINIPATH_RHF_H_ICRCERR
| INFINIPATH_RHF_H_VCRCERR
)) {
1100 u8 n
= (dd
->ipath_ibcctrl
>>
1101 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT
) &
1102 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK
;
1104 if (++dd
->ipath_lli_counter
> n
) {
1105 dd
->ipath_lli_counter
= 0;
1106 dd
->ipath_lli_errors
++;
1112 * ipath_kreceive - receive a packet
1113 * @pd: the infinipath port
1115 * called from interrupt handler for errors or receive interrupt
1117 void ipath_kreceive(struct ipath_portdata
*pd
)
1120 struct ipath_devdata
*dd
= pd
->port_dd
;
1122 const u32 rsize
= dd
->ipath_rcvhdrentsize
; /* words */
1123 const u32 maxcnt
= dd
->ipath_rcvhdrcnt
* rsize
; /* words */
1124 u32 etail
= -1, l
, hdrqtail
;
1125 struct ipath_message_header
*hdr
;
1126 u32 eflags
, i
, etype
, tlen
, pkttot
= 0, updegr
=0, reloop
=0;
1127 static u64 totcalls
; /* stats, may eventually remove */
1129 if (!dd
->ipath_hdrqtailptr
) {
1131 "hdrqtailptr not set, can't do receives\n");
1136 hdrqtail
= ipath_get_rcvhdrtail(pd
);
1141 for (i
= 0; l
!= hdrqtail
; i
++) {
1145 rc
= (u64
*) (pd
->port_rcvhdrq
+ (l
<< 2));
1146 hdr
= (struct ipath_message_header
*)&rc
[1];
1148 * could make a network order version of IPATH_KD_QP, and
1149 * do the obvious shift before masking to speed this up.
1151 qp
= ntohl(hdr
->bth
[1]) & 0xffffff;
1152 bthbytes
= (u8
*) hdr
->bth
;
1154 eflags
= ipath_hdrget_err_flags((__le32
*) rc
);
1155 etype
= ipath_hdrget_rcv_type((__le32
*) rc
);
1157 tlen
= ipath_hdrget_length_in_bytes((__le32
*) rc
);
1159 if (etype
!= RCVHQ_RCV_TYPE_EXPECTED
) {
1161 * it turns out that the chips uses an eager buffer
1162 * for all non-expected packets, whether it "needs"
1163 * one or not. So always get the index, but don't
1164 * set ebuf (so we try to copy data) unless the
1165 * length requires it.
1167 etail
= ipath_hdrget_index((__le32
*) rc
);
1168 if (tlen
> sizeof(*hdr
) ||
1169 etype
== RCVHQ_RCV_TYPE_NON_KD
)
1170 ebuf
= ipath_get_egrbuf(dd
, etail
);
1174 * both tiderr and ipathhdrerr are set for all plain IB
1175 * packets; only ipathhdrerr should be set.
1178 if (etype
!= RCVHQ_RCV_TYPE_NON_KD
&& etype
!=
1179 RCVHQ_RCV_TYPE_ERROR
&& ipath_hdrget_ipath_ver(
1180 hdr
->iph
.ver_port_tid_offset
) !=
1181 IPS_PROTO_VERSION
) {
1182 ipath_cdbg(PKT
, "Bad InfiniPath protocol version "
1186 if (unlikely(eflags
))
1187 ipath_rcv_hdrerr(dd
, eflags
, l
, etail
, rc
);
1188 else if (etype
== RCVHQ_RCV_TYPE_NON_KD
) {
1189 ipath_ib_rcv(dd
->verbs_dev
, rc
+ 1, ebuf
, tlen
);
1190 if (dd
->ipath_lli_counter
)
1191 dd
->ipath_lli_counter
--;
1192 ipath_cdbg(PKT
, "typ %x, opcode %x (eager, "
1193 "qp=%x), len %x; ignored\n",
1194 etype
, bthbytes
[0], qp
, tlen
);
1196 else if (etype
== RCVHQ_RCV_TYPE_EAGER
)
1197 ipath_cdbg(PKT
, "typ %x, opcode %x (eager, "
1198 "qp=%x), len %x; ignored\n",
1199 etype
, bthbytes
[0], qp
, tlen
);
1200 else if (etype
== RCVHQ_RCV_TYPE_EXPECTED
)
1201 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1202 be32_to_cpu(hdr
->bth
[0]) & 0xff);
1205 * error packet, type of error unknown.
1206 * Probably type 3, but we don't know, so don't
1207 * even try to print the opcode, etc.
1209 ipath_dbg("Error Pkt, but no eflags! egrbuf %x, "
1210 "len %x\nhdrq@%lx;hdrq+%x rhf: %llx; "
1211 "hdr %llx %llx %llx %llx %llx\n",
1212 etail
, tlen
, (unsigned long) rc
, l
,
1213 (unsigned long long) rc
[0],
1214 (unsigned long long) rc
[1],
1215 (unsigned long long) rc
[2],
1216 (unsigned long long) rc
[3],
1217 (unsigned long long) rc
[4],
1218 (unsigned long long) rc
[5]);
1223 if (etype
!= RCVHQ_RCV_TYPE_EXPECTED
)
1226 * update head regs on last packet, and every 16 packets.
1227 * Reduce bus traffic, while still trying to prevent
1228 * rcvhdrq overflows, for when the queue is nearly full
1230 if (l
== hdrqtail
|| (i
&& !(i
&0xf))) {
1233 /* request IBA6120 interrupt only on last */
1234 lval
= dd
->ipath_rhdrhead_intr_off
| l
;
1237 (void)ipath_write_ureg(dd
, ur_rcvhdrhead
, lval
, 0);
1239 (void)ipath_write_ureg(dd
, ur_rcvegrindexhead
,
1246 if (!dd
->ipath_rhdrhead_intr_off
&& !reloop
) {
1247 /* IBA6110 workaround; we can have a race clearing chip
1248 * interrupt with another interrupt about to be delivered,
1249 * and can clear it before it is delivered on the GPIO
1250 * workaround. By doing the extra check here for the
1251 * in-memory tail register updating while we were doing
1252 * earlier packets, we "almost" guarantee we have covered
1255 u32 hqtail
= ipath_get_rcvhdrtail(pd
);
1256 if (hqtail
!= hdrqtail
) {
1258 reloop
= 1; /* loop 1 extra time at most */
1267 if (pkttot
> ipath_stats
.sps_maxpkts_call
)
1268 ipath_stats
.sps_maxpkts_call
= pkttot
;
1269 ipath_stats
.sps_port0pkts
+= pkttot
;
1270 ipath_stats
.sps_avgpkts_call
=
1271 ipath_stats
.sps_port0pkts
/ ++totcalls
;
1277 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1278 * @dd: the infinipath device
1280 * called whenever our local copy indicates we have run out of send buffers
1281 * NOTE: This can be called from interrupt context by some code
1282 * and from non-interrupt context by ipath_getpiobuf().
1285 static void ipath_update_pio_bufs(struct ipath_devdata
*dd
)
1287 unsigned long flags
;
1289 const unsigned piobregs
= (unsigned)dd
->ipath_pioavregs
;
1291 /* If the generation (check) bits have changed, then we update the
1292 * busy bit for the corresponding PIO buffer. This algorithm will
1293 * modify positions to the value they already have in some cases
1294 * (i.e., no change), but it's faster than changing only the bits
1295 * that have changed.
1297 * We would like to do this atomicly, to avoid spinlocks in the
1298 * critical send path, but that's not really possible, given the
1299 * type of changes, and that this routine could be called on
1300 * multiple cpu's simultaneously, so we lock in this routine only,
1301 * to avoid conflicting updates; all we change is the shadow, and
1302 * it's a single 64 bit memory location, so by definition the update
1303 * is atomic in terms of what other cpu's can see in testing the
1304 * bits. The spin_lock overhead isn't too bad, since it only
1305 * happens when all buffers are in use, so only cpu overhead, not
1306 * latency or bandwidth is affected.
1308 #define _IPATH_ALL_CHECKBITS 0x5555555555555555ULL
1309 if (!dd
->ipath_pioavailregs_dma
) {
1310 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1313 if (ipath_debug
& __IPATH_VERBDBG
) {
1314 /* only if packet debug and verbose */
1315 volatile __le64
*dma
= dd
->ipath_pioavailregs_dma
;
1316 unsigned long *shadow
= dd
->ipath_pioavailshadow
;
1318 ipath_cdbg(PKT
, "Refill avail, dma0=%llx shad0=%lx, "
1319 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1321 (unsigned long long) le64_to_cpu(dma
[0]),
1323 (unsigned long long) le64_to_cpu(dma
[1]),
1325 (unsigned long long) le64_to_cpu(dma
[2]),
1327 (unsigned long long) le64_to_cpu(dma
[3]),
1331 PKT
, "2nd group, dma4=%llx shad4=%lx, "
1332 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1334 (unsigned long long) le64_to_cpu(dma
[4]),
1336 (unsigned long long) le64_to_cpu(dma
[5]),
1338 (unsigned long long) le64_to_cpu(dma
[6]),
1340 (unsigned long long) le64_to_cpu(dma
[7]),
1343 spin_lock_irqsave(&ipath_pioavail_lock
, flags
);
1344 for (i
= 0; i
< piobregs
; i
++) {
1345 u64 pchbusy
, pchg
, piov
, pnew
;
1347 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1349 if (i
> 3 && (dd
->ipath_flags
& IPATH_SWAP_PIOBUFS
))
1350 piov
= le64_to_cpu(dd
->ipath_pioavailregs_dma
[i
^ 1]);
1352 piov
= le64_to_cpu(dd
->ipath_pioavailregs_dma
[i
]);
1353 pchg
= _IPATH_ALL_CHECKBITS
&
1354 ~(dd
->ipath_pioavailshadow
[i
] ^ piov
);
1355 pchbusy
= pchg
<< INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
;
1356 if (pchg
&& (pchbusy
& dd
->ipath_pioavailshadow
[i
])) {
1357 pnew
= dd
->ipath_pioavailshadow
[i
] & ~pchbusy
;
1358 pnew
|= piov
& pchbusy
;
1359 dd
->ipath_pioavailshadow
[i
] = pnew
;
1362 spin_unlock_irqrestore(&ipath_pioavail_lock
, flags
);
1366 * ipath_setrcvhdrsize - set the receive header size
1367 * @dd: the infinipath device
1368 * @rhdrsize: the receive header size
1370 * called from user init code, and also layered driver init
1372 int ipath_setrcvhdrsize(struct ipath_devdata
*dd
, unsigned rhdrsize
)
1376 if (dd
->ipath_flags
& IPATH_RCVHDRSZ_SET
) {
1377 if (dd
->ipath_rcvhdrsize
!= rhdrsize
) {
1378 dev_info(&dd
->pcidev
->dev
,
1379 "Error: can't set protocol header "
1380 "size %u, already %u\n",
1381 rhdrsize
, dd
->ipath_rcvhdrsize
);
1384 ipath_cdbg(VERBOSE
, "Reuse same protocol header "
1385 "size %u\n", dd
->ipath_rcvhdrsize
);
1386 } else if (rhdrsize
> (dd
->ipath_rcvhdrentsize
-
1387 (sizeof(u64
) / sizeof(u32
)))) {
1388 ipath_dbg("Error: can't set protocol header size %u "
1389 "(> max %u)\n", rhdrsize
,
1390 dd
->ipath_rcvhdrentsize
-
1391 (u32
) (sizeof(u64
) / sizeof(u32
)));
1394 dd
->ipath_flags
|= IPATH_RCVHDRSZ_SET
;
1395 dd
->ipath_rcvhdrsize
= rhdrsize
;
1396 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvhdrsize
,
1397 dd
->ipath_rcvhdrsize
);
1398 ipath_cdbg(VERBOSE
, "Set protocol header size to %u\n",
1399 dd
->ipath_rcvhdrsize
);
1405 * ipath_getpiobuf - find an available pio buffer
1406 * @dd: the infinipath device
1407 * @pbufnum: the buffer number is placed here
1409 * do appropriate marking as busy, etc.
1410 * returns buffer number if one found (>=0), negative number is error.
1411 * Used by ipath_layer_send
1413 u32 __iomem
*ipath_getpiobuf(struct ipath_devdata
*dd
, u32
* pbufnum
)
1415 int i
, j
, starti
, updated
= 0;
1416 unsigned piobcnt
, iter
;
1417 unsigned long flags
;
1418 unsigned long *shadow
= dd
->ipath_pioavailshadow
;
1421 piobcnt
= (unsigned)(dd
->ipath_piobcnt2k
1422 + dd
->ipath_piobcnt4k
);
1423 starti
= dd
->ipath_lastport_piobuf
;
1424 iter
= piobcnt
- starti
;
1425 if (dd
->ipath_upd_pio_shadow
) {
1427 * Minor optimization. If we had no buffers on last call,
1428 * start out by doing the update; continue and do scan even
1429 * if no buffers were updated, to be paranoid
1431 ipath_update_pio_bufs(dd
);
1432 /* we scanned here, don't do it at end of scan */
1436 i
= dd
->ipath_lastpioindex
;
1440 * while test_and_set_bit() is atomic, we do that and then the
1441 * change_bit(), and the pair is not. See if this is the cause
1442 * of the remaining armlaunch errors.
1444 spin_lock_irqsave(&ipath_pioavail_lock
, flags
);
1445 for (j
= 0; j
< iter
; j
++, i
++) {
1449 * To avoid bus lock overhead, we first find a candidate
1450 * buffer, then do the test and set, and continue if that
1453 if (test_bit((2 * i
) + 1, shadow
) ||
1454 test_and_set_bit((2 * i
) + 1, shadow
))
1456 /* flip generation bit */
1457 change_bit(2 * i
, shadow
);
1460 spin_unlock_irqrestore(&ipath_pioavail_lock
, flags
);
1463 volatile __le64
*dma
= dd
->ipath_pioavailregs_dma
;
1466 * first time through; shadow exhausted, but may be real
1467 * buffers available, so go see; if any updated, rescan
1471 ipath_update_pio_bufs(dd
);
1476 dd
->ipath_upd_pio_shadow
= 1;
1478 * not atomic, but if we lose one once in a while, that's OK
1480 ipath_stats
.sps_nopiobufs
++;
1481 if (!(++dd
->ipath_consec_nopiobuf
% 100000)) {
1483 "%u pio sends with no bufavail; dmacopy: "
1484 "%llx %llx %llx %llx; shadow: "
1485 "%lx %lx %lx %lx\n",
1486 dd
->ipath_consec_nopiobuf
,
1487 (unsigned long long) le64_to_cpu(dma
[0]),
1488 (unsigned long long) le64_to_cpu(dma
[1]),
1489 (unsigned long long) le64_to_cpu(dma
[2]),
1490 (unsigned long long) le64_to_cpu(dma
[3]),
1491 shadow
[0], shadow
[1], shadow
[2],
1494 * 4 buffers per byte, 4 registers above, cover rest
1497 if ((dd
->ipath_piobcnt2k
+ dd
->ipath_piobcnt4k
) >
1498 (sizeof(shadow
[0]) * 4 * 4))
1499 ipath_dbg("2nd group: dmacopy: %llx %llx "
1500 "%llx %llx; shadow: %lx %lx "
1502 (unsigned long long)
1503 le64_to_cpu(dma
[4]),
1504 (unsigned long long)
1505 le64_to_cpu(dma
[5]),
1506 (unsigned long long)
1507 le64_to_cpu(dma
[6]),
1508 (unsigned long long)
1509 le64_to_cpu(dma
[7]),
1510 shadow
[4], shadow
[5],
1511 shadow
[6], shadow
[7]);
1518 * set next starting place. Since it's just an optimization,
1519 * it doesn't matter who wins on this, so no locking
1521 dd
->ipath_lastpioindex
= i
+ 1;
1522 if (dd
->ipath_upd_pio_shadow
)
1523 dd
->ipath_upd_pio_shadow
= 0;
1524 if (dd
->ipath_consec_nopiobuf
)
1525 dd
->ipath_consec_nopiobuf
= 0;
1526 if (i
< dd
->ipath_piobcnt2k
)
1527 buf
= (u32 __iomem
*) (dd
->ipath_pio2kbase
+
1528 i
* dd
->ipath_palign
);
1530 buf
= (u32 __iomem
*)
1531 (dd
->ipath_pio4kbase
+
1532 (i
- dd
->ipath_piobcnt2k
) * dd
->ipath_4kalign
);
1533 ipath_cdbg(VERBOSE
, "Return piobuf%u %uk @ %p\n",
1534 i
, (i
< dd
->ipath_piobcnt2k
) ? 2 : 4, buf
);
1543 * ipath_create_rcvhdrq - create a receive header queue
1544 * @dd: the infinipath device
1545 * @pd: the port data
1547 * this must be contiguous memory (from an i/o perspective), and must be
1548 * DMA'able (which means for some systems, it will go through an IOMMU,
1549 * or be forced into a low address range).
1551 int ipath_create_rcvhdrq(struct ipath_devdata
*dd
,
1552 struct ipath_portdata
*pd
)
1556 if (!pd
->port_rcvhdrq
) {
1557 dma_addr_t phys_hdrqtail
;
1558 gfp_t gfp_flags
= GFP_USER
| __GFP_COMP
;
1559 int amt
= ALIGN(dd
->ipath_rcvhdrcnt
* dd
->ipath_rcvhdrentsize
*
1560 sizeof(u32
), PAGE_SIZE
);
1562 pd
->port_rcvhdrq
= dma_alloc_coherent(
1563 &dd
->pcidev
->dev
, amt
, &pd
->port_rcvhdrq_phys
,
1566 if (!pd
->port_rcvhdrq
) {
1567 ipath_dev_err(dd
, "attempt to allocate %d bytes "
1568 "for port %u rcvhdrq failed\n",
1569 amt
, pd
->port_port
);
1573 pd
->port_rcvhdrtail_kvaddr
= dma_alloc_coherent(
1574 &dd
->pcidev
->dev
, PAGE_SIZE
, &phys_hdrqtail
, GFP_KERNEL
);
1575 if (!pd
->port_rcvhdrtail_kvaddr
) {
1576 ipath_dev_err(dd
, "attempt to allocate 1 page "
1577 "for port %u rcvhdrqtailaddr failed\n",
1580 dma_free_coherent(&dd
->pcidev
->dev
, amt
,
1581 pd
->port_rcvhdrq
, pd
->port_rcvhdrq_phys
);
1582 pd
->port_rcvhdrq
= NULL
;
1585 pd
->port_rcvhdrqtailaddr_phys
= phys_hdrqtail
;
1587 pd
->port_rcvhdrq_size
= amt
;
1589 ipath_cdbg(VERBOSE
, "%d pages at %p (phys %lx) size=%lu "
1590 "for port %u rcvhdr Q\n",
1591 amt
>> PAGE_SHIFT
, pd
->port_rcvhdrq
,
1592 (unsigned long) pd
->port_rcvhdrq_phys
,
1593 (unsigned long) pd
->port_rcvhdrq_size
,
1596 ipath_cdbg(VERBOSE
, "port %d hdrtailaddr, %llx physical\n",
1598 (unsigned long long) phys_hdrqtail
);
1601 ipath_cdbg(VERBOSE
, "reuse port %d rcvhdrq @%p %llx phys; "
1602 "hdrtailaddr@%p %llx physical\n",
1603 pd
->port_port
, pd
->port_rcvhdrq
,
1604 (unsigned long long) pd
->port_rcvhdrq_phys
,
1605 pd
->port_rcvhdrtail_kvaddr
, (unsigned long long)
1606 pd
->port_rcvhdrqtailaddr_phys
);
1608 /* clear for security and sanity on each use */
1609 memset(pd
->port_rcvhdrq
, 0, pd
->port_rcvhdrq_size
);
1610 if (pd
->port_rcvhdrtail_kvaddr
)
1611 memset(pd
->port_rcvhdrtail_kvaddr
, 0, PAGE_SIZE
);
1614 * tell chip each time we init it, even if we are re-using previous
1615 * memory (we zero the register at process close)
1617 ipath_write_kreg_port(dd
, dd
->ipath_kregs
->kr_rcvhdrtailaddr
,
1618 pd
->port_port
, pd
->port_rcvhdrqtailaddr_phys
);
1619 ipath_write_kreg_port(dd
, dd
->ipath_kregs
->kr_rcvhdraddr
,
1620 pd
->port_port
, pd
->port_rcvhdrq_phys
);
1629 * Flush all sends that might be in the ready to send state, as well as any
1630 * that are in the process of being sent. Used whenever we need to be
1631 * sure the send side is idle. Cleans up all buffer state by canceling
1632 * all pio buffers, and issuing an abort, which cleans up anything in the
1633 * launch fifo. The cancel is superfluous on some chip versions, but
1634 * it's safer to always do it.
1635 * PIOAvail bits are updated by the chip as if normal send had happened.
1637 void ipath_cancel_sends(struct ipath_devdata
*dd
, int restore_sendctrl
)
1639 ipath_dbg("Cancelling all in-progress send buffers\n");
1640 dd
->ipath_lastcancel
= jiffies
+HZ
/2; /* skip armlaunch errs a bit */
1642 * the abort bit is auto-clearing. We read scratch to be sure
1643 * that cancels and the abort have taken effect in the chip.
1645 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
1646 INFINIPATH_S_ABORT
);
1647 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
1648 ipath_disarm_piobufs(dd
, 0,
1649 (unsigned)(dd
->ipath_piobcnt2k
+ dd
->ipath_piobcnt4k
));
1650 if (restore_sendctrl
) /* else done by caller later */
1651 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
1652 dd
->ipath_sendctrl
);
1654 /* and again, be sure all have hit the chip */
1655 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
1659 static void ipath_set_ib_lstate(struct ipath_devdata
*dd
, int which
)
1661 static const char *what
[4] = {
1663 [INFINIPATH_IBCC_LINKCMD_DOWN
] = "DOWN",
1664 [INFINIPATH_IBCC_LINKCMD_ARMED
] = "ARMED",
1665 [INFINIPATH_IBCC_LINKCMD_ACTIVE
] = "ACTIVE"
1667 int linkcmd
= (which
>> INFINIPATH_IBCC_LINKCMD_SHIFT
) &
1668 INFINIPATH_IBCC_LINKCMD_MASK
;
1670 ipath_cdbg(VERBOSE
, "Trying to move unit %u to %s, current ltstate "
1671 "is %s\n", dd
->ipath_unit
,
1673 ipath_ibcstatus_str
[
1675 (dd
, dd
->ipath_kregs
->kr_ibcstatus
) >>
1676 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT
) &
1677 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK
]);
1678 /* flush all queued sends when going to DOWN to be sure that
1679 * they don't block MAD packets */
1680 if (linkcmd
== INFINIPATH_IBCC_LINKCMD_DOWN
)
1681 ipath_cancel_sends(dd
, 1);
1683 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1684 dd
->ipath_ibcctrl
| which
);
1687 int ipath_set_linkstate(struct ipath_devdata
*dd
, u8 newstate
)
1693 case IPATH_IB_LINKDOWN_ONLY
:
1694 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKCMD_DOWN
<<
1695 INFINIPATH_IBCC_LINKCMD_SHIFT
);
1700 case IPATH_IB_LINKDOWN
:
1701 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKINITCMD_POLL
<<
1702 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
1707 case IPATH_IB_LINKDOWN_SLEEP
:
1708 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKINITCMD_SLEEP
<<
1709 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
1714 case IPATH_IB_LINKDOWN_DISABLE
:
1715 ipath_set_ib_lstate(dd
,
1716 INFINIPATH_IBCC_LINKINITCMD_DISABLE
<<
1717 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
1722 case IPATH_IB_LINKARM
:
1723 if (dd
->ipath_flags
& IPATH_LINKARMED
) {
1727 if (!(dd
->ipath_flags
&
1728 (IPATH_LINKINIT
| IPATH_LINKACTIVE
))) {
1732 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKCMD_ARMED
<<
1733 INFINIPATH_IBCC_LINKCMD_SHIFT
);
1735 * Since the port can transition to ACTIVE by receiving
1736 * a non VL 15 packet, wait for either state.
1738 lstate
= IPATH_LINKARMED
| IPATH_LINKACTIVE
;
1741 case IPATH_IB_LINKACTIVE
:
1742 if (dd
->ipath_flags
& IPATH_LINKACTIVE
) {
1746 if (!(dd
->ipath_flags
& IPATH_LINKARMED
)) {
1750 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKCMD_ACTIVE
<<
1751 INFINIPATH_IBCC_LINKCMD_SHIFT
);
1752 lstate
= IPATH_LINKACTIVE
;
1755 case IPATH_IB_LINK_LOOPBACK
:
1756 dev_info(&dd
->pcidev
->dev
, "Enabling IB local loopback\n");
1757 dd
->ipath_ibcctrl
|= INFINIPATH_IBCC_LOOPBACK
;
1758 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1761 goto bail
; // no state change to wait for
1763 case IPATH_IB_LINK_EXTERNAL
:
1764 dev_info(&dd
->pcidev
->dev
, "Disabling IB local loopback (normal)\n");
1765 dd
->ipath_ibcctrl
&= ~INFINIPATH_IBCC_LOOPBACK
;
1766 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1769 goto bail
; // no state change to wait for
1772 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate
);
1776 ret
= ipath_wait_linkstate(dd
, lstate
, 2000);
1783 * ipath_set_mtu - set the MTU
1784 * @dd: the infinipath device
1787 * we can handle "any" incoming size, the issue here is whether we
1788 * need to restrict our outgoing size. For now, we don't do any
1789 * sanity checking on this, and we don't deal with what happens to
1790 * programs that are already running when the size changes.
1791 * NOTE: changing the MTU will usually cause the IBC to go back to
1792 * link initialize (IPATH_IBSTATE_INIT) state...
1794 int ipath_set_mtu(struct ipath_devdata
*dd
, u16 arg
)
1801 * mtu is IB data payload max. It's the largest power of 2 less
1802 * than piosize (or even larger, since it only really controls the
1803 * largest we can receive; we can send the max of the mtu and
1804 * piosize). We check that it's one of the valid IB sizes.
1806 if (arg
!= 256 && arg
!= 512 && arg
!= 1024 && arg
!= 2048 &&
1807 (arg
!= 4096 || !ipath_mtu4096
)) {
1808 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg
);
1812 if (dd
->ipath_ibmtu
== arg
) {
1813 ret
= 0; /* same as current */
1817 piosize
= dd
->ipath_ibmaxlen
;
1818 dd
->ipath_ibmtu
= arg
;
1820 if (arg
>= (piosize
- IPATH_PIO_MAXIBHDR
)) {
1821 /* Only if it's not the initial value (or reset to it) */
1822 if (piosize
!= dd
->ipath_init_ibmaxlen
) {
1823 if (arg
> piosize
&& arg
<= dd
->ipath_init_ibmaxlen
)
1824 piosize
= dd
->ipath_init_ibmaxlen
;
1825 dd
->ipath_ibmaxlen
= piosize
;
1828 } else if ((arg
+ IPATH_PIO_MAXIBHDR
) != dd
->ipath_ibmaxlen
) {
1829 piosize
= arg
+ IPATH_PIO_MAXIBHDR
;
1830 ipath_cdbg(VERBOSE
, "ibmaxlen was 0x%x, setting to 0x%x "
1831 "(mtu 0x%x)\n", dd
->ipath_ibmaxlen
, piosize
,
1833 dd
->ipath_ibmaxlen
= piosize
;
1838 u64 ibc
= dd
->ipath_ibcctrl
, ibdw
;
1840 * update our housekeeping variables, and set IBC max
1841 * size, same as init code; max IBC is max we allow in
1842 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
1844 dd
->ipath_ibmaxlen
= piosize
- 2 * sizeof(u32
);
1845 ibdw
= (dd
->ipath_ibmaxlen
>> 2) + 1;
1846 ibc
&= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK
<<
1847 dd
->ibcc_mpl_shift
);
1848 ibc
|= ibdw
<< dd
->ibcc_mpl_shift
;
1849 dd
->ipath_ibcctrl
= ibc
;
1850 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
,
1852 dd
->ipath_f_tidtemplate(dd
);
1861 int ipath_set_lid(struct ipath_devdata
*dd
, u32 arg
, u8 lmc
)
1863 dd
->ipath_lid
= arg
;
1864 dd
->ipath_lmc
= lmc
;
1871 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
1872 * @dd: the infinipath device
1873 * @regno: the register number to write
1874 * @port: the port containing the register
1875 * @value: the value to write
1877 * Registers that vary with the chip implementation constants (port)
1880 void ipath_write_kreg_port(const struct ipath_devdata
*dd
, ipath_kreg regno
,
1881 unsigned port
, u64 value
)
1885 if (port
< dd
->ipath_portcnt
&&
1886 (regno
== dd
->ipath_kregs
->kr_rcvhdraddr
||
1887 regno
== dd
->ipath_kregs
->kr_rcvhdrtailaddr
))
1888 where
= regno
+ port
;
1892 ipath_write_kreg(dd
, where
, value
);
1896 * Following deal with the "obviously simple" task of overriding the state
1897 * of the LEDS, which normally indicate link physical and logical status.
1898 * The complications arise in dealing with different hardware mappings
1899 * and the board-dependent routine being called from interrupts.
1900 * and then there's the requirement to _flash_ them.
1902 #define LED_OVER_FREQ_SHIFT 8
1903 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
1904 /* Below is "non-zero" to force override, but both actual LEDs are off */
1905 #define LED_OVER_BOTH_OFF (8)
1907 static void ipath_run_led_override(unsigned long opaque
)
1909 struct ipath_devdata
*dd
= (struct ipath_devdata
*)opaque
;
1912 u64 lstate
, ltstate
, val
;
1914 if (!(dd
->ipath_flags
& IPATH_INITTED
))
1917 pidx
= dd
->ipath_led_override_phase
++ & 1;
1918 dd
->ipath_led_override
= dd
->ipath_led_override_vals
[pidx
];
1919 timeoff
= dd
->ipath_led_override_timeoff
;
1922 * below potentially restores the LED values per current status,
1923 * should also possibly setup the traffic-blink register,
1924 * but leave that to per-chip functions.
1926 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_ibcstatus
);
1927 ltstate
= (val
>> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT
) &
1928 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK
;
1929 lstate
= (val
>> INFINIPATH_IBCS_LINKSTATE_SHIFT
) &
1930 INFINIPATH_IBCS_LINKSTATE_MASK
;
1932 dd
->ipath_f_setextled(dd
, lstate
, ltstate
);
1933 mod_timer(&dd
->ipath_led_override_timer
, jiffies
+ timeoff
);
1936 void ipath_set_led_override(struct ipath_devdata
*dd
, unsigned int val
)
1940 if (!(dd
->ipath_flags
& IPATH_INITTED
))
1943 /* First check if we are blinking. If not, use 1HZ polling */
1945 freq
= (val
& LED_OVER_FREQ_MASK
) >> LED_OVER_FREQ_SHIFT
;
1948 /* For blink, set each phase from one nybble of val */
1949 dd
->ipath_led_override_vals
[0] = val
& 0xF;
1950 dd
->ipath_led_override_vals
[1] = (val
>> 4) & 0xF;
1951 timeoff
= (HZ
<< 4)/freq
;
1953 /* Non-blink set both phases the same. */
1954 dd
->ipath_led_override_vals
[0] = val
& 0xF;
1955 dd
->ipath_led_override_vals
[1] = val
& 0xF;
1957 dd
->ipath_led_override_timeoff
= timeoff
;
1960 * If the timer has not already been started, do so. Use a "quick"
1961 * timeout so the function will be called soon, to look at our request.
1963 if (atomic_inc_return(&dd
->ipath_led_override_timer_active
) == 1) {
1964 /* Need to start timer */
1965 init_timer(&dd
->ipath_led_override_timer
);
1966 dd
->ipath_led_override_timer
.function
=
1967 ipath_run_led_override
;
1968 dd
->ipath_led_override_timer
.data
= (unsigned long) dd
;
1969 dd
->ipath_led_override_timer
.expires
= jiffies
+ 1;
1970 add_timer(&dd
->ipath_led_override_timer
);
1972 atomic_dec(&dd
->ipath_led_override_timer_active
);
1977 * ipath_shutdown_device - shut down a device
1978 * @dd: the infinipath device
1980 * This is called to make the device quiet when we are about to
1981 * unload the driver, and also when the device is administratively
1982 * disabled. It does not free any data structures.
1983 * Everything it does has to be setup again by ipath_init_chip(dd,1)
1985 void ipath_shutdown_device(struct ipath_devdata
*dd
)
1987 unsigned long flags
;
1989 ipath_dbg("Shutting down the device\n");
1991 dd
->ipath_flags
|= IPATH_LINKUNK
;
1992 dd
->ipath_flags
&= ~(IPATH_INITTED
| IPATH_LINKDOWN
|
1993 IPATH_LINKINIT
| IPATH_LINKARMED
|
1995 *dd
->ipath_statusp
&= ~(IPATH_STATUS_IB_CONF
|
1996 IPATH_STATUS_IB_READY
);
1998 /* mask interrupts, but not errors */
1999 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intmask
, 0ULL);
2001 dd
->ipath_rcvctrl
= 0;
2002 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvctrl
,
2006 * gracefully stop all sends allowing any in progress to trickle out
2009 spin_lock_irqsave(&dd
->ipath_sendctrl_lock
, flags
);
2010 dd
->ipath_sendctrl
= 0;
2011 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
, dd
->ipath_sendctrl
);
2013 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
2014 spin_unlock_irqrestore(&dd
->ipath_sendctrl_lock
, flags
);
2017 * enough for anything that's going to trickle out to have actually
2022 ipath_set_ib_lstate(dd
, INFINIPATH_IBCC_LINKINITCMD_DISABLE
<<
2023 INFINIPATH_IBCC_LINKINITCMD_SHIFT
);
2024 ipath_cancel_sends(dd
, 0);
2026 signal_ib_event(dd
, IB_EVENT_PORT_ERR
);
2029 dd
->ipath_control
&= ~INFINIPATH_C_LINKENABLE
;
2030 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
,
2031 dd
->ipath_control
| INFINIPATH_C_FREEZEMODE
);
2034 * clear SerdesEnable and turn the leds off; do this here because
2035 * we are unloading, so don't count on interrupts to move along
2036 * Turn the LEDs off explictly for the same reason.
2038 dd
->ipath_f_quiet_serdes(dd
);
2040 if (dd
->ipath_stats_timer_active
) {
2041 del_timer_sync(&dd
->ipath_stats_timer
);
2042 dd
->ipath_stats_timer_active
= 0;
2046 * clear all interrupts and errors, so that the next time the driver
2047 * is loaded or device is enabled, we know that whatever is set
2048 * happened while we were unloaded
2050 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrclear
,
2051 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED
);
2052 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errorclear
, -1LL);
2053 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intclear
, -1LL);
2055 ipath_cdbg(VERBOSE
, "Flush time and errors to EEPROM\n");
2056 ipath_update_eeprom_log(dd
);
2060 * ipath_free_pddata - free a port's allocated data
2061 * @dd: the infinipath device
2062 * @pd: the portdata structure
2064 * free up any allocated data for a port
2065 * This should not touch anything that would affect a simultaneous
2066 * re-allocation of port data, because it is called after ipath_mutex
2067 * is released (and can be called from reinit as well).
2068 * It should never change any chip state, or global driver state.
2069 * (The only exception to global state is freeing the port0 port0_skbs.)
2071 void ipath_free_pddata(struct ipath_devdata
*dd
, struct ipath_portdata
*pd
)
2076 if (pd
->port_rcvhdrq
) {
2077 ipath_cdbg(VERBOSE
, "free closed port %d rcvhdrq @ %p "
2078 "(size=%lu)\n", pd
->port_port
, pd
->port_rcvhdrq
,
2079 (unsigned long) pd
->port_rcvhdrq_size
);
2080 dma_free_coherent(&dd
->pcidev
->dev
, pd
->port_rcvhdrq_size
,
2081 pd
->port_rcvhdrq
, pd
->port_rcvhdrq_phys
);
2082 pd
->port_rcvhdrq
= NULL
;
2083 if (pd
->port_rcvhdrtail_kvaddr
) {
2084 dma_free_coherent(&dd
->pcidev
->dev
, PAGE_SIZE
,
2085 pd
->port_rcvhdrtail_kvaddr
,
2086 pd
->port_rcvhdrqtailaddr_phys
);
2087 pd
->port_rcvhdrtail_kvaddr
= NULL
;
2090 if (pd
->port_port
&& pd
->port_rcvegrbuf
) {
2093 for (e
= 0; e
< pd
->port_rcvegrbuf_chunks
; e
++) {
2094 void *base
= pd
->port_rcvegrbuf
[e
];
2095 size_t size
= pd
->port_rcvegrbuf_size
;
2097 ipath_cdbg(VERBOSE
, "egrbuf free(%p, %lu), "
2098 "chunk %u/%u\n", base
,
2099 (unsigned long) size
,
2100 e
, pd
->port_rcvegrbuf_chunks
);
2101 dma_free_coherent(&dd
->pcidev
->dev
, size
,
2102 base
, pd
->port_rcvegrbuf_phys
[e
]);
2104 kfree(pd
->port_rcvegrbuf
);
2105 pd
->port_rcvegrbuf
= NULL
;
2106 kfree(pd
->port_rcvegrbuf_phys
);
2107 pd
->port_rcvegrbuf_phys
= NULL
;
2108 pd
->port_rcvegrbuf_chunks
= 0;
2109 } else if (pd
->port_port
== 0 && dd
->ipath_port0_skbinfo
) {
2111 struct ipath_skbinfo
*skbinfo
= dd
->ipath_port0_skbinfo
;
2113 dd
->ipath_port0_skbinfo
= NULL
;
2114 ipath_cdbg(VERBOSE
, "free closed port %d "
2115 "ipath_port0_skbinfo @ %p\n", pd
->port_port
,
2117 for (e
= 0; e
< dd
->ipath_rcvegrcnt
; e
++)
2118 if (skbinfo
[e
].skb
) {
2119 pci_unmap_single(dd
->pcidev
, skbinfo
[e
].phys
,
2121 PCI_DMA_FROMDEVICE
);
2122 dev_kfree_skb(skbinfo
[e
].skb
);
2126 kfree(pd
->port_tid_pg_list
);
2127 vfree(pd
->subport_uregbase
);
2128 vfree(pd
->subport_rcvegrbuf
);
2129 vfree(pd
->subport_rcvhdr_base
);
2133 static int __init
infinipath_init(void)
2137 if (ipath_debug
& __IPATH_DBG
)
2138 printk(KERN_INFO DRIVER_LOAD_MSG
"%s", ib_ipath_version
);
2141 * These must be called before the driver is registered with
2142 * the PCI subsystem.
2144 idr_init(&unit_table
);
2145 if (!idr_pre_get(&unit_table
, GFP_KERNEL
)) {
2150 ret
= pci_register_driver(&ipath_driver
);
2152 printk(KERN_ERR IPATH_DRV_NAME
2153 ": Unable to register driver: error %d\n", -ret
);
2157 ret
= ipath_init_ipathfs();
2159 printk(KERN_ERR IPATH_DRV_NAME
": Unable to create "
2160 "ipathfs: error %d\n", -ret
);
2167 pci_unregister_driver(&ipath_driver
);
2170 idr_destroy(&unit_table
);
2176 static void __exit
infinipath_cleanup(void)
2178 ipath_exit_ipathfs();
2180 ipath_cdbg(VERBOSE
, "Unregistering pci driver\n");
2181 pci_unregister_driver(&ipath_driver
);
2183 idr_destroy(&unit_table
);
2187 * ipath_reset_device - reset the chip if possible
2188 * @unit: the device to reset
2190 * Whether or not reset is successful, we attempt to re-initialize the chip
2191 * (that is, much like a driver unload/reload). We clear the INITTED flag
2192 * so that the various entry points will fail until we reinitialize. For
2193 * now, we only allow this if no user ports are open that use chip resources
2195 int ipath_reset_device(int unit
)
2198 struct ipath_devdata
*dd
= ipath_lookup(unit
);
2205 if (atomic_read(&dd
->ipath_led_override_timer_active
)) {
2206 /* Need to stop LED timer, _then_ shut off LEDs */
2207 del_timer_sync(&dd
->ipath_led_override_timer
);
2208 atomic_set(&dd
->ipath_led_override_timer_active
, 0);
2211 /* Shut off LEDs after we are sure timer is not running */
2212 dd
->ipath_led_override
= LED_OVER_BOTH_OFF
;
2213 dd
->ipath_f_setextled(dd
, 0, 0);
2215 dev_info(&dd
->pcidev
->dev
, "Reset on unit %u requested\n", unit
);
2217 if (!dd
->ipath_kregbase
|| !(dd
->ipath_flags
& IPATH_PRESENT
)) {
2218 dev_info(&dd
->pcidev
->dev
, "Invalid unit number %u or "
2219 "not initialized or not present\n", unit
);
2225 for (i
= 1; i
< dd
->ipath_cfgports
; i
++) {
2226 if (dd
->ipath_pd
[i
] && dd
->ipath_pd
[i
]->port_cnt
) {
2227 ipath_dbg("unit %u port %d is in use "
2228 "(PID %u cmd %s), can't reset\n",
2230 dd
->ipath_pd
[i
]->port_pid
,
2231 dd
->ipath_pd
[i
]->port_comm
);
2237 dd
->ipath_flags
&= ~IPATH_INITTED
;
2238 ret
= dd
->ipath_f_reset(dd
);
2240 ipath_dbg("reset was not successful\n");
2241 ipath_dbg("Trying to reinitialize unit %u after reset attempt\n",
2243 ret
= ipath_init_chip(dd
, 1);
2245 ipath_dev_err(dd
, "Reinitialize unit %u after "
2246 "reset failed with %d\n", unit
, ret
);
2248 dev_info(&dd
->pcidev
->dev
, "Reinitialized unit %u after "
2249 "resetting\n", unit
);
2255 int ipath_set_rx_pol_inv(struct ipath_devdata
*dd
, u8 new_pol_inv
)
2258 if ( new_pol_inv
> INFINIPATH_XGXS_RX_POL_MASK
) {
2261 if ( dd
->ipath_rx_pol_inv
!= new_pol_inv
) {
2262 dd
->ipath_rx_pol_inv
= new_pol_inv
;
2263 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_xgxsconfig
);
2264 val
&= ~(INFINIPATH_XGXS_RX_POL_MASK
<<
2265 INFINIPATH_XGXS_RX_POL_SHIFT
);
2266 val
|= ((u64
)dd
->ipath_rx_pol_inv
) <<
2267 INFINIPATH_XGXS_RX_POL_SHIFT
;
2268 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_xgxsconfig
, val
);
2274 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2275 * the 7220, which is count-based, rather than trigger-based. Safe for the
2276 * driver check, since it's at init. Not completely safe when used for
2277 * user-mode checking, since some error checking can be lost, but not
2278 * particularly risky, and only has problematic side-effects in the face of
2279 * very buggy user code. There is no reference counting, but that's also
2280 * fine, given the intended use.
2282 void ipath_enable_armlaunch(struct ipath_devdata
*dd
)
2284 dd
->ipath_lasterror
&= ~INFINIPATH_E_SPIOARMLAUNCH
;
2285 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errorclear
,
2286 INFINIPATH_E_SPIOARMLAUNCH
);
2287 dd
->ipath_errormask
|= INFINIPATH_E_SPIOARMLAUNCH
;
2288 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errormask
,
2289 dd
->ipath_errormask
);
2292 void ipath_disable_armlaunch(struct ipath_devdata
*dd
)
2294 /* so don't re-enable if already set */
2295 dd
->ipath_maskederrs
&= ~INFINIPATH_E_SPIOARMLAUNCH
;
2296 dd
->ipath_errormask
&= ~INFINIPATH_E_SPIOARMLAUNCH
;
2297 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errormask
,
2298 dd
->ipath_errormask
);
2301 module_init(infinipath_init
);
2302 module_exit(infinipath_cleanup
);