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RDMA/cxgb3: Fix error paths in post_send and post_recv
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / infiniband / hw / cxgb3 / iwch_qp.c
1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/sched.h>
33 #include "iwch_provider.h"
34 #include "iwch.h"
35 #include "iwch_cm.h"
36 #include "cxio_hal.h"
37 #include "cxio_resource.h"
38
39 #define NO_SUPPORT -1
40
41 static int build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
42 u8 * flit_cnt)
43 {
44 int i;
45 u32 plen;
46
47 switch (wr->opcode) {
48 case IB_WR_SEND:
49 if (wr->send_flags & IB_SEND_SOLICITED)
50 wqe->send.rdmaop = T3_SEND_WITH_SE;
51 else
52 wqe->send.rdmaop = T3_SEND;
53 wqe->send.rem_stag = 0;
54 break;
55 case IB_WR_SEND_WITH_INV:
56 if (wr->send_flags & IB_SEND_SOLICITED)
57 wqe->send.rdmaop = T3_SEND_WITH_SE_INV;
58 else
59 wqe->send.rdmaop = T3_SEND_WITH_INV;
60 wqe->send.rem_stag = cpu_to_be32(wr->ex.invalidate_rkey);
61 break;
62 default:
63 return -EINVAL;
64 }
65 if (wr->num_sge > T3_MAX_SGE)
66 return -EINVAL;
67 wqe->send.reserved[0] = 0;
68 wqe->send.reserved[1] = 0;
69 wqe->send.reserved[2] = 0;
70 plen = 0;
71 for (i = 0; i < wr->num_sge; i++) {
72 if ((plen + wr->sg_list[i].length) < plen)
73 return -EMSGSIZE;
74
75 plen += wr->sg_list[i].length;
76 wqe->send.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
77 wqe->send.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
78 wqe->send.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
79 }
80 wqe->send.num_sgle = cpu_to_be32(wr->num_sge);
81 *flit_cnt = 4 + ((wr->num_sge) << 1);
82 wqe->send.plen = cpu_to_be32(plen);
83 return 0;
84 }
85
86 static int build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
87 u8 *flit_cnt)
88 {
89 int i;
90 u32 plen;
91 if (wr->num_sge > T3_MAX_SGE)
92 return -EINVAL;
93 wqe->write.rdmaop = T3_RDMA_WRITE;
94 wqe->write.reserved[0] = 0;
95 wqe->write.reserved[1] = 0;
96 wqe->write.reserved[2] = 0;
97 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
98 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
99
100 if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
101 plen = 4;
102 wqe->write.sgl[0].stag = wr->ex.imm_data;
103 wqe->write.sgl[0].len = cpu_to_be32(0);
104 wqe->write.num_sgle = cpu_to_be32(0);
105 *flit_cnt = 6;
106 } else {
107 plen = 0;
108 for (i = 0; i < wr->num_sge; i++) {
109 if ((plen + wr->sg_list[i].length) < plen) {
110 return -EMSGSIZE;
111 }
112 plen += wr->sg_list[i].length;
113 wqe->write.sgl[i].stag =
114 cpu_to_be32(wr->sg_list[i].lkey);
115 wqe->write.sgl[i].len =
116 cpu_to_be32(wr->sg_list[i].length);
117 wqe->write.sgl[i].to =
118 cpu_to_be64(wr->sg_list[i].addr);
119 }
120 wqe->write.num_sgle = cpu_to_be32(wr->num_sge);
121 *flit_cnt = 5 + ((wr->num_sge) << 1);
122 }
123 wqe->write.plen = cpu_to_be32(plen);
124 return 0;
125 }
126
127 static int build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
128 u8 *flit_cnt)
129 {
130 if (wr->num_sge > 1)
131 return -EINVAL;
132 wqe->read.rdmaop = T3_READ_REQ;
133 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
134 wqe->read.local_inv = 1;
135 else
136 wqe->read.local_inv = 0;
137 wqe->read.reserved[0] = 0;
138 wqe->read.reserved[1] = 0;
139 wqe->read.rem_stag = cpu_to_be32(wr->wr.rdma.rkey);
140 wqe->read.rem_to = cpu_to_be64(wr->wr.rdma.remote_addr);
141 wqe->read.local_stag = cpu_to_be32(wr->sg_list[0].lkey);
142 wqe->read.local_len = cpu_to_be32(wr->sg_list[0].length);
143 wqe->read.local_to = cpu_to_be64(wr->sg_list[0].addr);
144 *flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
145 return 0;
146 }
147
148 static int build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
149 u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
150 {
151 int i;
152 __be64 *p;
153
154 if (wr->wr.fast_reg.page_list_len > T3_MAX_FASTREG_DEPTH)
155 return -EINVAL;
156 *wr_cnt = 1;
157 wqe->fastreg.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
158 wqe->fastreg.len = cpu_to_be32(wr->wr.fast_reg.length);
159 wqe->fastreg.va_base_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
160 wqe->fastreg.va_base_lo_fbo =
161 cpu_to_be32(wr->wr.fast_reg.iova_start & 0xffffffff);
162 wqe->fastreg.page_type_perms = cpu_to_be32(
163 V_FR_PAGE_COUNT(wr->wr.fast_reg.page_list_len) |
164 V_FR_PAGE_SIZE(wr->wr.fast_reg.page_shift-12) |
165 V_FR_TYPE(TPT_VATO) |
166 V_FR_PERMS(iwch_ib_to_tpt_access(wr->wr.fast_reg.access_flags)));
167 p = &wqe->fastreg.pbl_addrs[0];
168 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++) {
169
170 /* If we need a 2nd WR, then set it up */
171 if (i == T3_MAX_FASTREG_FRAG) {
172 *wr_cnt = 2;
173 wqe = (union t3_wr *)(wq->queue +
174 Q_PTR2IDX((wq->wptr+1), wq->size_log2));
175 build_fw_riwrh((void *)wqe, T3_WR_FASTREG, 0,
176 Q_GENBIT(wq->wptr + 1, wq->size_log2),
177 0, 1 + wr->wr.fast_reg.page_list_len - T3_MAX_FASTREG_FRAG,
178 T3_EOP);
179
180 p = &wqe->pbl_frag.pbl_addrs[0];
181 }
182 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
183 }
184 *flit_cnt = 5 + wr->wr.fast_reg.page_list_len;
185 if (*flit_cnt > 15)
186 *flit_cnt = 15;
187 return 0;
188 }
189
190 static int build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
191 u8 *flit_cnt)
192 {
193 wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
194 wqe->local_inv.reserved = 0;
195 *flit_cnt = sizeof(struct t3_local_inv_wr) >> 3;
196 return 0;
197 }
198
199 static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
200 u32 num_sgle, u32 * pbl_addr, u8 * page_size)
201 {
202 int i;
203 struct iwch_mr *mhp;
204 u64 offset;
205 for (i = 0; i < num_sgle; i++) {
206
207 mhp = get_mhp(rhp, (sg_list[i].lkey) >> 8);
208 if (!mhp) {
209 PDBG("%s %d\n", __func__, __LINE__);
210 return -EIO;
211 }
212 if (!mhp->attr.state) {
213 PDBG("%s %d\n", __func__, __LINE__);
214 return -EIO;
215 }
216 if (mhp->attr.zbva) {
217 PDBG("%s %d\n", __func__, __LINE__);
218 return -EIO;
219 }
220
221 if (sg_list[i].addr < mhp->attr.va_fbo) {
222 PDBG("%s %d\n", __func__, __LINE__);
223 return -EINVAL;
224 }
225 if (sg_list[i].addr + ((u64) sg_list[i].length) <
226 sg_list[i].addr) {
227 PDBG("%s %d\n", __func__, __LINE__);
228 return -EINVAL;
229 }
230 if (sg_list[i].addr + ((u64) sg_list[i].length) >
231 mhp->attr.va_fbo + ((u64) mhp->attr.len)) {
232 PDBG("%s %d\n", __func__, __LINE__);
233 return -EINVAL;
234 }
235 offset = sg_list[i].addr - mhp->attr.va_fbo;
236 offset += mhp->attr.va_fbo &
237 ((1UL << (12 + mhp->attr.page_size)) - 1);
238 pbl_addr[i] = ((mhp->attr.pbl_addr -
239 rhp->rdev.rnic_info.pbl_base) >> 3) +
240 (offset >> (12 + mhp->attr.page_size));
241 page_size[i] = mhp->attr.page_size;
242 }
243 return 0;
244 }
245
246 static int build_rdma_recv(struct iwch_qp *qhp, union t3_wr *wqe,
247 struct ib_recv_wr *wr)
248 {
249 int i, err = 0;
250 u32 pbl_addr[T3_MAX_SGE];
251 u8 page_size[T3_MAX_SGE];
252
253 err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr,
254 page_size);
255 if (err)
256 return err;
257 wqe->recv.pagesz[0] = page_size[0];
258 wqe->recv.pagesz[1] = page_size[1];
259 wqe->recv.pagesz[2] = page_size[2];
260 wqe->recv.pagesz[3] = page_size[3];
261 wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
262 for (i = 0; i < wr->num_sge; i++) {
263 wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
264 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
265
266 /* to in the WQE == the offset into the page */
267 wqe->recv.sgl[i].to = cpu_to_be64(((u32)wr->sg_list[i].addr) &
268 ((1UL << (12 + page_size[i])) - 1));
269
270 /* pbl_addr is the adapters address in the PBL */
271 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
272 }
273 for (; i < T3_MAX_SGE; i++) {
274 wqe->recv.sgl[i].stag = 0;
275 wqe->recv.sgl[i].len = 0;
276 wqe->recv.sgl[i].to = 0;
277 wqe->recv.pbl_addr[i] = 0;
278 }
279 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
280 qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
281 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
282 qhp->wq.rq_size_log2)].pbl_addr = 0;
283 return 0;
284 }
285
286 static int build_zero_stag_recv(struct iwch_qp *qhp, union t3_wr *wqe,
287 struct ib_recv_wr *wr)
288 {
289 int i;
290 u32 pbl_addr;
291 u32 pbl_offset;
292
293
294 /*
295 * The T3 HW requires the PBL in the HW recv descriptor to reference
296 * a PBL entry. So we allocate the max needed PBL memory here and pass
297 * it to the uP in the recv WR. The uP will build the PBL and setup
298 * the HW recv descriptor.
299 */
300 pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE);
301 if (!pbl_addr)
302 return -ENOMEM;
303
304 /*
305 * Compute the 8B aligned offset.
306 */
307 pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3;
308
309 wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
310
311 for (i = 0; i < wr->num_sge; i++) {
312
313 /*
314 * Use a 128MB page size. This and an imposed 128MB
315 * sge length limit allows us to require only a 2-entry HW
316 * PBL for each SGE. This restriction is acceptable since
317 * since it is not possible to allocate 128MB of contiguous
318 * DMA coherent memory!
319 */
320 if (wr->sg_list[i].length > T3_STAG0_MAX_PBE_LEN)
321 return -EINVAL;
322 wqe->recv.pagesz[i] = T3_STAG0_PAGE_SHIFT;
323
324 /*
325 * T3 restricts a recv to all zero-stag or all non-zero-stag.
326 */
327 if (wr->sg_list[i].lkey != 0)
328 return -EINVAL;
329 wqe->recv.sgl[i].stag = 0;
330 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
331 wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
332 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset);
333 pbl_offset += 2;
334 }
335 for (; i < T3_MAX_SGE; i++) {
336 wqe->recv.pagesz[i] = 0;
337 wqe->recv.sgl[i].stag = 0;
338 wqe->recv.sgl[i].len = 0;
339 wqe->recv.sgl[i].to = 0;
340 wqe->recv.pbl_addr[i] = 0;
341 }
342 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
343 qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
344 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
345 qhp->wq.rq_size_log2)].pbl_addr = pbl_addr;
346 return 0;
347 }
348
349 int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
350 struct ib_send_wr **bad_wr)
351 {
352 int err = 0;
353 u8 uninitialized_var(t3_wr_flit_cnt);
354 enum t3_wr_opcode t3_wr_opcode = 0;
355 enum t3_wr_flags t3_wr_flags;
356 struct iwch_qp *qhp;
357 u32 idx;
358 union t3_wr *wqe;
359 u32 num_wrs;
360 unsigned long flag;
361 struct t3_swsq *sqp;
362 int wr_cnt = 1;
363
364 qhp = to_iwch_qp(ibqp);
365 spin_lock_irqsave(&qhp->lock, flag);
366 if (qhp->attr.state > IWCH_QP_STATE_RTS) {
367 spin_unlock_irqrestore(&qhp->lock, flag);
368 err = -EINVAL;
369 goto out;
370 }
371 num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
372 qhp->wq.sq_size_log2);
373 if (num_wrs <= 0) {
374 spin_unlock_irqrestore(&qhp->lock, flag);
375 err = -ENOMEM;
376 goto out;
377 }
378 while (wr) {
379 if (num_wrs == 0) {
380 err = -ENOMEM;
381 break;
382 }
383 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
384 wqe = (union t3_wr *) (qhp->wq.queue + idx);
385 t3_wr_flags = 0;
386 if (wr->send_flags & IB_SEND_SOLICITED)
387 t3_wr_flags |= T3_SOLICITED_EVENT_FLAG;
388 if (wr->send_flags & IB_SEND_SIGNALED)
389 t3_wr_flags |= T3_COMPLETION_FLAG;
390 sqp = qhp->wq.sq +
391 Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
392 switch (wr->opcode) {
393 case IB_WR_SEND:
394 case IB_WR_SEND_WITH_INV:
395 if (wr->send_flags & IB_SEND_FENCE)
396 t3_wr_flags |= T3_READ_FENCE_FLAG;
397 t3_wr_opcode = T3_WR_SEND;
398 err = build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
399 break;
400 case IB_WR_RDMA_WRITE:
401 case IB_WR_RDMA_WRITE_WITH_IMM:
402 t3_wr_opcode = T3_WR_WRITE;
403 err = build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
404 break;
405 case IB_WR_RDMA_READ:
406 case IB_WR_RDMA_READ_WITH_INV:
407 t3_wr_opcode = T3_WR_READ;
408 t3_wr_flags = 0; /* T3 reads are always signaled */
409 err = build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
410 if (err)
411 break;
412 sqp->read_len = wqe->read.local_len;
413 if (!qhp->wq.oldest_read)
414 qhp->wq.oldest_read = sqp;
415 break;
416 case IB_WR_FAST_REG_MR:
417 t3_wr_opcode = T3_WR_FASTREG;
418 err = build_fastreg(wqe, wr, &t3_wr_flit_cnt,
419 &wr_cnt, &qhp->wq);
420 break;
421 case IB_WR_LOCAL_INV:
422 if (wr->send_flags & IB_SEND_FENCE)
423 t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
424 t3_wr_opcode = T3_WR_INV_STAG;
425 err = build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
426 break;
427 default:
428 PDBG("%s post of type=%d TBD!\n", __func__,
429 wr->opcode);
430 err = -EINVAL;
431 }
432 if (err)
433 break;
434 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
435 sqp->wr_id = wr->wr_id;
436 sqp->opcode = wr2opcode(t3_wr_opcode);
437 sqp->sq_wptr = qhp->wq.sq_wptr;
438 sqp->complete = 0;
439 sqp->signaled = (wr->send_flags & IB_SEND_SIGNALED);
440
441 build_fw_riwrh((void *) wqe, t3_wr_opcode, t3_wr_flags,
442 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
443 0, t3_wr_flit_cnt,
444 (wr_cnt == 1) ? T3_SOPEOP : T3_SOP);
445 PDBG("%s cookie 0x%llx wq idx 0x%x swsq idx %ld opcode %d\n",
446 __func__, (unsigned long long) wr->wr_id, idx,
447 Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2),
448 sqp->opcode);
449 wr = wr->next;
450 num_wrs--;
451 qhp->wq.wptr += wr_cnt;
452 ++(qhp->wq.sq_wptr);
453 }
454 spin_unlock_irqrestore(&qhp->lock, flag);
455 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
456
457 out:
458 if (err)
459 *bad_wr = wr;
460 return err;
461 }
462
463 int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
464 struct ib_recv_wr **bad_wr)
465 {
466 int err = 0;
467 struct iwch_qp *qhp;
468 u32 idx;
469 union t3_wr *wqe;
470 u32 num_wrs;
471 unsigned long flag;
472
473 qhp = to_iwch_qp(ibqp);
474 spin_lock_irqsave(&qhp->lock, flag);
475 if (qhp->attr.state > IWCH_QP_STATE_RTS) {
476 spin_unlock_irqrestore(&qhp->lock, flag);
477 err = -EINVAL;
478 goto out;
479 }
480 num_wrs = Q_FREECNT(qhp->wq.rq_rptr, qhp->wq.rq_wptr,
481 qhp->wq.rq_size_log2) - 1;
482 if (!wr) {
483 spin_unlock_irqrestore(&qhp->lock, flag);
484 err = -ENOMEM;
485 goto out;
486 }
487 while (wr) {
488 if (wr->num_sge > T3_MAX_SGE) {
489 err = -EINVAL;
490 break;
491 }
492 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
493 wqe = (union t3_wr *) (qhp->wq.queue + idx);
494 if (num_wrs)
495 if (wr->sg_list[0].lkey)
496 err = build_rdma_recv(qhp, wqe, wr);
497 else
498 err = build_zero_stag_recv(qhp, wqe, wr);
499 else
500 err = -ENOMEM;
501
502 if (err)
503 break;
504
505 build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
506 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
507 0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
508 PDBG("%s cookie 0x%llx idx 0x%x rq_wptr 0x%x rw_rptr 0x%x "
509 "wqe %p \n", __func__, (unsigned long long) wr->wr_id,
510 idx, qhp->wq.rq_wptr, qhp->wq.rq_rptr, wqe);
511 ++(qhp->wq.rq_wptr);
512 ++(qhp->wq.wptr);
513 wr = wr->next;
514 num_wrs--;
515 }
516 spin_unlock_irqrestore(&qhp->lock, flag);
517 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
518
519 out:
520 if (err)
521 *bad_wr = wr;
522 return err;
523 }
524
525 int iwch_bind_mw(struct ib_qp *qp,
526 struct ib_mw *mw,
527 struct ib_mw_bind *mw_bind)
528 {
529 struct iwch_dev *rhp;
530 struct iwch_mw *mhp;
531 struct iwch_qp *qhp;
532 union t3_wr *wqe;
533 u32 pbl_addr;
534 u8 page_size;
535 u32 num_wrs;
536 unsigned long flag;
537 struct ib_sge sgl;
538 int err=0;
539 enum t3_wr_flags t3_wr_flags;
540 u32 idx;
541 struct t3_swsq *sqp;
542
543 qhp = to_iwch_qp(qp);
544 mhp = to_iwch_mw(mw);
545 rhp = qhp->rhp;
546
547 spin_lock_irqsave(&qhp->lock, flag);
548 if (qhp->attr.state > IWCH_QP_STATE_RTS) {
549 spin_unlock_irqrestore(&qhp->lock, flag);
550 return -EINVAL;
551 }
552 num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
553 qhp->wq.sq_size_log2);
554 if ((num_wrs) <= 0) {
555 spin_unlock_irqrestore(&qhp->lock, flag);
556 return -ENOMEM;
557 }
558 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
559 PDBG("%s: idx 0x%0x, mw 0x%p, mw_bind 0x%p\n", __func__, idx,
560 mw, mw_bind);
561 wqe = (union t3_wr *) (qhp->wq.queue + idx);
562
563 t3_wr_flags = 0;
564 if (mw_bind->send_flags & IB_SEND_SIGNALED)
565 t3_wr_flags = T3_COMPLETION_FLAG;
566
567 sgl.addr = mw_bind->addr;
568 sgl.lkey = mw_bind->mr->lkey;
569 sgl.length = mw_bind->length;
570 wqe->bind.reserved = 0;
571 wqe->bind.type = TPT_VATO;
572
573 /* TBD: check perms */
574 wqe->bind.perms = iwch_ib_to_tpt_bind_access(mw_bind->mw_access_flags);
575 wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey);
576 wqe->bind.mw_stag = cpu_to_be32(mw->rkey);
577 wqe->bind.mw_len = cpu_to_be32(mw_bind->length);
578 wqe->bind.mw_va = cpu_to_be64(mw_bind->addr);
579 err = iwch_sgl2pbl_map(rhp, &sgl, 1, &pbl_addr, &page_size);
580 if (err) {
581 spin_unlock_irqrestore(&qhp->lock, flag);
582 return err;
583 }
584 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
585 sqp = qhp->wq.sq + Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
586 sqp->wr_id = mw_bind->wr_id;
587 sqp->opcode = T3_BIND_MW;
588 sqp->sq_wptr = qhp->wq.sq_wptr;
589 sqp->complete = 0;
590 sqp->signaled = (mw_bind->send_flags & IB_SEND_SIGNALED);
591 wqe->bind.mr_pbl_addr = cpu_to_be32(pbl_addr);
592 wqe->bind.mr_pagesz = page_size;
593 build_fw_riwrh((void *)wqe, T3_WR_BIND, t3_wr_flags,
594 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), 0,
595 sizeof(struct t3_bind_mw_wr) >> 3, T3_SOPEOP);
596 ++(qhp->wq.wptr);
597 ++(qhp->wq.sq_wptr);
598 spin_unlock_irqrestore(&qhp->lock, flag);
599
600 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
601
602 return err;
603 }
604
605 static inline void build_term_codes(struct respQ_msg_t *rsp_msg,
606 u8 *layer_type, u8 *ecode)
607 {
608 int status = TPT_ERR_INTERNAL_ERR;
609 int tagged = 0;
610 int opcode = -1;
611 int rqtype = 0;
612 int send_inv = 0;
613
614 if (rsp_msg) {
615 status = CQE_STATUS(rsp_msg->cqe);
616 opcode = CQE_OPCODE(rsp_msg->cqe);
617 rqtype = RQ_TYPE(rsp_msg->cqe);
618 send_inv = (opcode == T3_SEND_WITH_INV) ||
619 (opcode == T3_SEND_WITH_SE_INV);
620 tagged = (opcode == T3_RDMA_WRITE) ||
621 (rqtype && (opcode == T3_READ_RESP));
622 }
623
624 switch (status) {
625 case TPT_ERR_STAG:
626 if (send_inv) {
627 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
628 *ecode = RDMAP_CANT_INV_STAG;
629 } else {
630 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
631 *ecode = RDMAP_INV_STAG;
632 }
633 break;
634 case TPT_ERR_PDID:
635 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
636 if ((opcode == T3_SEND_WITH_INV) ||
637 (opcode == T3_SEND_WITH_SE_INV))
638 *ecode = RDMAP_CANT_INV_STAG;
639 else
640 *ecode = RDMAP_STAG_NOT_ASSOC;
641 break;
642 case TPT_ERR_QPID:
643 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
644 *ecode = RDMAP_STAG_NOT_ASSOC;
645 break;
646 case TPT_ERR_ACCESS:
647 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
648 *ecode = RDMAP_ACC_VIOL;
649 break;
650 case TPT_ERR_WRAP:
651 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
652 *ecode = RDMAP_TO_WRAP;
653 break;
654 case TPT_ERR_BOUND:
655 if (tagged) {
656 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
657 *ecode = DDPT_BASE_BOUNDS;
658 } else {
659 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
660 *ecode = RDMAP_BASE_BOUNDS;
661 }
662 break;
663 case TPT_ERR_INVALIDATE_SHARED_MR:
664 case TPT_ERR_INVALIDATE_MR_WITH_MW_BOUND:
665 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
666 *ecode = RDMAP_CANT_INV_STAG;
667 break;
668 case TPT_ERR_ECC:
669 case TPT_ERR_ECC_PSTAG:
670 case TPT_ERR_INTERNAL_ERR:
671 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
672 *ecode = 0;
673 break;
674 case TPT_ERR_OUT_OF_RQE:
675 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
676 *ecode = DDPU_INV_MSN_NOBUF;
677 break;
678 case TPT_ERR_PBL_ADDR_BOUND:
679 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
680 *ecode = DDPT_BASE_BOUNDS;
681 break;
682 case TPT_ERR_CRC:
683 *layer_type = LAYER_MPA|DDP_LLP;
684 *ecode = MPA_CRC_ERR;
685 break;
686 case TPT_ERR_MARKER:
687 *layer_type = LAYER_MPA|DDP_LLP;
688 *ecode = MPA_MARKER_ERR;
689 break;
690 case TPT_ERR_PDU_LEN_ERR:
691 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
692 *ecode = DDPU_MSG_TOOBIG;
693 break;
694 case TPT_ERR_DDP_VERSION:
695 if (tagged) {
696 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
697 *ecode = DDPT_INV_VERS;
698 } else {
699 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
700 *ecode = DDPU_INV_VERS;
701 }
702 break;
703 case TPT_ERR_RDMA_VERSION:
704 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
705 *ecode = RDMAP_INV_VERS;
706 break;
707 case TPT_ERR_OPCODE:
708 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
709 *ecode = RDMAP_INV_OPCODE;
710 break;
711 case TPT_ERR_DDP_QUEUE_NUM:
712 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
713 *ecode = DDPU_INV_QN;
714 break;
715 case TPT_ERR_MSN:
716 case TPT_ERR_MSN_GAP:
717 case TPT_ERR_MSN_RANGE:
718 case TPT_ERR_IRD_OVERFLOW:
719 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
720 *ecode = DDPU_INV_MSN_RANGE;
721 break;
722 case TPT_ERR_TBIT:
723 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
724 *ecode = 0;
725 break;
726 case TPT_ERR_MO:
727 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
728 *ecode = DDPU_INV_MO;
729 break;
730 default:
731 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
732 *ecode = 0;
733 break;
734 }
735 }
736
737 int iwch_post_zb_read(struct iwch_qp *qhp)
738 {
739 union t3_wr *wqe;
740 struct sk_buff *skb;
741 u8 flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
742
743 PDBG("%s enter\n", __func__);
744 skb = alloc_skb(40, GFP_KERNEL);
745 if (!skb) {
746 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
747 return -ENOMEM;
748 }
749 wqe = (union t3_wr *)skb_put(skb, sizeof(struct t3_rdma_read_wr));
750 memset(wqe, 0, sizeof(struct t3_rdma_read_wr));
751 wqe->read.rdmaop = T3_READ_REQ;
752 wqe->read.reserved[0] = 0;
753 wqe->read.reserved[1] = 0;
754 wqe->read.rem_stag = cpu_to_be32(1);
755 wqe->read.rem_to = cpu_to_be64(1);
756 wqe->read.local_stag = cpu_to_be32(1);
757 wqe->read.local_len = cpu_to_be32(0);
758 wqe->read.local_to = cpu_to_be64(1);
759 wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_READ));
760 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)|
761 V_FW_RIWR_LEN(flit_cnt));
762 skb->priority = CPL_PRIORITY_DATA;
763 return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
764 }
765
766 /*
767 * This posts a TERMINATE with layer=RDMA, type=catastrophic.
768 */
769 int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
770 {
771 union t3_wr *wqe;
772 struct terminate_message *term;
773 struct sk_buff *skb;
774
775 PDBG("%s %d\n", __func__, __LINE__);
776 skb = alloc_skb(40, GFP_ATOMIC);
777 if (!skb) {
778 printk(KERN_ERR "%s cannot send TERMINATE!\n", __func__);
779 return -ENOMEM;
780 }
781 wqe = (union t3_wr *)skb_put(skb, 40);
782 memset(wqe, 0, 40);
783 wqe->send.rdmaop = T3_TERMINATE;
784
785 /* immediate data length */
786 wqe->send.plen = htonl(4);
787
788 /* immediate data starts here. */
789 term = (struct terminate_message *)wqe->send.sgl;
790 build_term_codes(rsp_msg, &term->layer_etype, &term->ecode);
791 wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_SEND) |
792 V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
793 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
794 skb->priority = CPL_PRIORITY_DATA;
795 return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
796 }
797
798 /*
799 * Assumes qhp lock is held.
800 */
801 static void __flush_qp(struct iwch_qp *qhp, unsigned long *flag)
802 {
803 struct iwch_cq *rchp, *schp;
804 int count;
805 int flushed;
806
807 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
808 schp = get_chp(qhp->rhp, qhp->attr.scq);
809
810 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
811 /* take a ref on the qhp since we must release the lock */
812 atomic_inc(&qhp->refcnt);
813 spin_unlock_irqrestore(&qhp->lock, *flag);
814
815 /* locking heirarchy: cq lock first, then qp lock. */
816 spin_lock_irqsave(&rchp->lock, *flag);
817 spin_lock(&qhp->lock);
818 cxio_flush_hw_cq(&rchp->cq);
819 cxio_count_rcqes(&rchp->cq, &qhp->wq, &count);
820 flushed = cxio_flush_rq(&qhp->wq, &rchp->cq, count);
821 spin_unlock(&qhp->lock);
822 spin_unlock_irqrestore(&rchp->lock, *flag);
823 if (flushed)
824 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
825
826 /* locking heirarchy: cq lock first, then qp lock. */
827 spin_lock_irqsave(&schp->lock, *flag);
828 spin_lock(&qhp->lock);
829 cxio_flush_hw_cq(&schp->cq);
830 cxio_count_scqes(&schp->cq, &qhp->wq, &count);
831 flushed = cxio_flush_sq(&qhp->wq, &schp->cq, count);
832 spin_unlock(&qhp->lock);
833 spin_unlock_irqrestore(&schp->lock, *flag);
834 if (flushed)
835 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
836
837 /* deref */
838 if (atomic_dec_and_test(&qhp->refcnt))
839 wake_up(&qhp->wait);
840
841 spin_lock_irqsave(&qhp->lock, *flag);
842 }
843
844 static void flush_qp(struct iwch_qp *qhp, unsigned long *flag)
845 {
846 if (qhp->ibqp.uobject)
847 cxio_set_wq_in_error(&qhp->wq);
848 else
849 __flush_qp(qhp, flag);
850 }
851
852
853 /*
854 * Return count of RECV WRs posted
855 */
856 u16 iwch_rqes_posted(struct iwch_qp *qhp)
857 {
858 union t3_wr *wqe = qhp->wq.queue;
859 u16 count = 0;
860 while ((count+1) != 0 && fw_riwrh_opcode((struct fw_riwrh *)wqe) == T3_WR_RCV) {
861 count++;
862 wqe++;
863 }
864 PDBG("%s qhp %p count %u\n", __func__, qhp, count);
865 return count;
866 }
867
868 static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
869 enum iwch_qp_attr_mask mask,
870 struct iwch_qp_attributes *attrs)
871 {
872 struct t3_rdma_init_attr init_attr;
873 int ret;
874
875 init_attr.tid = qhp->ep->hwtid;
876 init_attr.qpid = qhp->wq.qpid;
877 init_attr.pdid = qhp->attr.pd;
878 init_attr.scqid = qhp->attr.scq;
879 init_attr.rcqid = qhp->attr.rcq;
880 init_attr.rq_addr = qhp->wq.rq_addr;
881 init_attr.rq_size = 1 << qhp->wq.rq_size_log2;
882 init_attr.mpaattrs = uP_RI_MPA_IETF_ENABLE |
883 qhp->attr.mpa_attr.recv_marker_enabled |
884 (qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
885 (qhp->attr.mpa_attr.crc_enabled << 2);
886
887 init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE |
888 uP_RI_QP_RDMA_WRITE_ENABLE |
889 uP_RI_QP_BIND_ENABLE;
890 if (!qhp->ibqp.uobject)
891 init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE |
892 uP_RI_QP_FAST_REGISTER_ENABLE;
893
894 init_attr.tcp_emss = qhp->ep->emss;
895 init_attr.ord = qhp->attr.max_ord;
896 init_attr.ird = qhp->attr.max_ird;
897 init_attr.qp_dma_addr = qhp->wq.dma_addr;
898 init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
899 init_attr.rqe_count = iwch_rqes_posted(qhp);
900 init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
901 init_attr.chan = qhp->ep->l2t->smt_idx;
902 if (peer2peer) {
903 init_attr.rtr_type = RTR_READ;
904 if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
905 init_attr.ord = 1;
906 if (init_attr.ird == 0 && !qhp->attr.mpa_attr.initiator)
907 init_attr.ird = 1;
908 } else
909 init_attr.rtr_type = 0;
910 init_attr.irs = qhp->ep->rcv_seq;
911 PDBG("%s init_attr.rq_addr 0x%x init_attr.rq_size = %d "
912 "flags 0x%x qpcaps 0x%x\n", __func__,
913 init_attr.rq_addr, init_attr.rq_size,
914 init_attr.flags, init_attr.qpcaps);
915 ret = cxio_rdma_init(&rhp->rdev, &init_attr);
916 PDBG("%s ret %d\n", __func__, ret);
917 return ret;
918 }
919
920 int iwch_modify_qp(struct iwch_dev *rhp, struct iwch_qp *qhp,
921 enum iwch_qp_attr_mask mask,
922 struct iwch_qp_attributes *attrs,
923 int internal)
924 {
925 int ret = 0;
926 struct iwch_qp_attributes newattr = qhp->attr;
927 unsigned long flag;
928 int disconnect = 0;
929 int terminate = 0;
930 int abort = 0;
931 int free = 0;
932 struct iwch_ep *ep = NULL;
933
934 PDBG("%s qhp %p qpid 0x%x ep %p state %d -> %d\n", __func__,
935 qhp, qhp->wq.qpid, qhp->ep, qhp->attr.state,
936 (mask & IWCH_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
937
938 spin_lock_irqsave(&qhp->lock, flag);
939
940 /* Process attr changes if in IDLE */
941 if (mask & IWCH_QP_ATTR_VALID_MODIFY) {
942 if (qhp->attr.state != IWCH_QP_STATE_IDLE) {
943 ret = -EIO;
944 goto out;
945 }
946 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_READ)
947 newattr.enable_rdma_read = attrs->enable_rdma_read;
948 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_WRITE)
949 newattr.enable_rdma_write = attrs->enable_rdma_write;
950 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_BIND)
951 newattr.enable_bind = attrs->enable_bind;
952 if (mask & IWCH_QP_ATTR_MAX_ORD) {
953 if (attrs->max_ord >
954 rhp->attr.max_rdma_read_qp_depth) {
955 ret = -EINVAL;
956 goto out;
957 }
958 newattr.max_ord = attrs->max_ord;
959 }
960 if (mask & IWCH_QP_ATTR_MAX_IRD) {
961 if (attrs->max_ird >
962 rhp->attr.max_rdma_reads_per_qp) {
963 ret = -EINVAL;
964 goto out;
965 }
966 newattr.max_ird = attrs->max_ird;
967 }
968 qhp->attr = newattr;
969 }
970
971 if (!(mask & IWCH_QP_ATTR_NEXT_STATE))
972 goto out;
973 if (qhp->attr.state == attrs->next_state)
974 goto out;
975
976 switch (qhp->attr.state) {
977 case IWCH_QP_STATE_IDLE:
978 switch (attrs->next_state) {
979 case IWCH_QP_STATE_RTS:
980 if (!(mask & IWCH_QP_ATTR_LLP_STREAM_HANDLE)) {
981 ret = -EINVAL;
982 goto out;
983 }
984 if (!(mask & IWCH_QP_ATTR_MPA_ATTR)) {
985 ret = -EINVAL;
986 goto out;
987 }
988 qhp->attr.mpa_attr = attrs->mpa_attr;
989 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
990 qhp->ep = qhp->attr.llp_stream_handle;
991 qhp->attr.state = IWCH_QP_STATE_RTS;
992
993 /*
994 * Ref the endpoint here and deref when we
995 * disassociate the endpoint from the QP. This
996 * happens in CLOSING->IDLE transition or *->ERROR
997 * transition.
998 */
999 get_ep(&qhp->ep->com);
1000 spin_unlock_irqrestore(&qhp->lock, flag);
1001 ret = rdma_init(rhp, qhp, mask, attrs);
1002 spin_lock_irqsave(&qhp->lock, flag);
1003 if (ret)
1004 goto err;
1005 break;
1006 case IWCH_QP_STATE_ERROR:
1007 qhp->attr.state = IWCH_QP_STATE_ERROR;
1008 flush_qp(qhp, &flag);
1009 break;
1010 default:
1011 ret = -EINVAL;
1012 goto out;
1013 }
1014 break;
1015 case IWCH_QP_STATE_RTS:
1016 switch (attrs->next_state) {
1017 case IWCH_QP_STATE_CLOSING:
1018 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1019 qhp->attr.state = IWCH_QP_STATE_CLOSING;
1020 if (!internal) {
1021 abort=0;
1022 disconnect = 1;
1023 ep = qhp->ep;
1024 get_ep(&ep->com);
1025 }
1026 break;
1027 case IWCH_QP_STATE_TERMINATE:
1028 qhp->attr.state = IWCH_QP_STATE_TERMINATE;
1029 if (qhp->ibqp.uobject)
1030 cxio_set_wq_in_error(&qhp->wq);
1031 if (!internal)
1032 terminate = 1;
1033 break;
1034 case IWCH_QP_STATE_ERROR:
1035 qhp->attr.state = IWCH_QP_STATE_ERROR;
1036 if (!internal) {
1037 abort=1;
1038 disconnect = 1;
1039 ep = qhp->ep;
1040 get_ep(&ep->com);
1041 }
1042 goto err;
1043 break;
1044 default:
1045 ret = -EINVAL;
1046 goto out;
1047 }
1048 break;
1049 case IWCH_QP_STATE_CLOSING:
1050 if (!internal) {
1051 ret = -EINVAL;
1052 goto out;
1053 }
1054 switch (attrs->next_state) {
1055 case IWCH_QP_STATE_IDLE:
1056 flush_qp(qhp, &flag);
1057 qhp->attr.state = IWCH_QP_STATE_IDLE;
1058 qhp->attr.llp_stream_handle = NULL;
1059 put_ep(&qhp->ep->com);
1060 qhp->ep = NULL;
1061 wake_up(&qhp->wait);
1062 break;
1063 case IWCH_QP_STATE_ERROR:
1064 goto err;
1065 default:
1066 ret = -EINVAL;
1067 goto err;
1068 }
1069 break;
1070 case IWCH_QP_STATE_ERROR:
1071 if (attrs->next_state != IWCH_QP_STATE_IDLE) {
1072 ret = -EINVAL;
1073 goto out;
1074 }
1075
1076 if (!Q_EMPTY(qhp->wq.sq_rptr, qhp->wq.sq_wptr) ||
1077 !Q_EMPTY(qhp->wq.rq_rptr, qhp->wq.rq_wptr)) {
1078 ret = -EINVAL;
1079 goto out;
1080 }
1081 qhp->attr.state = IWCH_QP_STATE_IDLE;
1082 break;
1083 case IWCH_QP_STATE_TERMINATE:
1084 if (!internal) {
1085 ret = -EINVAL;
1086 goto out;
1087 }
1088 goto err;
1089 break;
1090 default:
1091 printk(KERN_ERR "%s in a bad state %d\n",
1092 __func__, qhp->attr.state);
1093 ret = -EINVAL;
1094 goto err;
1095 break;
1096 }
1097 goto out;
1098 err:
1099 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1100 qhp->wq.qpid);
1101
1102 /* disassociate the LLP connection */
1103 qhp->attr.llp_stream_handle = NULL;
1104 ep = qhp->ep;
1105 qhp->ep = NULL;
1106 qhp->attr.state = IWCH_QP_STATE_ERROR;
1107 free=1;
1108 wake_up(&qhp->wait);
1109 BUG_ON(!ep);
1110 flush_qp(qhp, &flag);
1111 out:
1112 spin_unlock_irqrestore(&qhp->lock, flag);
1113
1114 if (terminate)
1115 iwch_post_terminate(qhp, NULL);
1116
1117 /*
1118 * If disconnect is 1, then we need to initiate a disconnect
1119 * on the EP. This can be a normal close (RTS->CLOSING) or
1120 * an abnormal close (RTS/CLOSING->ERROR).
1121 */
1122 if (disconnect) {
1123 iwch_ep_disconnect(ep, abort, GFP_KERNEL);
1124 put_ep(&ep->com);
1125 }
1126
1127 /*
1128 * If free is 1, then we've disassociated the EP from the QP
1129 * and we need to dereference the EP.
1130 */
1131 if (free)
1132 put_ep(&ep->com);
1133
1134 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1135 return ret;
1136 }
1137
1138 static int quiesce_qp(struct iwch_qp *qhp)
1139 {
1140 spin_lock_irq(&qhp->lock);
1141 iwch_quiesce_tid(qhp->ep);
1142 qhp->flags |= QP_QUIESCED;
1143 spin_unlock_irq(&qhp->lock);
1144 return 0;
1145 }
1146
1147 static int resume_qp(struct iwch_qp *qhp)
1148 {
1149 spin_lock_irq(&qhp->lock);
1150 iwch_resume_tid(qhp->ep);
1151 qhp->flags &= ~QP_QUIESCED;
1152 spin_unlock_irq(&qhp->lock);
1153 return 0;
1154 }
1155
1156 int iwch_quiesce_qps(struct iwch_cq *chp)
1157 {
1158 int i;
1159 struct iwch_qp *qhp;
1160
1161 for (i=0; i < T3_MAX_NUM_QP; i++) {
1162 qhp = get_qhp(chp->rhp, i);
1163 if (!qhp)
1164 continue;
1165 if ((qhp->attr.rcq == chp->cq.cqid) && !qp_quiesced(qhp)) {
1166 quiesce_qp(qhp);
1167 continue;
1168 }
1169 if ((qhp->attr.scq == chp->cq.cqid) && !qp_quiesced(qhp))
1170 quiesce_qp(qhp);
1171 }
1172 return 0;
1173 }
1174
1175 int iwch_resume_qps(struct iwch_cq *chp)
1176 {
1177 int i;
1178 struct iwch_qp *qhp;
1179
1180 for (i=0; i < T3_MAX_NUM_QP; i++) {
1181 qhp = get_qhp(chp->rhp, i);
1182 if (!qhp)
1183 continue;
1184 if ((qhp->attr.rcq == chp->cq.cqid) && qp_quiesced(qhp)) {
1185 resume_qp(qhp);
1186 continue;
1187 }
1188 if ((qhp->attr.scq == chp->cq.cqid) && qp_quiesced(qhp))
1189 resume_qp(qhp);
1190 }
1191 return 0;
1192 }
kernel source for telekom puls (alcatel/mediatek)