drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

   1 /*
   2 * Copyright (C) 2012 Invensense, Inc.
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-mux.h>
  15 #include <linux/kfifo.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/buffer.h>
  19 #include <linux/regmap.h>
  20 #include <linux/iio/sysfs.h>
  21 #include <linux/iio/kfifo_buf.h>
  22 #include <linux/iio/trigger.h>
  23 #include <linux/iio/triggered_buffer.h>
  24 #include <linux/iio/trigger_consumer.h>
  25 #include <linux/platform_data/invensense_mpu6050.h>
  26
  27 /**
  28  *  struct inv_mpu6050_reg_map - Notable registers.
  29  *  @sample_rate_div:   Divider applied to gyro output rate.
  30  *  @lpf:               Configures internal low pass filter.
  31  *  @accel_lpf:         Configures accelerometer low pass filter.
  32  *  @user_ctrl:         Enables/resets the FIFO.
  33  *  @fifo_en:           Determines which data will appear in FIFO.
  34  *  @gyro_config:       gyro config register.
  35  *  @accl_config:       accel config register
  36  *  @fifo_count_h:      Upper byte of FIFO count.
  37  *  @fifo_r_w:          FIFO register.
  38  *  @raw_gyro:          Address of first gyro register.
  39  *  @raw_accl:          Address of first accel register.
  40  *  @temperature:       temperature register
  41  *  @int_enable:        Interrupt enable register.
  42  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  43  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  44  *  @int_pin_cfg;       Controls interrupt pin configuration.
  45  *  @accl_offset:       Controls the accelerometer calibration offset.
  46  *  @gyro_offset:       Controls the gyroscope calibration offset.
  47  */
  48 struct inv_mpu6050_reg_map {
  49         u8 sample_rate_div;
  50         u8 lpf;
  51         u8 accel_lpf;
  52         u8 user_ctrl;
  53         u8 fifo_en;
  54         u8 gyro_config;
  55         u8 accl_config;
  56         u8 fifo_count_h;
  57         u8 fifo_r_w;
  58         u8 raw_gyro;
  59         u8 raw_accl;
  60         u8 temperature;
  61         u8 int_enable;
  62         u8 pwr_mgmt_1;
  63         u8 pwr_mgmt_2;
  64         u8 int_pin_cfg;
  65         u8 accl_offset;
  66         u8 gyro_offset;
  67 };
  68
  69 /*device enum */
  70 enum inv_devices {
  71         INV_MPU6050,
  72         INV_MPU6500,
  73         INV_MPU6000,
  74         INV_MPU9150,
  75         INV_MPU9250,
  76         INV_ICM20608,
  77         INV_NUM_PARTS
  78 };
  79
  80 /**
  81  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  82  *  @fsr:               Full scale range.
  83  *  @lpf:               Digital low pass filter frequency.
  84  *  @accl_fs:           accel full scale range.
  85  *  @enable:            master enable state.
  86  *  @accl_fifo_enable:  enable accel data output
  87  *  @gyro_fifo_enable:  enable gyro data output
  88  *  @fifo_rate:         FIFO update rate.
  89  */
  90 struct inv_mpu6050_chip_config {
  91         unsigned int fsr:2;
  92         unsigned int lpf:3;
  93         unsigned int accl_fs:2;
  94         unsigned int enable:1;
  95         unsigned int accl_fifo_enable:1;
  96         unsigned int gyro_fifo_enable:1;
  97         u16 fifo_rate;
  98 };
  99
 100 /**
 101  *  struct inv_mpu6050_hw - Other important hardware information.
 102  *  @whoami:    Self identification byte from WHO_AM_I register
 103  *  @name:      name of the chip.
 104  *  @reg:   register map of the chip.
 105  *  @config:    configuration of the chip.
 106  */
 107 struct inv_mpu6050_hw {
 108         u8 whoami;
 109         u8 *name;
 110         const struct inv_mpu6050_reg_map *reg;
 111         const struct inv_mpu6050_chip_config *config;
 112 };
 113
 114 /*
 115  *  struct inv_mpu6050_state - Driver state variables.
 116  *  @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
 117  *  @trig:              IIO trigger.
 118  *  @chip_config:       Cached attribute information.
 119  *  @reg:               Map of important registers.
 120  *  @hw:                Other hardware-specific information.
 121  *  @chip_type:         chip type.
 122  *  @time_stamp_lock:   spin lock to time stamp.
 123  *  @plat_data:         platform data (deprecated in favor of @orientation).
 124  *  @orientation:       sensor chip orientation relative to main hardware.
 125  *  @timestamps:        kfifo queue to store time stamp.
 126  *  @map                regmap pointer.
 127  *  @irq                interrupt number.
 128  */
 129 struct inv_mpu6050_state {
 130 #define TIMESTAMP_FIFO_SIZE 16
 131         struct iio_trigger  *trig;
 132         struct inv_mpu6050_chip_config chip_config;
 133         const struct inv_mpu6050_reg_map *reg;
 134         const struct inv_mpu6050_hw *hw;
 135         enum   inv_devices chip_type;
 136         spinlock_t time_stamp_lock;
 137         struct i2c_mux_core *muxc;
 138         struct i2c_client *mux_client;
 139         unsigned int powerup_count;
 140         struct inv_mpu6050_platform_data plat_data;
 141         struct iio_mount_matrix orientation;
 142         DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
 143         struct regmap *map;
 144         int irq;
 145 };
 146
 147 /*register and associated bit definition*/
 148 #define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 149 #define INV_MPU6050_REG_GYRO_OFFSET         0x13
 150
 151 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 152 #define INV_MPU6050_REG_CONFIG              0x1A
 153 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 154 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 155
 156 #define INV_MPU6050_REG_FIFO_EN             0x23
 157 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 158 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 159
 160 #define INV_MPU6050_REG_INT_ENABLE          0x38
 161 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 162 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 163
 164 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 165 #define INV_MPU6050_REG_TEMPERATURE         0x41
 166 #define INV_MPU6050_REG_RAW_GYRO            0x43
 167
 168 #define INV_MPU6050_REG_USER_CTRL           0x6A
 169 #define INV_MPU6050_BIT_FIFO_RST            0x04
 170 #define INV_MPU6050_BIT_DMP_RST             0x08
 171 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 172 #define INV_MPU6050_BIT_FIFO_EN             0x40
 173 #define INV_MPU6050_BIT_DMP_EN              0x80
 174 #define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 175
 176 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 177 #define INV_MPU6050_BIT_H_RESET             0x80
 178 #define INV_MPU6050_BIT_SLEEP               0x40
 179 #define INV_MPU6050_BIT_CLK_MASK            0x7
 180
 181 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 182 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 183 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 184
 185 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 186 #define INV_MPU6050_REG_FIFO_R_W            0x74
 187
 188 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 189 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 190 #define INV_MPU6050_FIFO_THRESHOLD           500
 191
 192 /* mpu6500 registers */
 193 #define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 194 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 195
 196 /* delay time in milliseconds */
 197 #define INV_MPU6050_POWER_UP_TIME            100
 198 #define INV_MPU6050_TEMP_UP_TIME             100
 199 #define INV_MPU6050_SENSOR_UP_TIME           30
 200
 201 /* delay time in microseconds */
 202 #define INV_MPU6050_REG_UP_TIME_MIN          5000
 203 #define INV_MPU6050_REG_UP_TIME_MAX          10000
 204
 205 #define INV_MPU6050_TEMP_OFFSET              12421
 206 #define INV_MPU6050_TEMP_SCALE               2941
 207 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 208 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 209 #define INV_MPU6050_THREE_AXIS               3
 210 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 211 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 212
 213 /* 6 + 6 round up and plus 8 */
 214 #define INV_MPU6050_OUTPUT_DATA_SIZE         24
 215
 216 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 217 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 218 #define INV_MPU6050_INT_PIN_CFG         0
 219
 220 /* init parameters */
 221 #define INV_MPU6050_INIT_FIFO_RATE           50
 222 #define INV_MPU6050_TIME_STAMP_TOR           5
 223 #define INV_MPU6050_MAX_FIFO_RATE            1000
 224 #define INV_MPU6050_MIN_FIFO_RATE            4
 225 #define INV_MPU6050_ONE_K_HZ                 1000
 226
 227 #define INV_MPU6050_REG_WHOAMI                  117
 228
 229 #define INV_MPU6000_WHOAMI_VALUE                0x68
 230 #define INV_MPU6050_WHOAMI_VALUE                0x68
 231 #define INV_MPU6500_WHOAMI_VALUE                0x70
 232 #define INV_MPU9150_WHOAMI_VALUE                0x68
 233 #define INV_MPU9250_WHOAMI_VALUE                0x71
 234 #define INV_ICM20608_WHOAMI_VALUE               0xAF
 235
 236 /* scan element definition */
 237 enum inv_mpu6050_scan {
 238         INV_MPU6050_SCAN_ACCL_X,
 239         INV_MPU6050_SCAN_ACCL_Y,
 240         INV_MPU6050_SCAN_ACCL_Z,
 241         INV_MPU6050_SCAN_GYRO_X,
 242         INV_MPU6050_SCAN_GYRO_Y,
 243         INV_MPU6050_SCAN_GYRO_Z,
 244         INV_MPU6050_SCAN_TIMESTAMP,
 245 };
 246
 247 enum inv_mpu6050_filter_e {
 248         INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 249         INV_MPU6050_FILTER_188HZ,
 250         INV_MPU6050_FILTER_98HZ,
 251         INV_MPU6050_FILTER_42HZ,
 252         INV_MPU6050_FILTER_20HZ,
 253         INV_MPU6050_FILTER_10HZ,
 254         INV_MPU6050_FILTER_5HZ,
 255         INV_MPU6050_FILTER_2100HZ_NOLPF,
 256         NUM_MPU6050_FILTER
 257 };
 258
 259 /* IIO attribute address */
 260 enum INV_MPU6050_IIO_ATTR_ADDR {
 261         ATTR_GYRO_MATRIX,
 262         ATTR_ACCL_MATRIX,
 263 };
 264
 265 enum inv_mpu6050_accl_fs_e {
 266         INV_MPU6050_FS_02G = 0,
 267         INV_MPU6050_FS_04G,
 268         INV_MPU6050_FS_08G,
 269         INV_MPU6050_FS_16G,
 270         NUM_ACCL_FSR
 271 };
 272
 273 enum inv_mpu6050_fsr_e {
 274         INV_MPU6050_FSR_250DPS = 0,
 275         INV_MPU6050_FSR_500DPS,
 276         INV_MPU6050_FSR_1000DPS,
 277         INV_MPU6050_FSR_2000DPS,
 278         NUM_MPU6050_FSR
 279 };
 280
 281 enum inv_mpu6050_clock_sel_e {
 282         INV_CLK_INTERNAL = 0,
 283         INV_CLK_PLL,
 284         NUM_CLK
 285 };
 286
 287 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
 288 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 289 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
 290 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
 291 int inv_reset_fifo(struct iio_dev *indio_dev);
 292 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 293 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 294 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 295 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 296 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 297 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 298                 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 299 int inv_mpu_core_remove(struct device *dev);
 300 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 301 extern const struct dev_pm_ops inv_mpu_pmops;