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[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / iio / adc / mxs-lradc-adc.c
1 /*
2 * Freescale MXS LRADC ADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
6 *
7 * Authors:
8 * Marek Vasut <marex@denx.de>
9 * Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22 #include <linux/completion.h>
23 #include <linux/device.h>
24 #include <linux/err.h>
25 #include <linux/interrupt.h>
26 #include <linux/mfd/core.h>
27 #include <linux/mfd/mxs-lradc.h>
28 #include <linux/module.h>
29 #include <linux/of_irq.h>
30 #include <linux/platform_device.h>
31 #include <linux/sysfs.h>
32
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/iio.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
38 #include <linux/iio/sysfs.h>
39
40 /*
41 * Make this runtime configurable if necessary. Currently, if the buffered mode
42 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
43 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
44 * seconds. The result is that the samples arrive every 500mS.
45 */
46 #define LRADC_DELAY_TIMER_PER 200
47 #define LRADC_DELAY_TIMER_LOOP 5
48
49 #define VREF_MV_BASE 1850
50
51 const char *mx23_lradc_adc_irq_names[] = {
52 "mxs-lradc-channel0",
53 "mxs-lradc-channel1",
54 "mxs-lradc-channel2",
55 "mxs-lradc-channel3",
56 "mxs-lradc-channel4",
57 "mxs-lradc-channel5",
58 };
59
60 const char *mx28_lradc_adc_irq_names[] = {
61 "mxs-lradc-thresh0",
62 "mxs-lradc-thresh1",
63 "mxs-lradc-channel0",
64 "mxs-lradc-channel1",
65 "mxs-lradc-channel2",
66 "mxs-lradc-channel3",
67 "mxs-lradc-channel4",
68 "mxs-lradc-channel5",
69 "mxs-lradc-button0",
70 "mxs-lradc-button1",
71 };
72
73 static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
74 [IMX23_LRADC] = {
75 VREF_MV_BASE, /* CH0 */
76 VREF_MV_BASE, /* CH1 */
77 VREF_MV_BASE, /* CH2 */
78 VREF_MV_BASE, /* CH3 */
79 VREF_MV_BASE, /* CH4 */
80 VREF_MV_BASE, /* CH5 */
81 VREF_MV_BASE * 2, /* CH6 VDDIO */
82 VREF_MV_BASE * 4, /* CH7 VBATT */
83 VREF_MV_BASE, /* CH8 Temp sense 0 */
84 VREF_MV_BASE, /* CH9 Temp sense 1 */
85 VREF_MV_BASE, /* CH10 */
86 VREF_MV_BASE, /* CH11 */
87 VREF_MV_BASE, /* CH12 USB_DP */
88 VREF_MV_BASE, /* CH13 USB_DN */
89 VREF_MV_BASE, /* CH14 VBG */
90 VREF_MV_BASE * 4, /* CH15 VDD5V */
91 },
92 [IMX28_LRADC] = {
93 VREF_MV_BASE, /* CH0 */
94 VREF_MV_BASE, /* CH1 */
95 VREF_MV_BASE, /* CH2 */
96 VREF_MV_BASE, /* CH3 */
97 VREF_MV_BASE, /* CH4 */
98 VREF_MV_BASE, /* CH5 */
99 VREF_MV_BASE, /* CH6 */
100 VREF_MV_BASE * 4, /* CH7 VBATT */
101 VREF_MV_BASE, /* CH8 Temp sense 0 */
102 VREF_MV_BASE, /* CH9 Temp sense 1 */
103 VREF_MV_BASE * 2, /* CH10 VDDIO */
104 VREF_MV_BASE, /* CH11 VTH */
105 VREF_MV_BASE * 2, /* CH12 VDDA */
106 VREF_MV_BASE, /* CH13 VDDD */
107 VREF_MV_BASE, /* CH14 VBG */
108 VREF_MV_BASE * 4, /* CH15 VDD5V */
109 },
110 };
111
112 enum mxs_lradc_divbytwo {
113 MXS_LRADC_DIV_DISABLED = 0,
114 MXS_LRADC_DIV_ENABLED,
115 };
116
117 struct mxs_lradc_scale {
118 unsigned int integer;
119 unsigned int nano;
120 };
121
122 struct mxs_lradc_adc {
123 struct mxs_lradc *lradc;
124 struct device *dev;
125
126 void __iomem *base;
127 u32 buffer[10];
128 struct iio_trigger *trig;
129 struct completion completion;
130 spinlock_t lock;
131
132 const u32 *vref_mv;
133 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
134 unsigned long is_divided;
135 };
136
137
138 /* Raw I/O operations */
139 static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
140 int *val)
141 {
142 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
143 struct mxs_lradc *lradc = adc->lradc;
144 int ret;
145
146 /*
147 * See if there is no buffered operation in progress. If there is simply
148 * bail out. This can be improved to support both buffered and raw IO at
149 * the same time, yet the code becomes horribly complicated. Therefore I
150 * applied KISS principle here.
151 */
152 ret = iio_device_claim_direct_mode(iio_dev);
153 if (ret)
154 return ret;
155
156 reinit_completion(&adc->completion);
157
158 /*
159 * No buffered operation in progress, map the channel and trigger it.
160 * Virtual channel 0 is always used here as the others are always not
161 * used if doing raw sampling.
162 */
163 if (lradc->soc == IMX28_LRADC)
164 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
165 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
166 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
167
168 /* Enable / disable the divider per requirement */
169 if (test_bit(chan, &adc->is_divided))
170 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
171 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
172 else
173 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
174 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
175
176 /* Clean the slot's previous content, then set new one. */
177 writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
178 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
179 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
180
181 writel(0, adc->base + LRADC_CH(0));
182
183 /* Enable the IRQ and start sampling the channel. */
184 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
185 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
186 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
187
188 /* Wait for completion on the channel, 1 second max. */
189 ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
190 if (!ret)
191 ret = -ETIMEDOUT;
192 if (ret < 0)
193 goto err;
194
195 /* Read the data. */
196 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
197 ret = IIO_VAL_INT;
198
199 err:
200 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
201 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
202
203 iio_device_release_direct_mode(iio_dev);
204
205 return ret;
206 }
207
208 static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
209 {
210 int ret, min, max;
211
212 ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
213 if (ret != IIO_VAL_INT)
214 return ret;
215
216 ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
217 if (ret != IIO_VAL_INT)
218 return ret;
219
220 *val = max - min;
221
222 return IIO_VAL_INT;
223 }
224
225 static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
226 const struct iio_chan_spec *chan,
227 int *val, int *val2, long m)
228 {
229 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
230
231 switch (m) {
232 case IIO_CHAN_INFO_RAW:
233 if (chan->type == IIO_TEMP)
234 return mxs_lradc_adc_read_temp(iio_dev, val);
235
236 return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
237
238 case IIO_CHAN_INFO_SCALE:
239 if (chan->type == IIO_TEMP) {
240 /*
241 * From the datasheet, we have to multiply by 1.012 and
242 * divide by 4
243 */
244 *val = 0;
245 *val2 = 253000;
246 return IIO_VAL_INT_PLUS_MICRO;
247 }
248
249 *val = adc->vref_mv[chan->channel];
250 *val2 = chan->scan_type.realbits -
251 test_bit(chan->channel, &adc->is_divided);
252 return IIO_VAL_FRACTIONAL_LOG2;
253
254 case IIO_CHAN_INFO_OFFSET:
255 if (chan->type == IIO_TEMP) {
256 /*
257 * The calculated value from the ADC is in Kelvin, we
258 * want Celsius for hwmon so the offset is -273.15
259 * The offset is applied before scaling so it is
260 * actually -213.15 * 4 / 1.012 = -1079.644268
261 */
262 *val = -1079;
263 *val2 = 644268;
264
265 return IIO_VAL_INT_PLUS_MICRO;
266 }
267
268 return -EINVAL;
269
270 default:
271 break;
272 }
273
274 return -EINVAL;
275 }
276
277 static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
278 const struct iio_chan_spec *chan,
279 int val, int val2, long m)
280 {
281 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
282 struct mxs_lradc_scale *scale_avail =
283 adc->scale_avail[chan->channel];
284 int ret;
285
286 ret = iio_device_claim_direct_mode(iio_dev);
287 if (ret)
288 return ret;
289
290 switch (m) {
291 case IIO_CHAN_INFO_SCALE:
292 ret = -EINVAL;
293 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
294 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
295 /* divider by two disabled */
296 clear_bit(chan->channel, &adc->is_divided);
297 ret = 0;
298 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
299 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
300 /* divider by two enabled */
301 set_bit(chan->channel, &adc->is_divided);
302 ret = 0;
303 }
304
305 break;
306 default:
307 ret = -EINVAL;
308 break;
309 }
310
311 iio_device_release_direct_mode(iio_dev);
312
313 return ret;
314 }
315
316 static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
317 const struct iio_chan_spec *chan,
318 long m)
319 {
320 return IIO_VAL_INT_PLUS_NANO;
321 }
322
323 static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
324 struct device_attribute *attr,
325 char *buf)
326 {
327 struct iio_dev *iio = dev_to_iio_dev(dev);
328 struct mxs_lradc_adc *adc = iio_priv(iio);
329 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
330 int i, ch, len = 0;
331
332 ch = iio_attr->address;
333 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
334 len += sprintf(buf + len, "%u.%09u ",
335 adc->scale_avail[ch][i].integer,
336 adc->scale_avail[ch][i].nano);
337
338 len += sprintf(buf + len, "\n");
339
340 return len;
341 }
342
343 #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
344 IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
345 mxs_lradc_adc_show_scale_avail, NULL, ch)
346
347 SHOW_SCALE_AVAILABLE_ATTR(0);
348 SHOW_SCALE_AVAILABLE_ATTR(1);
349 SHOW_SCALE_AVAILABLE_ATTR(2);
350 SHOW_SCALE_AVAILABLE_ATTR(3);
351 SHOW_SCALE_AVAILABLE_ATTR(4);
352 SHOW_SCALE_AVAILABLE_ATTR(5);
353 SHOW_SCALE_AVAILABLE_ATTR(6);
354 SHOW_SCALE_AVAILABLE_ATTR(7);
355 SHOW_SCALE_AVAILABLE_ATTR(10);
356 SHOW_SCALE_AVAILABLE_ATTR(11);
357 SHOW_SCALE_AVAILABLE_ATTR(12);
358 SHOW_SCALE_AVAILABLE_ATTR(13);
359 SHOW_SCALE_AVAILABLE_ATTR(14);
360 SHOW_SCALE_AVAILABLE_ATTR(15);
361
362 static struct attribute *mxs_lradc_adc_attributes[] = {
363 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
364 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
365 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
366 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
367 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
368 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
369 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
370 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
371 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
372 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
373 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
374 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
375 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
376 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
377 NULL
378 };
379
380 static const struct attribute_group mxs_lradc_adc_attribute_group = {
381 .attrs = mxs_lradc_adc_attributes,
382 };
383
384 static const struct iio_info mxs_lradc_adc_iio_info = {
385 .driver_module = THIS_MODULE,
386 .read_raw = mxs_lradc_adc_read_raw,
387 .write_raw = mxs_lradc_adc_write_raw,
388 .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
389 .attrs = &mxs_lradc_adc_attribute_group,
390 };
391
392 /* IRQ Handling */
393 static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
394 {
395 struct iio_dev *iio = data;
396 struct mxs_lradc_adc *adc = iio_priv(iio);
397 struct mxs_lradc *lradc = adc->lradc;
398 unsigned long reg = readl(adc->base + LRADC_CTRL1);
399 unsigned long flags;
400
401 if (!(reg & mxs_lradc_irq_mask(lradc)))
402 return IRQ_NONE;
403
404 if (iio_buffer_enabled(iio)) {
405 if (reg & lradc->buffer_vchans) {
406 spin_lock_irqsave(&adc->lock, flags);
407 iio_trigger_poll(iio->trig);
408 spin_unlock_irqrestore(&adc->lock, flags);
409 }
410 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
411 complete(&adc->completion);
412 }
413
414 writel(reg & mxs_lradc_irq_mask(lradc),
415 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
416
417 return IRQ_HANDLED;
418 }
419
420
421 /* Trigger handling */
422 static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
423 {
424 struct iio_poll_func *pf = p;
425 struct iio_dev *iio = pf->indio_dev;
426 struct mxs_lradc_adc *adc = iio_priv(iio);
427 const u32 chan_value = LRADC_CH_ACCUMULATE |
428 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
429 unsigned int i, j = 0;
430
431 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
432 adc->buffer[j] = readl(adc->base + LRADC_CH(j));
433 writel(chan_value, adc->base + LRADC_CH(j));
434 adc->buffer[j] &= LRADC_CH_VALUE_MASK;
435 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
436 j++;
437 }
438
439 iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
440
441 iio_trigger_notify_done(iio->trig);
442
443 return IRQ_HANDLED;
444 }
445
446 static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
447 {
448 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
449 struct mxs_lradc_adc *adc = iio_priv(iio);
450 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
451
452 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
453
454 return 0;
455 }
456
457 static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
458 .owner = THIS_MODULE,
459 .set_trigger_state = &mxs_lradc_adc_configure_trigger,
460 };
461
462 static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
463 {
464 int ret;
465 struct iio_trigger *trig;
466 struct mxs_lradc_adc *adc = iio_priv(iio);
467
468 trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
469 iio->id);
470
471 trig->dev.parent = adc->dev;
472 iio_trigger_set_drvdata(trig, iio);
473 trig->ops = &mxs_lradc_adc_trigger_ops;
474
475 ret = iio_trigger_register(trig);
476 if (ret)
477 return ret;
478
479 adc->trig = trig;
480
481 return 0;
482 }
483
484 static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
485 {
486 struct mxs_lradc_adc *adc = iio_priv(iio);
487
488 iio_trigger_unregister(adc->trig);
489 }
490
491 static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
492 {
493 struct mxs_lradc_adc *adc = iio_priv(iio);
494 struct mxs_lradc *lradc = adc->lradc;
495 int chan, ofs = 0;
496 unsigned long enable = 0;
497 u32 ctrl4_set = 0;
498 u32 ctrl4_clr = 0;
499 u32 ctrl1_irq = 0;
500 const u32 chan_value = LRADC_CH_ACCUMULATE |
501 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
502
503 if (lradc->soc == IMX28_LRADC)
504 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
505 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
506 writel(lradc->buffer_vchans,
507 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
508
509 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
510 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
511 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
512 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
513 writel(chan_value, adc->base + LRADC_CH(ofs));
514 bitmap_set(&enable, ofs, 1);
515 ofs++;
516 }
517
518 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
519 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
520 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
521 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
522 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
523 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
524 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
525
526 return 0;
527 }
528
529 static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
530 {
531 struct mxs_lradc_adc *adc = iio_priv(iio);
532 struct mxs_lradc *lradc = adc->lradc;
533
534 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
535 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
536
537 writel(lradc->buffer_vchans,
538 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
539 if (lradc->soc == IMX28_LRADC)
540 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
541 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
542
543 return 0;
544 }
545
546 static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
547 const unsigned long *mask)
548 {
549 struct mxs_lradc_adc *adc = iio_priv(iio);
550 struct mxs_lradc *lradc = adc->lradc;
551 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
552 int rsvd_chans = 0;
553 unsigned long rsvd_mask = 0;
554
555 if (lradc->use_touchbutton)
556 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
557 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
558 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
559 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
560 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
561
562 if (lradc->use_touchbutton)
563 rsvd_chans++;
564 if (lradc->touchscreen_wire)
565 rsvd_chans += 2;
566
567 /* Test for attempts to map channels with special mode of operation. */
568 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
569 return false;
570
571 /* Test for attempts to map more channels then available slots. */
572 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
573 return false;
574
575 return true;
576 }
577
578 static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
579 .preenable = &mxs_lradc_adc_buffer_preenable,
580 .postenable = &iio_triggered_buffer_postenable,
581 .predisable = &iio_triggered_buffer_predisable,
582 .postdisable = &mxs_lradc_adc_buffer_postdisable,
583 .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
584 };
585
586 /* Driver initialization */
587 #define MXS_ADC_CHAN(idx, chan_type, name) { \
588 .type = (chan_type), \
589 .indexed = 1, \
590 .scan_index = (idx), \
591 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
592 BIT(IIO_CHAN_INFO_SCALE), \
593 .channel = (idx), \
594 .address = (idx), \
595 .scan_type = { \
596 .sign = 'u', \
597 .realbits = LRADC_RESOLUTION, \
598 .storagebits = 32, \
599 }, \
600 .datasheet_name = (name), \
601 }
602
603 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
604 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
605 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
606 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
607 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
608 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
609 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
610 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
611 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
612 /* Combined Temperature sensors */
613 {
614 .type = IIO_TEMP,
615 .indexed = 1,
616 .scan_index = 8,
617 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
618 BIT(IIO_CHAN_INFO_OFFSET) |
619 BIT(IIO_CHAN_INFO_SCALE),
620 .channel = 8,
621 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
622 .datasheet_name = "TEMP_DIE",
623 },
624 /* Hidden channel to keep indexes */
625 {
626 .type = IIO_TEMP,
627 .indexed = 1,
628 .scan_index = -1,
629 .channel = 9,
630 },
631 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
632 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
633 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
634 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
635 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
636 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
637 };
638
639 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
640 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
641 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
642 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
643 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
644 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
645 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
646 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
647 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
648 /* Combined Temperature sensors */
649 {
650 .type = IIO_TEMP,
651 .indexed = 1,
652 .scan_index = 8,
653 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
654 BIT(IIO_CHAN_INFO_OFFSET) |
655 BIT(IIO_CHAN_INFO_SCALE),
656 .channel = 8,
657 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
658 .datasheet_name = "TEMP_DIE",
659 },
660 /* Hidden channel to keep indexes */
661 {
662 .type = IIO_TEMP,
663 .indexed = 1,
664 .scan_index = -1,
665 .channel = 9,
666 },
667 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
668 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
669 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
670 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
671 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
672 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
673 };
674
675 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
676 {
677 /* The ADC always uses DELAY CHANNEL 0. */
678 const u32 adc_cfg =
679 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
680 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
681
682 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
683 writel(adc_cfg, adc->base + LRADC_DELAY(0));
684
685 /*
686 * Start internal temperature sensing by clearing bit
687 * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
688 * after power up.
689 */
690 writel(0, adc->base + LRADC_CTRL2);
691 }
692
693 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
694 {
695 writel(0, adc->base + LRADC_DELAY(0));
696 }
697
698 static int mxs_lradc_adc_probe(struct platform_device *pdev)
699 {
700 struct device *dev = &pdev->dev;
701 struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
702 struct mxs_lradc_adc *adc;
703 struct iio_dev *iio;
704 struct resource *iores;
705 int ret, irq, virq, i, s, n;
706 u64 scale_uv;
707 const char **irq_name;
708
709 /* Allocate the IIO device. */
710 iio = devm_iio_device_alloc(dev, sizeof(*adc));
711 if (!iio) {
712 dev_err(dev, "Failed to allocate IIO device\n");
713 return -ENOMEM;
714 }
715
716 adc = iio_priv(iio);
717 adc->lradc = lradc;
718 adc->dev = dev;
719
720 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
721 adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
722 if (IS_ERR(adc->base))
723 return PTR_ERR(adc->base);
724
725 init_completion(&adc->completion);
726 spin_lock_init(&adc->lock);
727
728 platform_set_drvdata(pdev, iio);
729
730 iio->name = pdev->name;
731 iio->dev.parent = dev;
732 iio->dev.of_node = dev->parent->of_node;
733 iio->info = &mxs_lradc_adc_iio_info;
734 iio->modes = INDIO_DIRECT_MODE;
735 iio->masklength = LRADC_MAX_TOTAL_CHANS;
736
737 if (lradc->soc == IMX23_LRADC) {
738 iio->channels = mx23_lradc_chan_spec;
739 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
740 irq_name = mx23_lradc_adc_irq_names;
741 n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
742 } else {
743 iio->channels = mx28_lradc_chan_spec;
744 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
745 irq_name = mx28_lradc_adc_irq_names;
746 n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
747 }
748
749 ret = stmp_reset_block(adc->base);
750 if (ret)
751 return ret;
752
753 for (i = 0; i < n; i++) {
754 irq = platform_get_irq_byname(pdev, irq_name[i]);
755 if (irq < 0)
756 return irq;
757
758 virq = irq_of_parse_and_map(dev->parent->of_node, irq);
759
760 ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
761 0, irq_name[i], iio);
762 if (ret)
763 return ret;
764 }
765
766 ret = mxs_lradc_adc_trigger_init(iio);
767 if (ret)
768 goto err_trig;
769
770 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
771 &mxs_lradc_adc_trigger_handler,
772 &mxs_lradc_adc_buffer_ops);
773 if (ret)
774 return ret;
775
776 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
777
778 /* Populate available ADC input ranges */
779 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
780 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
781 /*
782 * [s=0] = optional divider by two disabled (default)
783 * [s=1] = optional divider by two enabled
784 *
785 * The scale is calculated by doing:
786 * Vref >> (realbits - s)
787 * which multiplies by two on the second component
788 * of the array.
789 */
790 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
791 (LRADC_RESOLUTION - s);
792 adc->scale_avail[i][s].nano =
793 do_div(scale_uv, 100000000) * 10;
794 adc->scale_avail[i][s].integer = scale_uv;
795 }
796 }
797
798 /* Configure the hardware. */
799 mxs_lradc_adc_hw_init(adc);
800
801 /* Register IIO device. */
802 ret = iio_device_register(iio);
803 if (ret) {
804 dev_err(dev, "Failed to register IIO device\n");
805 goto err_dev;
806 }
807
808 return 0;
809
810 err_dev:
811 mxs_lradc_adc_hw_stop(adc);
812 mxs_lradc_adc_trigger_remove(iio);
813 err_trig:
814 iio_triggered_buffer_cleanup(iio);
815 return ret;
816 }
817
818 static int mxs_lradc_adc_remove(struct platform_device *pdev)
819 {
820 struct iio_dev *iio = platform_get_drvdata(pdev);
821 struct mxs_lradc_adc *adc = iio_priv(iio);
822
823 iio_device_unregister(iio);
824 mxs_lradc_adc_hw_stop(adc);
825 mxs_lradc_adc_trigger_remove(iio);
826 iio_triggered_buffer_cleanup(iio);
827
828 return 0;
829 }
830
831 static struct platform_driver mxs_lradc_adc_driver = {
832 .driver = {
833 .name = "mxs-lradc-adc",
834 },
835 .probe = mxs_lradc_adc_probe,
836 .remove = mxs_lradc_adc_remove,
837 };
838 module_platform_driver(mxs_lradc_adc_driver);
839
840 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
841 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
842 MODULE_LICENSE("GPL");
843 MODULE_ALIAS("platform:mxs-lradc-adc");