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Merge branches 'fixes' and 'mmci' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iio / adc / max1363.c
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33 #include <linux/module.h>
34
35 #include <linux/iio/iio.h>
36 #include <linux/iio/sysfs.h>
37 #include <linux/iio/events.h>
38 #include <linux/iio/buffer.h>
39 #include <linux/iio/driver.h>
40 #include <linux/iio/kfifo_buf.h>
41 #include <linux/iio/trigger_consumer.h>
42
43 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
44
45 /* There is a fair bit more defined here than currently
46 * used, but the intention is to support everything these
47 * chips do in the long run */
48
49 /* see data sheets */
50 /* max1363 and max1236, max1237, max1238, max1239 */
51 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
52 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
53 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
54 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
55 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
56 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
57
58 /* think about includeing max11600 etc - more settings */
59 #define MAX1363_SETUP_EXT_CLOCK 0x08
60 #define MAX1363_SETUP_INT_CLOCK 0x00
61 #define MAX1363_SETUP_UNIPOLAR 0x00
62 #define MAX1363_SETUP_BIPOLAR 0x04
63 #define MAX1363_SETUP_RESET 0x00
64 #define MAX1363_SETUP_NORESET 0x02
65 /* max1363 only - though don't care on others.
66 * For now monitor modes are not implemented as the relevant
67 * line is not connected on my test board.
68 * The definitions are here as I intend to add this soon.
69 */
70 #define MAX1363_SETUP_MONITOR_SETUP 0x01
71
72 /* Specific to the max1363 */
73 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
74 #define MAX1363_MON_INT_ENABLE 0x01
75
76 /* defined for readability reasons */
77 /* All chips */
78 #define MAX1363_CONFIG_BYTE(a) ((a))
79
80 #define MAX1363_CONFIG_SE 0x01
81 #define MAX1363_CONFIG_DE 0x00
82 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
83 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
84 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
85 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
86 /* max123{6-9} only */
87 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
88
89 /* max1363 only - merely part of channel selects or don't care for others*/
90 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
91
92 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
93
94 /* max1363 strictly 0x06 - but doesn't matter */
95 #define MAX1363_CHANNEL_SEL_MASK 0x1E
96 #define MAX1363_SCAN_MASK 0x60
97 #define MAX1363_SE_DE_MASK 0x01
98
99 #define MAX1363_MAX_CHANNELS 25
100 /**
101 * struct max1363_mode - scan mode information
102 * @conf: The corresponding value of the configuration register
103 * @modemask: Bit mask corresponding to channels enabled in this mode
104 */
105 struct max1363_mode {
106 int8_t conf;
107 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
108 };
109
110 /* This must be maintained along side the max1363_mode_table in max1363_core */
111 enum max1363_modes {
112 /* Single read of a single channel */
113 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
114 /* Differential single read */
115 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
116 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
117 /* Scan to channel and mid to channel where overlapping */
118 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
119 s6to7, s0to7, s6to8, s0to8, s6to9,
120 s0to9, s6to10, s0to10, s6to11, s0to11,
121 /* Differential scan to channel and mid to channel where overlapping */
122 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
123 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
124 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
125 d7m6to11m10, d1m0to11m10,
126 };
127
128 /**
129 * struct max1363_chip_info - chip specifc information
130 * @info: iio core function callbacks structure
131 * @channels: channel specification
132 * @num_channels: number of channels
133 * @mode_list: array of available scan modes
134 * @default_mode: the scan mode in which the chip starts up
135 * @int_vref_mv: the internal reference voltage
136 * @num_channels: number of channels
137 * @bits: accuracy of the adc in bits
138 */
139 struct max1363_chip_info {
140 const struct iio_info *info;
141 const struct iio_chan_spec *channels;
142 int num_channels;
143 const enum max1363_modes *mode_list;
144 enum max1363_modes default_mode;
145 u16 int_vref_mv;
146 u8 num_modes;
147 u8 bits;
148 };
149
150 /**
151 * struct max1363_state - driver instance specific data
152 * @client: i2c_client
153 * @setupbyte: cache of current device setup byte
154 * @configbyte: cache of current device config byte
155 * @chip_info: chip model specific constants, available modes etc
156 * @current_mode: the scan mode of this chip
157 * @requestedmask: a valid requested set of channels
158 * @reg: supply regulator
159 * @monitor_on: whether monitor mode is enabled
160 * @monitor_speed: parameter corresponding to device monitor speed setting
161 * @mask_high: bitmask for enabled high thresholds
162 * @mask_low: bitmask for enabled low thresholds
163 * @thresh_high: high threshold values
164 * @thresh_low: low threshold values
165 */
166 struct max1363_state {
167 struct i2c_client *client;
168 u8 setupbyte;
169 u8 configbyte;
170 const struct max1363_chip_info *chip_info;
171 const struct max1363_mode *current_mode;
172 u32 requestedmask;
173 struct regulator *reg;
174
175 /* Using monitor modes and buffer at the same time is
176 currently not supported */
177 bool monitor_on;
178 unsigned int monitor_speed:3;
179 u8 mask_high;
180 u8 mask_low;
181 /* 4x unipolar first then the fours bipolar ones */
182 s16 thresh_high[8];
183 s16 thresh_low[8];
184 };
185
186 #define MAX1363_MODE_SINGLE(_num, _mask) { \
187 .conf = MAX1363_CHANNEL_SEL(_num) \
188 | MAX1363_CONFIG_SCAN_SINGLE_1 \
189 | MAX1363_CONFIG_SE, \
190 .modemask[0] = _mask, \
191 }
192
193 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
194 .conf = MAX1363_CHANNEL_SEL(_num) \
195 | MAX1363_CONFIG_SCAN_TO_CS \
196 | MAX1363_CONFIG_SE, \
197 .modemask[0] = _mask, \
198 }
199
200 /* note not available for max1363 hence naming */
201 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
202 .conf = MAX1363_CHANNEL_SEL(_num) \
203 | MAX1236_SCAN_MID_TO_CHANNEL \
204 | MAX1363_CONFIG_SE, \
205 .modemask[0] = _mask \
206 }
207
208 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
209 .conf = MAX1363_CHANNEL_SEL(_nump) \
210 | MAX1363_CONFIG_SCAN_SINGLE_1 \
211 | MAX1363_CONFIG_DE, \
212 .modemask[0] = _mask \
213 }
214
215 /* Can't think how to automate naming so specify for now */
216 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
217 .conf = MAX1363_CHANNEL_SEL(_num) \
218 | MAX1363_CONFIG_SCAN_TO_CS \
219 | MAX1363_CONFIG_DE, \
220 .modemask[0] = _mask \
221 }
222
223 /* note only available for max1363 hence naming */
224 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
225 .conf = MAX1363_CHANNEL_SEL(_num) \
226 | MAX1236_SCAN_MID_TO_CHANNEL \
227 | MAX1363_CONFIG_SE, \
228 .modemask[0] = _mask \
229 }
230
231 static const struct max1363_mode max1363_mode_table[] = {
232 /* All of the single channel options first */
233 MAX1363_MODE_SINGLE(0, 1 << 0),
234 MAX1363_MODE_SINGLE(1, 1 << 1),
235 MAX1363_MODE_SINGLE(2, 1 << 2),
236 MAX1363_MODE_SINGLE(3, 1 << 3),
237 MAX1363_MODE_SINGLE(4, 1 << 4),
238 MAX1363_MODE_SINGLE(5, 1 << 5),
239 MAX1363_MODE_SINGLE(6, 1 << 6),
240 MAX1363_MODE_SINGLE(7, 1 << 7),
241 MAX1363_MODE_SINGLE(8, 1 << 8),
242 MAX1363_MODE_SINGLE(9, 1 << 9),
243 MAX1363_MODE_SINGLE(10, 1 << 10),
244 MAX1363_MODE_SINGLE(11, 1 << 11),
245
246 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
247 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
248 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
249 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
250 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
251 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
252 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
253 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
254 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
255 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
256 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
257 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
258
259 /* The multichannel scans next */
260 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
261 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
262 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
263 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
264 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
265 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
266 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
267 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
268 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
269 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
270 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
271 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
272 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
273 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
274 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
275 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
276 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
277
278 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
279 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
280 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
281 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
282 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
283 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
290 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
292 };
293
294 static const struct max1363_mode
295 *max1363_match_mode(const unsigned long *mask,
296 const struct max1363_chip_info *ci)
297 {
298 int i;
299 if (mask)
300 for (i = 0; i < ci->num_modes; i++)
301 if (bitmap_subset(mask,
302 max1363_mode_table[ci->mode_list[i]].
303 modemask,
304 MAX1363_MAX_CHANNELS))
305 return &max1363_mode_table[ci->mode_list[i]];
306 return NULL;
307 }
308
309 static int max1363_write_basic_config(struct i2c_client *client,
310 unsigned char d1,
311 unsigned char d2)
312 {
313 u8 tx_buf[2] = {d1, d2};
314
315 return i2c_master_send(client, tx_buf, 2);
316 }
317
318 static int max1363_set_scan_mode(struct max1363_state *st)
319 {
320 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
321 | MAX1363_SCAN_MASK
322 | MAX1363_SE_DE_MASK);
323 st->configbyte |= st->current_mode->conf;
324
325 return max1363_write_basic_config(st->client,
326 st->setupbyte,
327 st->configbyte);
328 }
329
330 static int max1363_read_single_chan(struct iio_dev *indio_dev,
331 struct iio_chan_spec const *chan,
332 int *val,
333 long m)
334 {
335 int ret = 0;
336 s32 data;
337 char rxbuf[2];
338 struct max1363_state *st = iio_priv(indio_dev);
339 struct i2c_client *client = st->client;
340
341 mutex_lock(&indio_dev->mlock);
342 /*
343 * If monitor mode is enabled, the method for reading a single
344 * channel will have to be rather different and has not yet
345 * been implemented.
346 *
347 * Also, cannot read directly if buffered capture enabled.
348 */
349 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
350 ret = -EBUSY;
351 goto error_ret;
352 }
353
354 /* Check to see if current scan mode is correct */
355 if (st->current_mode != &max1363_mode_table[chan->address]) {
356 /* Update scan mode if needed */
357 st->current_mode = &max1363_mode_table[chan->address];
358 ret = max1363_set_scan_mode(st);
359 if (ret < 0)
360 goto error_ret;
361 }
362 if (st->chip_info->bits != 8) {
363 /* Get reading */
364 data = i2c_master_recv(client, rxbuf, 2);
365 if (data < 0) {
366 ret = data;
367 goto error_ret;
368 }
369 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
370 } else {
371 /* Get reading */
372 data = i2c_master_recv(client, rxbuf, 1);
373 if (data < 0) {
374 ret = data;
375 goto error_ret;
376 }
377 data = rxbuf[0];
378 }
379 *val = data;
380 error_ret:
381 mutex_unlock(&indio_dev->mlock);
382 return ret;
383
384 }
385
386 static int max1363_read_raw(struct iio_dev *indio_dev,
387 struct iio_chan_spec const *chan,
388 int *val,
389 int *val2,
390 long m)
391 {
392 struct max1363_state *st = iio_priv(indio_dev);
393 int ret;
394 switch (m) {
395 case IIO_CHAN_INFO_RAW:
396 ret = max1363_read_single_chan(indio_dev, chan, val, m);
397 if (ret < 0)
398 return ret;
399 return IIO_VAL_INT;
400 case IIO_CHAN_INFO_SCALE:
401 if ((1 << (st->chip_info->bits + 1)) >
402 st->chip_info->int_vref_mv) {
403 *val = 0;
404 *val2 = 500000;
405 return IIO_VAL_INT_PLUS_MICRO;
406 } else {
407 *val = (st->chip_info->int_vref_mv)
408 >> st->chip_info->bits;
409 return IIO_VAL_INT;
410 }
411 default:
412 return -EINVAL;
413 }
414 return 0;
415 }
416
417 /* Applies to max1363 */
418 static const enum max1363_modes max1363_mode_list[] = {
419 _s0, _s1, _s2, _s3,
420 s0to1, s0to2, s0to3,
421 d0m1, d2m3, d1m0, d3m2,
422 d0m1to2m3, d1m0to3m2,
423 };
424
425 #define MAX1363_EV_M \
426 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
427 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
428 #define MAX1363_INFO_MASK (IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
429 IIO_CHAN_INFO_SCALE_SHARED_BIT)
430 #define MAX1363_CHAN_U(num, addr, si, bits, evmask) \
431 { \
432 .type = IIO_VOLTAGE, \
433 .indexed = 1, \
434 .channel = num, \
435 .address = addr, \
436 .info_mask = MAX1363_INFO_MASK, \
437 .datasheet_name = "AIN"#num, \
438 .scan_type = { \
439 .sign = 'u', \
440 .realbits = bits, \
441 .storagebits = (bits > 8) ? 16 : 8, \
442 .endianness = IIO_BE, \
443 }, \
444 .scan_index = si, \
445 .event_mask = evmask, \
446 }
447
448 /* bipolar channel */
449 #define MAX1363_CHAN_B(num, num2, addr, si, bits, evmask) \
450 { \
451 .type = IIO_VOLTAGE, \
452 .differential = 1, \
453 .indexed = 1, \
454 .channel = num, \
455 .channel2 = num2, \
456 .address = addr, \
457 .info_mask = MAX1363_INFO_MASK, \
458 .datasheet_name = "AIN"#num"-AIN"#num2, \
459 .scan_type = { \
460 .sign = 's', \
461 .realbits = bits, \
462 .storagebits = (bits > 8) ? 16 : 8, \
463 .endianness = IIO_BE, \
464 }, \
465 .scan_index = si, \
466 .event_mask = evmask, \
467 }
468
469 #define MAX1363_4X_CHANS(bits, em) { \
470 MAX1363_CHAN_U(0, _s0, 0, bits, em), \
471 MAX1363_CHAN_U(1, _s1, 1, bits, em), \
472 MAX1363_CHAN_U(2, _s2, 2, bits, em), \
473 MAX1363_CHAN_U(3, _s3, 3, bits, em), \
474 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, em), \
475 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, em), \
476 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, em), \
477 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, em), \
478 IIO_CHAN_SOFT_TIMESTAMP(8) \
479 }
480
481 static const struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8, 0);
482 static const struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10, 0);
483 static const struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12, 0);
484 static const struct iio_chan_spec max1361_channels[] =
485 MAX1363_4X_CHANS(10, MAX1363_EV_M);
486 static const struct iio_chan_spec max1363_channels[] =
487 MAX1363_4X_CHANS(12, MAX1363_EV_M);
488
489 /* Applies to max1236, max1237 */
490 static const enum max1363_modes max1236_mode_list[] = {
491 _s0, _s1, _s2, _s3,
492 s0to1, s0to2, s0to3,
493 d0m1, d2m3, d1m0, d3m2,
494 d0m1to2m3, d1m0to3m2,
495 s2to3,
496 };
497
498 /* Applies to max1238, max1239 */
499 static const enum max1363_modes max1238_mode_list[] = {
500 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
501 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
502 s0to7, s0to8, s0to9, s0to10, s0to11,
503 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
504 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
505 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
506 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
507 s6to7, s6to8, s6to9, s6to10, s6to11,
508 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
509 };
510
511 #define MAX1363_12X_CHANS(bits) { \
512 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
513 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
514 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
515 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
516 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
517 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
518 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
519 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
520 MAX1363_CHAN_U(8, _s8, 8, bits, 0), \
521 MAX1363_CHAN_U(9, _s9, 9, bits, 0), \
522 MAX1363_CHAN_U(10, _s10, 10, bits, 0), \
523 MAX1363_CHAN_U(11, _s11, 11, bits, 0), \
524 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, 0), \
525 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, 0), \
526 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, 0), \
527 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, 0), \
528 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, 0), \
529 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, 0), \
530 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, 0), \
531 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, 0), \
532 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, 0), \
533 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, 0), \
534 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, 0), \
535 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, 0), \
536 IIO_CHAN_SOFT_TIMESTAMP(24) \
537 }
538 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
539 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
540 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
541
542 static const enum max1363_modes max11607_mode_list[] = {
543 _s0, _s1, _s2, _s3,
544 s0to1, s0to2, s0to3,
545 s2to3,
546 d0m1, d2m3, d1m0, d3m2,
547 d0m1to2m3, d1m0to3m2,
548 };
549
550 static const enum max1363_modes max11608_mode_list[] = {
551 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
552 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
553 s6to7,
554 d0m1, d2m3, d4m5, d6m7,
555 d1m0, d3m2, d5m4, d7m6,
556 d0m1to2m3, d0m1to4m5, d0m1to6m7,
557 d1m0to3m2, d1m0to5m4, d1m0to7m6,
558 };
559
560 #define MAX1363_8X_CHANS(bits) { \
561 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
562 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
563 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
564 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
565 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
566 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
567 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
568 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
569 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, 0), \
570 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, 0), \
571 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, 0), \
572 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, 0), \
573 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, 0), \
574 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, 0), \
575 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, 0), \
576 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, 0), \
577 IIO_CHAN_SOFT_TIMESTAMP(16) \
578 }
579 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
580 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
581 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
582
583 static const enum max1363_modes max11644_mode_list[] = {
584 _s0, _s1, s0to1, d0m1, d1m0,
585 };
586
587 #define MAX1363_2X_CHANS(bits) { \
588 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
589 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
590 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, 0), \
591 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, 0), \
592 IIO_CHAN_SOFT_TIMESTAMP(4) \
593 }
594
595 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
596 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
597
598 enum { max1361,
599 max1362,
600 max1363,
601 max1364,
602 max1036,
603 max1037,
604 max1038,
605 max1039,
606 max1136,
607 max1137,
608 max1138,
609 max1139,
610 max1236,
611 max1237,
612 max1238,
613 max1239,
614 max11600,
615 max11601,
616 max11602,
617 max11603,
618 max11604,
619 max11605,
620 max11606,
621 max11607,
622 max11608,
623 max11609,
624 max11610,
625 max11611,
626 max11612,
627 max11613,
628 max11614,
629 max11615,
630 max11616,
631 max11617,
632 max11644,
633 max11645,
634 max11646,
635 max11647
636 };
637
638 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
639 8300, 4200, 2000, 1000 };
640
641 static ssize_t max1363_monitor_show_freq(struct device *dev,
642 struct device_attribute *attr,
643 char *buf)
644 {
645 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
646 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
647 }
648
649 static ssize_t max1363_monitor_store_freq(struct device *dev,
650 struct device_attribute *attr,
651 const char *buf,
652 size_t len)
653 {
654 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
655 struct max1363_state *st = iio_priv(indio_dev);
656 int i, ret;
657 unsigned long val;
658 bool found = false;
659
660 ret = strict_strtoul(buf, 10, &val);
661 if (ret)
662 return -EINVAL;
663 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
664 if (val == max1363_monitor_speeds[i]) {
665 found = true;
666 break;
667 }
668 if (!found)
669 return -EINVAL;
670
671 mutex_lock(&indio_dev->mlock);
672 st->monitor_speed = i;
673 mutex_unlock(&indio_dev->mlock);
674
675 return 0;
676 }
677
678 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
679 max1363_monitor_show_freq,
680 max1363_monitor_store_freq);
681
682 static IIO_CONST_ATTR(sampling_frequency_available,
683 "133000 665000 33300 16600 8300 4200 2000 1000");
684
685 static int max1363_read_thresh(struct iio_dev *indio_dev,
686 u64 event_code,
687 int *val)
688 {
689 struct max1363_state *st = iio_priv(indio_dev);
690 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
691 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
692 else
693 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
694 return 0;
695 }
696
697 static int max1363_write_thresh(struct iio_dev *indio_dev,
698 u64 event_code,
699 int val)
700 {
701 struct max1363_state *st = iio_priv(indio_dev);
702 /* make it handle signed correctly as well */
703 switch (st->chip_info->bits) {
704 case 10:
705 if (val > 0x3FF)
706 return -EINVAL;
707 break;
708 case 12:
709 if (val > 0xFFF)
710 return -EINVAL;
711 break;
712 }
713
714 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
715 case IIO_EV_DIR_FALLING:
716 st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
717 break;
718 case IIO_EV_DIR_RISING:
719 st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
720 break;
721 }
722
723 return 0;
724 }
725
726 static const u64 max1363_event_codes[] = {
727 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
728 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
729 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
730 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
731 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
732 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
733 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
734 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
735 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
736 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
737 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
738 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
739 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
740 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
741 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
742 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
743 };
744
745 static irqreturn_t max1363_event_handler(int irq, void *private)
746 {
747 struct iio_dev *indio_dev = private;
748 struct max1363_state *st = iio_priv(indio_dev);
749 s64 timestamp = iio_get_time_ns();
750 unsigned long mask, loc;
751 u8 rx;
752 u8 tx[2] = { st->setupbyte,
753 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
754
755 i2c_master_recv(st->client, &rx, 1);
756 mask = rx;
757 for_each_set_bit(loc, &mask, 8)
758 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
759 i2c_master_send(st->client, tx, 2);
760
761 return IRQ_HANDLED;
762 }
763
764 static int max1363_read_event_config(struct iio_dev *indio_dev,
765 u64 event_code)
766 {
767 struct max1363_state *st = iio_priv(indio_dev);
768 int val;
769 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
770
771 mutex_lock(&indio_dev->mlock);
772 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
773 val = (1 << number) & st->mask_low;
774 else
775 val = (1 << number) & st->mask_high;
776 mutex_unlock(&indio_dev->mlock);
777
778 return val;
779 }
780
781 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
782 {
783 u8 *tx_buf;
784 int ret, i = 3, j;
785 unsigned long numelements;
786 int len;
787 const long *modemask;
788
789 if (!enabled) {
790 /* transition to buffered capture is not currently supported */
791 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
792 st->configbyte &= ~MAX1363_SCAN_MASK;
793 st->monitor_on = false;
794 return max1363_write_basic_config(st->client,
795 st->setupbyte,
796 st->configbyte);
797 }
798
799 /* Ensure we are in the relevant mode */
800 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
801 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
802 | MAX1363_SCAN_MASK
803 | MAX1363_SE_DE_MASK);
804 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
805 if ((st->mask_low | st->mask_high) & 0x0F) {
806 st->configbyte |= max1363_mode_table[s0to3].conf;
807 modemask = max1363_mode_table[s0to3].modemask;
808 } else if ((st->mask_low | st->mask_high) & 0x30) {
809 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
810 modemask = max1363_mode_table[d0m1to2m3].modemask;
811 } else {
812 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
813 modemask = max1363_mode_table[d1m0to3m2].modemask;
814 }
815 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
816 len = 3 * numelements + 3;
817 tx_buf = kmalloc(len, GFP_KERNEL);
818 if (!tx_buf) {
819 ret = -ENOMEM;
820 goto error_ret;
821 }
822 tx_buf[0] = st->configbyte;
823 tx_buf[1] = st->setupbyte;
824 tx_buf[2] = (st->monitor_speed << 1);
825
826 /*
827 * So we need to do yet another bit of nefarious scan mode
828 * setup to match what we need.
829 */
830 for (j = 0; j < 8; j++)
831 if (test_bit(j, modemask)) {
832 /* Establish the mode is in the scan */
833 if (st->mask_low & (1 << j)) {
834 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
835 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
836 } else if (j < 4) {
837 tx_buf[i] = 0;
838 tx_buf[i + 1] = 0;
839 } else {
840 tx_buf[i] = 0x80;
841 tx_buf[i + 1] = 0;
842 }
843 if (st->mask_high & (1 << j)) {
844 tx_buf[i + 1] |=
845 (st->thresh_high[j] >> 8) & 0x0F;
846 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
847 } else if (j < 4) {
848 tx_buf[i + 1] |= 0x0F;
849 tx_buf[i + 2] = 0xFF;
850 } else {
851 tx_buf[i + 1] |= 0x07;
852 tx_buf[i + 2] = 0xFF;
853 }
854 i += 3;
855 }
856
857
858 ret = i2c_master_send(st->client, tx_buf, len);
859 if (ret < 0)
860 goto error_ret;
861 if (ret != len) {
862 ret = -EIO;
863 goto error_ret;
864 }
865
866 /*
867 * Now that we hopefully have sensible thresholds in place it is
868 * time to turn the interrupts on.
869 * It is unclear from the data sheet if this should be necessary
870 * (i.e. whether monitor mode setup is atomic) but it appears to
871 * be in practice.
872 */
873 tx_buf[0] = st->setupbyte;
874 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
875 ret = i2c_master_send(st->client, tx_buf, 2);
876 if (ret < 0)
877 goto error_ret;
878 if (ret != 2) {
879 ret = -EIO;
880 goto error_ret;
881 }
882 ret = 0;
883 st->monitor_on = true;
884 error_ret:
885
886 kfree(tx_buf);
887
888 return ret;
889 }
890
891 /*
892 * To keep this manageable we always use one of 3 scan modes.
893 * Scan 0...3, 0-1,2-3 and 1-0,3-2
894 */
895
896 static inline int __max1363_check_event_mask(int thismask, int checkmask)
897 {
898 int ret = 0;
899 /* Is it unipolar */
900 if (thismask < 4) {
901 if (checkmask & ~0x0F) {
902 ret = -EBUSY;
903 goto error_ret;
904 }
905 } else if (thismask < 6) {
906 if (checkmask & ~0x30) {
907 ret = -EBUSY;
908 goto error_ret;
909 }
910 } else if (checkmask & ~0xC0)
911 ret = -EBUSY;
912 error_ret:
913 return ret;
914 }
915
916 static int max1363_write_event_config(struct iio_dev *indio_dev,
917 u64 event_code,
918 int state)
919 {
920 int ret = 0;
921 struct max1363_state *st = iio_priv(indio_dev);
922 u16 unifiedmask;
923 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
924
925 mutex_lock(&indio_dev->mlock);
926 unifiedmask = st->mask_low | st->mask_high;
927 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
928
929 if (state == 0)
930 st->mask_low &= ~(1 << number);
931 else {
932 ret = __max1363_check_event_mask((1 << number),
933 unifiedmask);
934 if (ret)
935 goto error_ret;
936 st->mask_low |= (1 << number);
937 }
938 } else {
939 if (state == 0)
940 st->mask_high &= ~(1 << number);
941 else {
942 ret = __max1363_check_event_mask((1 << number),
943 unifiedmask);
944 if (ret)
945 goto error_ret;
946 st->mask_high |= (1 << number);
947 }
948 }
949
950 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
951 error_ret:
952 mutex_unlock(&indio_dev->mlock);
953
954 return ret;
955 }
956
957 /*
958 * As with scan_elements, only certain sets of these can
959 * be combined.
960 */
961 static struct attribute *max1363_event_attributes[] = {
962 &iio_dev_attr_sampling_frequency.dev_attr.attr,
963 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
964 NULL,
965 };
966
967 static struct attribute_group max1363_event_attribute_group = {
968 .attrs = max1363_event_attributes,
969 .name = "events",
970 };
971
972 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
973 const unsigned long *scan_mask)
974 {
975 struct max1363_state *st = iio_priv(indio_dev);
976
977 /*
978 * Need to figure out the current mode based upon the requested
979 * scan mask in iio_dev
980 */
981 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
982 if (!st->current_mode)
983 return -EINVAL;
984 max1363_set_scan_mode(st);
985 return 0;
986 }
987
988 static const struct iio_info max1238_info = {
989 .read_raw = &max1363_read_raw,
990 .driver_module = THIS_MODULE,
991 .update_scan_mode = &max1363_update_scan_mode,
992 };
993
994 static const struct iio_info max1363_info = {
995 .read_event_value = &max1363_read_thresh,
996 .write_event_value = &max1363_write_thresh,
997 .read_event_config = &max1363_read_event_config,
998 .write_event_config = &max1363_write_event_config,
999 .read_raw = &max1363_read_raw,
1000 .update_scan_mode = &max1363_update_scan_mode,
1001 .driver_module = THIS_MODULE,
1002 .event_attrs = &max1363_event_attribute_group,
1003 };
1004
1005 /* max1363 and max1368 tested - rest from data sheet */
1006 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1007 [max1361] = {
1008 .bits = 10,
1009 .int_vref_mv = 2048,
1010 .mode_list = max1363_mode_list,
1011 .num_modes = ARRAY_SIZE(max1363_mode_list),
1012 .default_mode = s0to3,
1013 .channels = max1361_channels,
1014 .num_channels = ARRAY_SIZE(max1361_channels),
1015 .info = &max1363_info,
1016 },
1017 [max1362] = {
1018 .bits = 10,
1019 .int_vref_mv = 4096,
1020 .mode_list = max1363_mode_list,
1021 .num_modes = ARRAY_SIZE(max1363_mode_list),
1022 .default_mode = s0to3,
1023 .channels = max1361_channels,
1024 .num_channels = ARRAY_SIZE(max1361_channels),
1025 .info = &max1363_info,
1026 },
1027 [max1363] = {
1028 .bits = 12,
1029 .int_vref_mv = 2048,
1030 .mode_list = max1363_mode_list,
1031 .num_modes = ARRAY_SIZE(max1363_mode_list),
1032 .default_mode = s0to3,
1033 .channels = max1363_channels,
1034 .num_channels = ARRAY_SIZE(max1363_channels),
1035 .info = &max1363_info,
1036 },
1037 [max1364] = {
1038 .bits = 12,
1039 .int_vref_mv = 4096,
1040 .mode_list = max1363_mode_list,
1041 .num_modes = ARRAY_SIZE(max1363_mode_list),
1042 .default_mode = s0to3,
1043 .channels = max1363_channels,
1044 .num_channels = ARRAY_SIZE(max1363_channels),
1045 .info = &max1363_info,
1046 },
1047 [max1036] = {
1048 .bits = 8,
1049 .int_vref_mv = 4096,
1050 .mode_list = max1236_mode_list,
1051 .num_modes = ARRAY_SIZE(max1236_mode_list),
1052 .default_mode = s0to3,
1053 .info = &max1238_info,
1054 .channels = max1036_channels,
1055 .num_channels = ARRAY_SIZE(max1036_channels),
1056 },
1057 [max1037] = {
1058 .bits = 8,
1059 .int_vref_mv = 2048,
1060 .mode_list = max1236_mode_list,
1061 .num_modes = ARRAY_SIZE(max1236_mode_list),
1062 .default_mode = s0to3,
1063 .info = &max1238_info,
1064 .channels = max1036_channels,
1065 .num_channels = ARRAY_SIZE(max1036_channels),
1066 },
1067 [max1038] = {
1068 .bits = 8,
1069 .int_vref_mv = 4096,
1070 .mode_list = max1238_mode_list,
1071 .num_modes = ARRAY_SIZE(max1238_mode_list),
1072 .default_mode = s0to11,
1073 .info = &max1238_info,
1074 .channels = max1038_channels,
1075 .num_channels = ARRAY_SIZE(max1038_channels),
1076 },
1077 [max1039] = {
1078 .bits = 8,
1079 .int_vref_mv = 2048,
1080 .mode_list = max1238_mode_list,
1081 .num_modes = ARRAY_SIZE(max1238_mode_list),
1082 .default_mode = s0to11,
1083 .info = &max1238_info,
1084 .channels = max1038_channels,
1085 .num_channels = ARRAY_SIZE(max1038_channels),
1086 },
1087 [max1136] = {
1088 .bits = 10,
1089 .int_vref_mv = 4096,
1090 .mode_list = max1236_mode_list,
1091 .num_modes = ARRAY_SIZE(max1236_mode_list),
1092 .default_mode = s0to3,
1093 .info = &max1238_info,
1094 .channels = max1136_channels,
1095 .num_channels = ARRAY_SIZE(max1136_channels),
1096 },
1097 [max1137] = {
1098 .bits = 10,
1099 .int_vref_mv = 2048,
1100 .mode_list = max1236_mode_list,
1101 .num_modes = ARRAY_SIZE(max1236_mode_list),
1102 .default_mode = s0to3,
1103 .info = &max1238_info,
1104 .channels = max1136_channels,
1105 .num_channels = ARRAY_SIZE(max1136_channels),
1106 },
1107 [max1138] = {
1108 .bits = 10,
1109 .int_vref_mv = 4096,
1110 .mode_list = max1238_mode_list,
1111 .num_modes = ARRAY_SIZE(max1238_mode_list),
1112 .default_mode = s0to11,
1113 .info = &max1238_info,
1114 .channels = max1138_channels,
1115 .num_channels = ARRAY_SIZE(max1138_channels),
1116 },
1117 [max1139] = {
1118 .bits = 10,
1119 .int_vref_mv = 2048,
1120 .mode_list = max1238_mode_list,
1121 .num_modes = ARRAY_SIZE(max1238_mode_list),
1122 .default_mode = s0to11,
1123 .info = &max1238_info,
1124 .channels = max1138_channels,
1125 .num_channels = ARRAY_SIZE(max1138_channels),
1126 },
1127 [max1236] = {
1128 .bits = 12,
1129 .int_vref_mv = 4096,
1130 .mode_list = max1236_mode_list,
1131 .num_modes = ARRAY_SIZE(max1236_mode_list),
1132 .default_mode = s0to3,
1133 .info = &max1238_info,
1134 .channels = max1236_channels,
1135 .num_channels = ARRAY_SIZE(max1236_channels),
1136 },
1137 [max1237] = {
1138 .bits = 12,
1139 .int_vref_mv = 2048,
1140 .mode_list = max1236_mode_list,
1141 .num_modes = ARRAY_SIZE(max1236_mode_list),
1142 .default_mode = s0to3,
1143 .info = &max1238_info,
1144 .channels = max1236_channels,
1145 .num_channels = ARRAY_SIZE(max1236_channels),
1146 },
1147 [max1238] = {
1148 .bits = 12,
1149 .int_vref_mv = 4096,
1150 .mode_list = max1238_mode_list,
1151 .num_modes = ARRAY_SIZE(max1238_mode_list),
1152 .default_mode = s0to11,
1153 .info = &max1238_info,
1154 .channels = max1238_channels,
1155 .num_channels = ARRAY_SIZE(max1238_channels),
1156 },
1157 [max1239] = {
1158 .bits = 12,
1159 .int_vref_mv = 2048,
1160 .mode_list = max1238_mode_list,
1161 .num_modes = ARRAY_SIZE(max1238_mode_list),
1162 .default_mode = s0to11,
1163 .info = &max1238_info,
1164 .channels = max1238_channels,
1165 .num_channels = ARRAY_SIZE(max1238_channels),
1166 },
1167 [max11600] = {
1168 .bits = 8,
1169 .int_vref_mv = 4096,
1170 .mode_list = max11607_mode_list,
1171 .num_modes = ARRAY_SIZE(max11607_mode_list),
1172 .default_mode = s0to3,
1173 .info = &max1238_info,
1174 .channels = max1036_channels,
1175 .num_channels = ARRAY_SIZE(max1036_channels),
1176 },
1177 [max11601] = {
1178 .bits = 8,
1179 .int_vref_mv = 2048,
1180 .mode_list = max11607_mode_list,
1181 .num_modes = ARRAY_SIZE(max11607_mode_list),
1182 .default_mode = s0to3,
1183 .info = &max1238_info,
1184 .channels = max1036_channels,
1185 .num_channels = ARRAY_SIZE(max1036_channels),
1186 },
1187 [max11602] = {
1188 .bits = 8,
1189 .int_vref_mv = 4096,
1190 .mode_list = max11608_mode_list,
1191 .num_modes = ARRAY_SIZE(max11608_mode_list),
1192 .default_mode = s0to7,
1193 .info = &max1238_info,
1194 .channels = max11602_channels,
1195 .num_channels = ARRAY_SIZE(max11602_channels),
1196 },
1197 [max11603] = {
1198 .bits = 8,
1199 .int_vref_mv = 2048,
1200 .mode_list = max11608_mode_list,
1201 .num_modes = ARRAY_SIZE(max11608_mode_list),
1202 .default_mode = s0to7,
1203 .info = &max1238_info,
1204 .channels = max11602_channels,
1205 .num_channels = ARRAY_SIZE(max11602_channels),
1206 },
1207 [max11604] = {
1208 .bits = 8,
1209 .int_vref_mv = 4098,
1210 .mode_list = max1238_mode_list,
1211 .num_modes = ARRAY_SIZE(max1238_mode_list),
1212 .default_mode = s0to11,
1213 .info = &max1238_info,
1214 .channels = max1238_channels,
1215 .num_channels = ARRAY_SIZE(max1238_channels),
1216 },
1217 [max11605] = {
1218 .bits = 8,
1219 .int_vref_mv = 2048,
1220 .mode_list = max1238_mode_list,
1221 .num_modes = ARRAY_SIZE(max1238_mode_list),
1222 .default_mode = s0to11,
1223 .info = &max1238_info,
1224 .channels = max1238_channels,
1225 .num_channels = ARRAY_SIZE(max1238_channels),
1226 },
1227 [max11606] = {
1228 .bits = 10,
1229 .int_vref_mv = 4096,
1230 .mode_list = max11607_mode_list,
1231 .num_modes = ARRAY_SIZE(max11607_mode_list),
1232 .default_mode = s0to3,
1233 .info = &max1238_info,
1234 .channels = max1136_channels,
1235 .num_channels = ARRAY_SIZE(max1136_channels),
1236 },
1237 [max11607] = {
1238 .bits = 10,
1239 .int_vref_mv = 2048,
1240 .mode_list = max11607_mode_list,
1241 .num_modes = ARRAY_SIZE(max11607_mode_list),
1242 .default_mode = s0to3,
1243 .info = &max1238_info,
1244 .channels = max1136_channels,
1245 .num_channels = ARRAY_SIZE(max1136_channels),
1246 },
1247 [max11608] = {
1248 .bits = 10,
1249 .int_vref_mv = 4096,
1250 .mode_list = max11608_mode_list,
1251 .num_modes = ARRAY_SIZE(max11608_mode_list),
1252 .default_mode = s0to7,
1253 .info = &max1238_info,
1254 .channels = max11608_channels,
1255 .num_channels = ARRAY_SIZE(max11608_channels),
1256 },
1257 [max11609] = {
1258 .bits = 10,
1259 .int_vref_mv = 2048,
1260 .mode_list = max11608_mode_list,
1261 .num_modes = ARRAY_SIZE(max11608_mode_list),
1262 .default_mode = s0to7,
1263 .info = &max1238_info,
1264 .channels = max11608_channels,
1265 .num_channels = ARRAY_SIZE(max11608_channels),
1266 },
1267 [max11610] = {
1268 .bits = 10,
1269 .int_vref_mv = 4098,
1270 .mode_list = max1238_mode_list,
1271 .num_modes = ARRAY_SIZE(max1238_mode_list),
1272 .default_mode = s0to11,
1273 .info = &max1238_info,
1274 .channels = max1238_channels,
1275 .num_channels = ARRAY_SIZE(max1238_channels),
1276 },
1277 [max11611] = {
1278 .bits = 10,
1279 .int_vref_mv = 2048,
1280 .mode_list = max1238_mode_list,
1281 .num_modes = ARRAY_SIZE(max1238_mode_list),
1282 .default_mode = s0to11,
1283 .info = &max1238_info,
1284 .channels = max1238_channels,
1285 .num_channels = ARRAY_SIZE(max1238_channels),
1286 },
1287 [max11612] = {
1288 .bits = 12,
1289 .int_vref_mv = 4096,
1290 .mode_list = max11607_mode_list,
1291 .num_modes = ARRAY_SIZE(max11607_mode_list),
1292 .default_mode = s0to3,
1293 .info = &max1238_info,
1294 .channels = max1363_channels,
1295 .num_channels = ARRAY_SIZE(max1363_channels),
1296 },
1297 [max11613] = {
1298 .bits = 12,
1299 .int_vref_mv = 2048,
1300 .mode_list = max11607_mode_list,
1301 .num_modes = ARRAY_SIZE(max11607_mode_list),
1302 .default_mode = s0to3,
1303 .info = &max1238_info,
1304 .channels = max1363_channels,
1305 .num_channels = ARRAY_SIZE(max1363_channels),
1306 },
1307 [max11614] = {
1308 .bits = 12,
1309 .int_vref_mv = 4096,
1310 .mode_list = max11608_mode_list,
1311 .num_modes = ARRAY_SIZE(max11608_mode_list),
1312 .default_mode = s0to7,
1313 .info = &max1238_info,
1314 .channels = max11614_channels,
1315 .num_channels = ARRAY_SIZE(max11614_channels),
1316 },
1317 [max11615] = {
1318 .bits = 12,
1319 .int_vref_mv = 2048,
1320 .mode_list = max11608_mode_list,
1321 .num_modes = ARRAY_SIZE(max11608_mode_list),
1322 .default_mode = s0to7,
1323 .info = &max1238_info,
1324 .channels = max11614_channels,
1325 .num_channels = ARRAY_SIZE(max11614_channels),
1326 },
1327 [max11616] = {
1328 .bits = 12,
1329 .int_vref_mv = 4098,
1330 .mode_list = max1238_mode_list,
1331 .num_modes = ARRAY_SIZE(max1238_mode_list),
1332 .default_mode = s0to11,
1333 .info = &max1238_info,
1334 .channels = max1238_channels,
1335 .num_channels = ARRAY_SIZE(max1238_channels),
1336 },
1337 [max11617] = {
1338 .bits = 12,
1339 .int_vref_mv = 2048,
1340 .mode_list = max1238_mode_list,
1341 .num_modes = ARRAY_SIZE(max1238_mode_list),
1342 .default_mode = s0to11,
1343 .info = &max1238_info,
1344 .channels = max1238_channels,
1345 .num_channels = ARRAY_SIZE(max1238_channels),
1346 },
1347 [max11644] = {
1348 .bits = 12,
1349 .int_vref_mv = 2048,
1350 .mode_list = max11644_mode_list,
1351 .num_modes = ARRAY_SIZE(max11644_mode_list),
1352 .default_mode = s0to1,
1353 .info = &max1238_info,
1354 .channels = max11644_channels,
1355 .num_channels = ARRAY_SIZE(max11644_channels),
1356 },
1357 [max11645] = {
1358 .bits = 12,
1359 .int_vref_mv = 4096,
1360 .mode_list = max11644_mode_list,
1361 .num_modes = ARRAY_SIZE(max11644_mode_list),
1362 .default_mode = s0to1,
1363 .info = &max1238_info,
1364 .channels = max11644_channels,
1365 .num_channels = ARRAY_SIZE(max11644_channels),
1366 },
1367 [max11646] = {
1368 .bits = 10,
1369 .int_vref_mv = 2048,
1370 .mode_list = max11644_mode_list,
1371 .num_modes = ARRAY_SIZE(max11644_mode_list),
1372 .default_mode = s0to1,
1373 .info = &max1238_info,
1374 .channels = max11646_channels,
1375 .num_channels = ARRAY_SIZE(max11646_channels),
1376 },
1377 [max11647] = {
1378 .bits = 10,
1379 .int_vref_mv = 4096,
1380 .mode_list = max11644_mode_list,
1381 .num_modes = ARRAY_SIZE(max11644_mode_list),
1382 .default_mode = s0to1,
1383 .info = &max1238_info,
1384 .channels = max11646_channels,
1385 .num_channels = ARRAY_SIZE(max11646_channels),
1386 },
1387 };
1388
1389 static int max1363_initial_setup(struct max1363_state *st)
1390 {
1391 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1392 | MAX1363_SETUP_POWER_UP_INT_REF
1393 | MAX1363_SETUP_INT_CLOCK
1394 | MAX1363_SETUP_UNIPOLAR
1395 | MAX1363_SETUP_NORESET;
1396
1397 /* Set scan mode writes the config anyway so wait until then*/
1398 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1399 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1400 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1401
1402 return max1363_set_scan_mode(st);
1403 }
1404
1405 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1406 {
1407 struct max1363_state *st = iio_priv(indio_dev);
1408 unsigned long *masks;
1409 int i;
1410
1411 masks = kzalloc(BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*sizeof(long)*
1412 (st->chip_info->num_modes + 1), GFP_KERNEL);
1413 if (!masks)
1414 return -ENOMEM;
1415
1416 for (i = 0; i < st->chip_info->num_modes; i++)
1417 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1418 max1363_mode_table[st->chip_info->mode_list[i]]
1419 .modemask, MAX1363_MAX_CHANNELS);
1420
1421 indio_dev->available_scan_masks = masks;
1422
1423 return 0;
1424 }
1425
1426
1427 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1428 {
1429 struct iio_poll_func *pf = p;
1430 struct iio_dev *indio_dev = pf->indio_dev;
1431 struct max1363_state *st = iio_priv(indio_dev);
1432 s64 time_ns;
1433 __u8 *rxbuf;
1434 int b_sent;
1435 size_t d_size;
1436 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1437 MAX1363_MAX_CHANNELS);
1438
1439 /* Ensure the timestamp is 8 byte aligned */
1440 if (st->chip_info->bits != 8)
1441 d_size = numvals*2;
1442 else
1443 d_size = numvals;
1444 if (indio_dev->scan_timestamp) {
1445 d_size += sizeof(s64);
1446 if (d_size % sizeof(s64))
1447 d_size += sizeof(s64) - (d_size % sizeof(s64));
1448 }
1449 /* Monitor mode prevents reading. Whilst not currently implemented
1450 * might as well have this test in here in the meantime as it does
1451 * no harm.
1452 */
1453 if (numvals == 0)
1454 goto done;
1455
1456 rxbuf = kmalloc(d_size, GFP_KERNEL);
1457 if (rxbuf == NULL)
1458 goto done;
1459 if (st->chip_info->bits != 8)
1460 b_sent = i2c_master_recv(st->client, rxbuf, numvals*2);
1461 else
1462 b_sent = i2c_master_recv(st->client, rxbuf, numvals);
1463 if (b_sent < 0)
1464 goto done_free;
1465
1466 time_ns = iio_get_time_ns();
1467
1468 if (indio_dev->scan_timestamp)
1469 memcpy(rxbuf + d_size - sizeof(s64), &time_ns, sizeof(time_ns));
1470 iio_push_to_buffers(indio_dev, rxbuf);
1471
1472 done_free:
1473 kfree(rxbuf);
1474 done:
1475 iio_trigger_notify_done(indio_dev->trig);
1476
1477 return IRQ_HANDLED;
1478 }
1479
1480 static const struct iio_buffer_setup_ops max1363_buffered_setup_ops = {
1481 .postenable = &iio_triggered_buffer_postenable,
1482 .preenable = &iio_sw_buffer_preenable,
1483 .predisable = &iio_triggered_buffer_predisable,
1484 };
1485
1486 static int max1363_register_buffered_funcs_and_init(struct iio_dev *indio_dev)
1487 {
1488 struct max1363_state *st = iio_priv(indio_dev);
1489 int ret = 0;
1490
1491 indio_dev->buffer = iio_kfifo_allocate(indio_dev);
1492 if (!indio_dev->buffer) {
1493 ret = -ENOMEM;
1494 goto error_ret;
1495 }
1496 indio_dev->pollfunc = iio_alloc_pollfunc(NULL,
1497 &max1363_trigger_handler,
1498 IRQF_ONESHOT,
1499 indio_dev,
1500 "%s_consumer%d",
1501 st->client->name,
1502 indio_dev->id);
1503 if (indio_dev->pollfunc == NULL) {
1504 ret = -ENOMEM;
1505 goto error_deallocate_sw_rb;
1506 }
1507 /* Buffer functions - here trigger setup related */
1508 indio_dev->setup_ops = &max1363_buffered_setup_ops;
1509
1510 /* Flag that polled buffering is possible */
1511 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
1512
1513 return 0;
1514
1515 error_deallocate_sw_rb:
1516 iio_kfifo_free(indio_dev->buffer);
1517 error_ret:
1518 return ret;
1519 }
1520
1521 static void max1363_buffer_cleanup(struct iio_dev *indio_dev)
1522 {
1523 /* ensure that the trigger has been detached */
1524 iio_dealloc_pollfunc(indio_dev->pollfunc);
1525 iio_kfifo_free(indio_dev->buffer);
1526 }
1527
1528 static int max1363_probe(struct i2c_client *client,
1529 const struct i2c_device_id *id)
1530 {
1531 int ret;
1532 struct max1363_state *st;
1533 struct iio_dev *indio_dev;
1534
1535 indio_dev = iio_device_alloc(sizeof(struct max1363_state));
1536 if (indio_dev == NULL) {
1537 ret = -ENOMEM;
1538 goto error_out;
1539 }
1540
1541 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1542 if (ret < 0)
1543 goto error_free_device;
1544
1545 st = iio_priv(indio_dev);
1546
1547 st->reg = regulator_get(&client->dev, "vcc");
1548 if (IS_ERR(st->reg)) {
1549 ret = PTR_ERR(st->reg);
1550 goto error_unregister_map;
1551 }
1552
1553 ret = regulator_enable(st->reg);
1554 if (ret)
1555 goto error_put_reg;
1556
1557 /* this is only used for device removal purposes */
1558 i2c_set_clientdata(client, indio_dev);
1559
1560 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1561 st->client = client;
1562
1563 ret = max1363_alloc_scan_masks(indio_dev);
1564 if (ret)
1565 goto error_disable_reg;
1566
1567 /* Estabilish that the iio_dev is a child of the i2c device */
1568 indio_dev->dev.parent = &client->dev;
1569 indio_dev->name = id->name;
1570 indio_dev->channels = st->chip_info->channels;
1571 indio_dev->num_channels = st->chip_info->num_channels;
1572 indio_dev->info = st->chip_info->info;
1573 indio_dev->modes = INDIO_DIRECT_MODE;
1574 indio_dev->channels = st->chip_info->channels;
1575 indio_dev->num_channels = st->chip_info->num_channels;
1576 ret = max1363_initial_setup(st);
1577 if (ret < 0)
1578 goto error_free_available_scan_masks;
1579
1580 ret = max1363_register_buffered_funcs_and_init(indio_dev);
1581 if (ret)
1582 goto error_free_available_scan_masks;
1583
1584 ret = iio_buffer_register(indio_dev,
1585 st->chip_info->channels,
1586 st->chip_info->num_channels);
1587 if (ret)
1588 goto error_cleanup_buffer;
1589
1590 if (client->irq) {
1591 ret = request_threaded_irq(st->client->irq,
1592 NULL,
1593 &max1363_event_handler,
1594 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1595 "max1363_event",
1596 indio_dev);
1597
1598 if (ret)
1599 goto error_uninit_buffer;
1600 }
1601
1602 ret = iio_device_register(indio_dev);
1603 if (ret < 0)
1604 goto error_free_irq;
1605
1606 return 0;
1607 error_free_irq:
1608 if (client->irq)
1609 free_irq(st->client->irq, indio_dev);
1610 error_uninit_buffer:
1611 iio_buffer_unregister(indio_dev);
1612 error_cleanup_buffer:
1613 max1363_buffer_cleanup(indio_dev);
1614 error_free_available_scan_masks:
1615 kfree(indio_dev->available_scan_masks);
1616 error_disable_reg:
1617 regulator_disable(st->reg);
1618 error_put_reg:
1619 regulator_put(st->reg);
1620 error_unregister_map:
1621 iio_map_array_unregister(indio_dev, client->dev.platform_data);
1622 error_free_device:
1623 iio_device_free(indio_dev);
1624 error_out:
1625 return ret;
1626 }
1627
1628 static int max1363_remove(struct i2c_client *client)
1629 {
1630 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1631 struct max1363_state *st = iio_priv(indio_dev);
1632
1633 iio_device_unregister(indio_dev);
1634 if (client->irq)
1635 free_irq(st->client->irq, indio_dev);
1636 iio_buffer_unregister(indio_dev);
1637 max1363_buffer_cleanup(indio_dev);
1638 kfree(indio_dev->available_scan_masks);
1639 regulator_disable(st->reg);
1640 regulator_put(st->reg);
1641 iio_map_array_unregister(indio_dev, client->dev.platform_data);
1642 iio_device_free(indio_dev);
1643
1644 return 0;
1645 }
1646
1647 static const struct i2c_device_id max1363_id[] = {
1648 { "max1361", max1361 },
1649 { "max1362", max1362 },
1650 { "max1363", max1363 },
1651 { "max1364", max1364 },
1652 { "max1036", max1036 },
1653 { "max1037", max1037 },
1654 { "max1038", max1038 },
1655 { "max1039", max1039 },
1656 { "max1136", max1136 },
1657 { "max1137", max1137 },
1658 { "max1138", max1138 },
1659 { "max1139", max1139 },
1660 { "max1236", max1236 },
1661 { "max1237", max1237 },
1662 { "max1238", max1238 },
1663 { "max1239", max1239 },
1664 { "max11600", max11600 },
1665 { "max11601", max11601 },
1666 { "max11602", max11602 },
1667 { "max11603", max11603 },
1668 { "max11604", max11604 },
1669 { "max11605", max11605 },
1670 { "max11606", max11606 },
1671 { "max11607", max11607 },
1672 { "max11608", max11608 },
1673 { "max11609", max11609 },
1674 { "max11610", max11610 },
1675 { "max11611", max11611 },
1676 { "max11612", max11612 },
1677 { "max11613", max11613 },
1678 { "max11614", max11614 },
1679 { "max11615", max11615 },
1680 { "max11616", max11616 },
1681 { "max11617", max11617 },
1682 {}
1683 };
1684
1685 MODULE_DEVICE_TABLE(i2c, max1363_id);
1686
1687 static struct i2c_driver max1363_driver = {
1688 .driver = {
1689 .name = "max1363",
1690 },
1691 .probe = max1363_probe,
1692 .remove = max1363_remove,
1693 .id_table = max1363_id,
1694 };
1695 module_i2c_driver(max1363_driver);
1696
1697 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1698 MODULE_DESCRIPTION("Maxim 1363 ADC");
1699 MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)