Merge branch 'dmaengine' into async-tx-next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / qd65xx.c
1 /*
2 * Copyright (C) 1996-2001 Linus Torvalds & author (see below)
3 */
4
5 /*
6 * Version 0.03 Cleaned auto-tune, added probe
7 * Version 0.04 Added second channel tuning
8 * Version 0.05 Enhanced tuning ; added qd6500 support
9 * Version 0.06 Added dos driver's list
10 * Version 0.07 Second channel bug fix
11 *
12 * QDI QD6500/QD6580 EIDE controller fast support
13 *
14 * To activate controller support, use "ide0=qd65xx"
15 */
16
17 /*
18 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
19 * Samuel Thibault <samuel.thibault@ens-lyon.org>
20 */
21
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/timer.h>
27 #include <linux/mm.h>
28 #include <linux/ioport.h>
29 #include <linux/blkdev.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
32 #include <asm/system.h>
33 #include <asm/io.h>
34
35 #define DRV_NAME "qd65xx"
36
37 #include "qd65xx.h"
38
39 /*
40 * I/O ports are 0x30-0x31 (and 0x32-0x33 for qd6580)
41 * or 0xb0-0xb1 (and 0xb2-0xb3 for qd6580)
42 * -- qd6500 is a single IDE interface
43 * -- qd6580 is a dual IDE interface
44 *
45 * More research on qd6580 being done by willmore@cig.mot.com (David)
46 * More Information given by Petr Soucek (petr@ryston.cz)
47 * http://www.ryston.cz/petr/vlb
48 */
49
50 /*
51 * base: Timer1
52 *
53 *
54 * base+0x01: Config (R/O)
55 *
56 * bit 0: ide baseport: 1 = 0x1f0 ; 0 = 0x170 (only useful for qd6500)
57 * bit 1: qd65xx baseport: 1 = 0xb0 ; 0 = 0x30
58 * bit 2: ID3: bus speed: 1 = <=33MHz ; 0 = >33MHz
59 * bit 3: qd6500: 1 = disabled, 0 = enabled
60 * qd6580: 1
61 * upper nibble:
62 * qd6500: 1100
63 * qd6580: either 1010 or 0101
64 *
65 *
66 * base+0x02: Timer2 (qd6580 only)
67 *
68 *
69 * base+0x03: Control (qd6580 only)
70 *
71 * bits 0-3 must always be set 1
72 * bit 4 must be set 1, but is set 0 by dos driver while measuring vlb clock
73 * bit 0 : 1 = Only primary port enabled : channel 0 for hda, channel 1 for hdb
74 * 0 = Primary and Secondary ports enabled : channel 0 for hda & hdb
75 * channel 1 for hdc & hdd
76 * bit 1 : 1 = only disks on primary port
77 * 0 = disks & ATAPI devices on primary port
78 * bit 2-4 : always 0
79 * bit 5 : status, but of what ?
80 * bit 6 : always set 1 by dos driver
81 * bit 7 : set 1 for non-ATAPI devices on primary port
82 * (maybe read-ahead and post-write buffer ?)
83 */
84
85 static int timings[4]={-1,-1,-1,-1}; /* stores current timing for each timer */
86
87 /*
88 * qd65xx_select:
89 *
90 * This routine is invoked to prepare for access to a given drive.
91 */
92
93 static void qd65xx_dev_select(ide_drive_t *drive)
94 {
95 u8 index = (( (QD_TIMREG(drive)) & 0x80 ) >> 7) |
96 (QD_TIMREG(drive) & 0x02);
97
98 if (timings[index] != QD_TIMING(drive))
99 outb(timings[index] = QD_TIMING(drive), QD_TIMREG(drive));
100
101 outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
102 }
103
104 /*
105 * qd6500_compute_timing
106 *
107 * computes the timing value where
108 * lower nibble represents active time, in count of VLB clocks
109 * upper nibble represents recovery time, in count of VLB clocks
110 */
111
112 static u8 qd6500_compute_timing (ide_hwif_t *hwif, int active_time, int recovery_time)
113 {
114 int clk = ide_vlb_clk ? ide_vlb_clk : 50;
115 u8 act_cyc, rec_cyc;
116
117 if (clk <= 33) {
118 act_cyc = 9 - IDE_IN(active_time * clk / 1000 + 1, 2, 9);
119 rec_cyc = 15 - IDE_IN(recovery_time * clk / 1000 + 1, 0, 15);
120 } else {
121 act_cyc = 8 - IDE_IN(active_time * clk / 1000 + 1, 1, 8);
122 rec_cyc = 18 - IDE_IN(recovery_time * clk / 1000 + 1, 3, 18);
123 }
124
125 return (rec_cyc << 4) | 0x08 | act_cyc;
126 }
127
128 /*
129 * qd6580_compute_timing
130 *
131 * idem for qd6580
132 */
133
134 static u8 qd6580_compute_timing (int active_time, int recovery_time)
135 {
136 int clk = ide_vlb_clk ? ide_vlb_clk : 50;
137 u8 act_cyc, rec_cyc;
138
139 act_cyc = 17 - IDE_IN(active_time * clk / 1000 + 1, 2, 17);
140 rec_cyc = 15 - IDE_IN(recovery_time * clk / 1000 + 1, 2, 15);
141
142 return (rec_cyc << 4) | act_cyc;
143 }
144
145 /*
146 * qd_find_disk_type
147 *
148 * tries to find timing from dos driver's table
149 */
150
151 static int qd_find_disk_type (ide_drive_t *drive,
152 int *active_time, int *recovery_time)
153 {
154 struct qd65xx_timing_s *p;
155 char *m = (char *)&drive->id[ATA_ID_PROD];
156 char model[ATA_ID_PROD_LEN];
157
158 if (*m == 0)
159 return 0;
160
161 strncpy(model, m, ATA_ID_PROD_LEN);
162 ide_fixstring(model, ATA_ID_PROD_LEN, 1); /* byte-swap */
163
164 for (p = qd65xx_timing ; p->offset != -1 ; p++) {
165 if (!strncmp(p->model, model+p->offset, 4)) {
166 printk(KERN_DEBUG "%s: listed !\n", drive->name);
167 *active_time = p->active;
168 *recovery_time = p->recovery;
169 return 1;
170 }
171 }
172 return 0;
173 }
174
175 /*
176 * qd_set_timing:
177 *
178 * records the timing
179 */
180
181 static void qd_set_timing (ide_drive_t *drive, u8 timing)
182 {
183 unsigned long data = (unsigned long)ide_get_drivedata(drive);
184
185 data &= 0xff00;
186 data |= timing;
187 ide_set_drivedata(drive, (void *)data);
188
189 printk(KERN_DEBUG "%s: %#x\n", drive->name, timing);
190 }
191
192 static void qd6500_set_pio_mode(ide_drive_t *drive, const u8 pio)
193 {
194 u16 *id = drive->id;
195 int active_time = 175;
196 int recovery_time = 415; /* worst case values from the dos driver */
197
198 /*
199 * FIXME: use "pio" value
200 */
201 if (!qd_find_disk_type(drive, &active_time, &recovery_time) &&
202 (id[ATA_ID_OLD_PIO_MODES] & 0xff) && (id[ATA_ID_FIELD_VALID] & 2) &&
203 id[ATA_ID_EIDE_PIO] >= 240) {
204 printk(KERN_INFO "%s: PIO mode%d\n", drive->name,
205 id[ATA_ID_OLD_PIO_MODES] & 0xff);
206 active_time = 110;
207 recovery_time = drive->id[ATA_ID_EIDE_PIO] - 120;
208 }
209
210 qd_set_timing(drive, qd6500_compute_timing(drive->hwif,
211 active_time, recovery_time));
212 }
213
214 static void qd6580_set_pio_mode(ide_drive_t *drive, const u8 pio)
215 {
216 ide_hwif_t *hwif = drive->hwif;
217 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
218 unsigned int cycle_time;
219 int active_time = 175;
220 int recovery_time = 415; /* worst case values from the dos driver */
221 u8 base = (hwif->config_data & 0xff00) >> 8;
222
223 if (drive->id && !qd_find_disk_type(drive, &active_time, &recovery_time)) {
224 cycle_time = ide_pio_cycle_time(drive, pio);
225
226 switch (pio) {
227 case 0: break;
228 case 3:
229 if (cycle_time >= 110) {
230 active_time = 86;
231 recovery_time = cycle_time - 102;
232 } else
233 printk(KERN_WARNING "%s: Strange recovery time !\n",drive->name);
234 break;
235 case 4:
236 if (cycle_time >= 69) {
237 active_time = 70;
238 recovery_time = cycle_time - 61;
239 } else
240 printk(KERN_WARNING "%s: Strange recovery time !\n",drive->name);
241 break;
242 default:
243 if (cycle_time >= 180) {
244 active_time = 110;
245 recovery_time = cycle_time - 120;
246 } else {
247 active_time = t->active;
248 recovery_time = cycle_time - active_time;
249 }
250 }
251 printk(KERN_INFO "%s: PIO mode%d\n", drive->name,pio);
252 }
253
254 if (!hwif->channel && drive->media != ide_disk) {
255 outb(0x5f, QD_CONTROL_PORT);
256 printk(KERN_WARNING "%s: ATAPI: disabled read-ahead FIFO "
257 "and post-write buffer on %s.\n",
258 drive->name, hwif->name);
259 }
260
261 qd_set_timing(drive, qd6580_compute_timing(active_time, recovery_time));
262 }
263
264 /*
265 * qd_testreg
266 *
267 * tests if the given port is a register
268 */
269
270 static int __init qd_testreg(int port)
271 {
272 unsigned long flags;
273 u8 savereg, readreg;
274
275 local_irq_save(flags);
276 savereg = inb_p(port);
277 outb_p(QD_TESTVAL, port); /* safe value */
278 readreg = inb_p(port);
279 outb(savereg, port);
280 local_irq_restore(flags);
281
282 if (savereg == QD_TESTVAL) {
283 printk(KERN_ERR "Outch ! the probe for qd65xx isn't reliable !\n");
284 printk(KERN_ERR "Please contact maintainers to tell about your hardware\n");
285 printk(KERN_ERR "Assuming qd65xx is not present.\n");
286 return 1;
287 }
288
289 return (readreg != QD_TESTVAL);
290 }
291
292 static void __init qd6500_init_dev(ide_drive_t *drive)
293 {
294 ide_hwif_t *hwif = drive->hwif;
295 u8 base = (hwif->config_data & 0xff00) >> 8;
296 u8 config = QD_CONFIG(hwif);
297
298 ide_set_drivedata(drive, (void *)QD6500_DEF_DATA);
299 }
300
301 static void __init qd6580_init_dev(ide_drive_t *drive)
302 {
303 ide_hwif_t *hwif = drive->hwif;
304 u16 t1, t2;
305 u8 base = (hwif->config_data & 0xff00) >> 8;
306 u8 config = QD_CONFIG(hwif);
307
308 if (hwif->host_flags & IDE_HFLAG_SINGLE) {
309 t1 = QD6580_DEF_DATA;
310 t2 = QD6580_DEF_DATA2;
311 } else
312 t2 = t1 = hwif->channel ? QD6580_DEF_DATA2 : QD6580_DEF_DATA;
313
314 ide_set_drivedata(drive, (void *)((drive->dn & 1) ? t2 : t1));
315 }
316
317 static const struct ide_tp_ops qd65xx_tp_ops = {
318 .exec_command = ide_exec_command,
319 .read_status = ide_read_status,
320 .read_altstatus = ide_read_altstatus,
321 .write_devctl = ide_write_devctl,
322
323 .dev_select = qd65xx_dev_select,
324 .tf_load = ide_tf_load,
325 .tf_read = ide_tf_read,
326
327 .input_data = ide_input_data,
328 .output_data = ide_output_data,
329 };
330
331 static const struct ide_port_ops qd6500_port_ops = {
332 .init_dev = qd6500_init_dev,
333 .set_pio_mode = qd6500_set_pio_mode,
334 };
335
336 static const struct ide_port_ops qd6580_port_ops = {
337 .init_dev = qd6580_init_dev,
338 .set_pio_mode = qd6580_set_pio_mode,
339 };
340
341 static const struct ide_port_info qd65xx_port_info __initdata = {
342 .name = DRV_NAME,
343 .tp_ops = &qd65xx_tp_ops,
344 .chipset = ide_qd65xx,
345 .host_flags = IDE_HFLAG_IO_32BIT |
346 IDE_HFLAG_NO_DMA,
347 .pio_mask = ATA_PIO4,
348 };
349
350 /*
351 * qd_probe:
352 *
353 * looks at the specified baseport, and if qd found, registers & initialises it
354 * return 1 if another qd may be probed
355 */
356
357 static int __init qd_probe(int base)
358 {
359 int rc;
360 u8 config, unit, control;
361 struct ide_port_info d = qd65xx_port_info;
362
363 config = inb(QD_CONFIG_PORT);
364
365 if (! ((config & QD_CONFIG_BASEPORT) >> 1 == (base == 0xb0)) )
366 return -ENODEV;
367
368 unit = ! (config & QD_CONFIG_IDE_BASEPORT);
369
370 if (unit)
371 d.host_flags |= IDE_HFLAG_QD_2ND_PORT;
372
373 switch (config & 0xf0) {
374 case QD_CONFIG_QD6500:
375 if (qd_testreg(base))
376 return -ENODEV; /* bad register */
377
378 if (config & QD_CONFIG_DISABLED) {
379 printk(KERN_WARNING "qd6500 is disabled !\n");
380 return -ENODEV;
381 }
382
383 printk(KERN_NOTICE "qd6500 at %#x\n", base);
384 printk(KERN_DEBUG "qd6500: config=%#x, ID3=%u\n",
385 config, QD_ID3);
386
387 d.port_ops = &qd6500_port_ops;
388 d.host_flags |= IDE_HFLAG_SINGLE;
389 break;
390 case QD_CONFIG_QD6580_A:
391 case QD_CONFIG_QD6580_B:
392 if (qd_testreg(base) || qd_testreg(base + 0x02))
393 return -ENODEV; /* bad registers */
394
395 control = inb(QD_CONTROL_PORT);
396
397 printk(KERN_NOTICE "qd6580 at %#x\n", base);
398 printk(KERN_DEBUG "qd6580: config=%#x, control=%#x, ID3=%u\n",
399 config, control, QD_ID3);
400
401 outb(QD_DEF_CONTR, QD_CONTROL_PORT);
402
403 d.port_ops = &qd6580_port_ops;
404 if (control & QD_CONTR_SEC_DISABLED)
405 d.host_flags |= IDE_HFLAG_SINGLE;
406
407 printk(KERN_INFO "qd6580: %s IDE board\n",
408 (control & QD_CONTR_SEC_DISABLED) ? "single" : "dual");
409 break;
410 default:
411 return -ENODEV;
412 }
413
414 rc = ide_legacy_device_add(&d, (base << 8) | config);
415
416 if (d.host_flags & IDE_HFLAG_SINGLE)
417 return (rc == 0) ? 1 : rc;
418
419 return rc;
420 }
421
422 static int probe_qd65xx;
423
424 module_param_named(probe, probe_qd65xx, bool, 0);
425 MODULE_PARM_DESC(probe, "probe for QD65xx chipsets");
426
427 static int __init qd65xx_init(void)
428 {
429 int rc1, rc2 = -ENODEV;
430
431 if (probe_qd65xx == 0)
432 return -ENODEV;
433
434 rc1 = qd_probe(0x30);
435 if (rc1)
436 rc2 = qd_probe(0xb0);
437
438 if (rc1 < 0 && rc2 < 0)
439 return -ENODEV;
440
441 return 0;
442 }
443
444 module_init(qd65xx_init);
445
446 MODULE_AUTHOR("Samuel Thibault");
447 MODULE_DESCRIPTION("support of qd65xx vlb ide chipset");
448 MODULE_LICENSE("GPL");