drivers/ide/pci/trm290.c

   1 /*
   2  *  linux/drivers/ide/pci/trm290.c              Version 1.02    Mar. 18, 2000
   3  *
   4  *  Copyright (c) 1997-1998  Mark Lord
   5  *  May be copied or modified under the terms of the GNU General Public License
   6  *
   7  *  June 22, 2004 - get rid of check_region
   8  *                   - Jesper Juhl
   9  *
  10  */
  11
  12 /*
  13  * This module provides support for the bus-master IDE DMA function
  14  * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
  15  * including a "Precision Instruments" board.  The TRM290 pre-dates
  16  * the sff-8038 standard (ide-dma.c) by a few months, and differs
  17  * significantly enough to warrant separate routines for some functions,
  18  * while re-using others from ide-dma.c.
  19  *
  20  * EXPERIMENTAL!  It works for me (a sample of one).
  21  *
  22  * Works reliably for me in DMA mode (READs only),
  23  * DMA WRITEs are disabled by default (see #define below);
  24  *
  25  * DMA is not enabled automatically for this chipset,
  26  * but can be turned on manually (with "hdparm -d1") at run time.
  27  *
  28  * I need volunteers with "spare" drives for further testing
  29  * and development, and maybe to help figure out the peculiarities.
  30  * Even knowing the registers (below), some things behave strangely.
  31  */
  32
  33 #define TRM290_NO_DMA_WRITES    /* DMA writes seem unreliable sometimes */
  34
  35 /*
  36  * TRM-290 PCI-IDE2 Bus Master Chip
  37  * ================================
  38  * The configuration registers are addressed in normal I/O port space
  39  * and are used as follows:
  40  *
  41  * trm290_base depends on jumper settings, and is probed for by ide-dma.c
  42  *
  43  * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
  44  *      bit7 must always be written as "1"
  45  *      bits6-2 undefined
  46  *      bit1 1=legacy_compatible_mode, 0=native_pci_mode
  47  *      bit0 1=test_mode, 0=normal(default)
  48  *
  49  * trm290_base+2 when READ: status register (byte, read-only)
  50  *      bits7-2 undefined
  51  *      bit1 channel0 busmaster interrupt status 0=none, 1=asserted
  52  *      bit0 channel0 interrupt status 0=none, 1=asserted
  53  *
  54  * trm290_base+3 Interrupt mask register
  55  *      bits7-5 undefined
  56  *      bit4 legacy_header: 1=present, 0=absent
  57  *      bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
  58  *      bit2 channel1 interrupt status 0=none, 1=asserted (read only)
  59  *      bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
  60  *      bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
  61  *
  62  * trm290_base+1 "CPR" Config Pointer Register (byte)
  63  *      bit7 1=autoincrement CPR bits 2-0 after each access of CDR
  64  *      bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
  65  *      bit5 0=enabled master burst access (default), 1=disable  (write only)
  66  *      bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
  67  *      bit3 0=primary IDE channel, 1=secondary IDE channel
  68  *      bits2-0 register index for accesses through CDR port
  69  *
  70  * trm290_base+0 "CDR" Config Data Register (word)
  71  *      two sets of seven config registers,
  72  *      selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
  73  *      each index defined below:
  74  *
  75  * Index-0 Base address register for command block (word)
  76  *      defaults: 0x1f0 for primary, 0x170 for secondary
  77  *
  78  * Index-1 general config register (byte)
  79  *      bit7 1=DMA enable, 0=DMA disable
  80  *      bit6 1=activate IDE_RESET, 0=no action (default)
  81  *      bit5 1=enable IORDY, 0=disable IORDY (default)
  82  *      bit4 0=16-bit data port(default), 1=8-bit (XT) data port
  83  *      bit3 interrupt polarity: 1=active_low, 0=active_high(default)
  84  *      bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
  85  *      bit1 bus_master_mode(?): 1=enable, 0=disable(default)
  86  *      bit0 enable_io_ports: 1=enable(default), 0=disable
  87  *
  88  * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
  89  *      bits7-0 bits7-0 of readahead count
  90  *
  91  * Index-3 read-ahead config register (byte, write only)
  92  *      bit7 1=enable_readahead, 0=disable_readahead(default)
  93  *      bit6 1=clear_FIFO, 0=no_action
  94  *      bit5 undefined
  95  *      bit4 mode4 timing control: 1=enable, 0=disable(default)
  96  *      bit3 undefined
  97  *      bit2 undefined
  98  *      bits1-0 bits9-8 of read-ahead count
  99  *
 100  * Index-4 base address register for control block (word)
 101  *      defaults: 0x3f6 for primary, 0x376 for secondary
 102  *
 103  * Index-5 data port timings (shared by both drives) (byte)
 104  *      standard PCI "clk" (clock) counts, default value = 0xf5
 105  *
 106  *      bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
 107  *      bits5-3 hold time:      000=1clk, 001=2clk, 010=3clk,
 108  *                              011=4clk, 100=5clk, 101=6clk,
 109  *                              110=8clk, 111=12clk
 110  *      bits2-0 active time:    000=2clk, 001=3clk, 010=4clk,
 111  *                              011=5clk, 100=6clk, 101=8clk,
 112  *                              110=12clk, 111=16clk
 113  *
 114  * Index-6 command/control port timings (shared by both drives) (byte)
 115  *      same layout as Index-5, default value = 0xde
 116  *
 117  * Suggested CDR programming for PIO mode0 (600ns):
 118  *      0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde  ; primary
 119  *      0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde  ; secondary
 120  *
 121  * Suggested CDR programming for PIO mode3 (180ns):
 122  *      0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde  ; primary
 123  *      0x0170,0x21,0xff,0x80,0x0376,0x09,0xde  ; secondary
 124  *
 125  * Suggested CDR programming for PIO mode4 (120ns):
 126  *      0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde  ; primary
 127  *      0x0170,0x21,0xff,0x80,0x0376,0x00,0xde  ; secondary
 128  *
 129  */
 130
 131 #include <linux/types.h>
 132 #include <linux/module.h>
 133 #include <linux/kernel.h>
 134 #include <linux/mm.h>
 135 #include <linux/ioport.h>
 136 #include <linux/interrupt.h>
 137 #include <linux/blkdev.h>
 138 #include <linux/init.h>
 139 #include <linux/hdreg.h>
 140 #include <linux/pci.h>
 141 #include <linux/delay.h>
 142 #include <linux/ide.h>
 143
 144 #include <asm/io.h>
 145
 146 static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
 147 {
 148         ide_hwif_t *hwif = HWIF(drive);
 149         u16 reg = 0;
 150         unsigned long flags;
 151
 152         /* select PIO or DMA */
 153         reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
 154
 155         local_irq_save(flags);
 156
 157         if (reg != hwif->select_data) {
 158                 hwif->select_data = reg;
 159                 /* set PIO/DMA */
 160                 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
 161                 hwif->OUTW(reg & 0xff, hwif->config_data);
 162         }
 163
 164         /* enable IRQ if not probing */
 165         if (drive->present) {
 166                 reg = hwif->INW(hwif->config_data + 3);
 167                 reg &= 0x13;
 168                 reg &= ~(1 << hwif->channel);
 169                 hwif->OUTW(reg, hwif->config_data+3);
 170         }
 171
 172         local_irq_restore(flags);
 173 }
 174
 175 static void trm290_selectproc (ide_drive_t *drive)
 176 {
 177         trm290_prepare_drive(drive, drive->using_dma);
 178 }
 179
 180 #ifdef CONFIG_BLK_DEV_IDEDMA
 181 static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 182 {
 183         ide_hwif_t *hwif        = HWIF(drive);
 184
 185         BUG_ON(HWGROUP(drive)->handler != NULL);        /* paranoia check */
 186         ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
 187         /* issue cmd to drive */
 188         hwif->OUTB(command, IDE_COMMAND_REG);
 189 }
 190
 191 static int trm290_ide_dma_setup(ide_drive_t *drive)
 192 {
 193         ide_hwif_t *hwif = drive->hwif;
 194         struct request *rq = hwif->hwgroup->rq;
 195         unsigned int count, rw;
 196
 197         if (rq_data_dir(rq)) {
 198 #ifdef TRM290_NO_DMA_WRITES
 199                 /* always use PIO for writes */
 200                 trm290_prepare_drive(drive, 0); /* select PIO xfer */
 201                 return 1;
 202 #endif
 203                 rw = 1;
 204         } else
 205                 rw = 2;
 206
 207         if (!(count = ide_build_dmatable(drive, rq))) {
 208                 /* try PIO instead of DMA */
 209                 trm290_prepare_drive(drive, 0); /* select PIO xfer */
 210                 return 1;
 211         }
 212         /* select DMA xfer */
 213         trm290_prepare_drive(drive, 1);
 214         hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command);
 215         drive->waiting_for_dma = 1;
 216         /* start DMA */
 217         hwif->OUTW((count * 2) - 1, hwif->dma_status);
 218         return 0;
 219 }
 220
 221 static void trm290_ide_dma_start(ide_drive_t *drive)
 222 {
 223 }
 224
 225 static int trm290_ide_dma_end (ide_drive_t *drive)
 226 {
 227         ide_hwif_t *hwif = HWIF(drive);
 228         u16 status = 0;
 229
 230         drive->waiting_for_dma = 0;
 231         /* purge DMA mappings */
 232         ide_destroy_dmatable(drive);
 233         status = hwif->INW(hwif->dma_status);
 234         return (status != 0x00ff);
 235 }
 236
 237 static int trm290_ide_dma_test_irq (ide_drive_t *drive)
 238 {
 239         ide_hwif_t *hwif = HWIF(drive);
 240         u16 status = 0;
 241
 242         status = hwif->INW(hwif->dma_status);
 243         return (status == 0x00ff);
 244 }
 245 #endif /* CONFIG_BLK_DEV_IDEDMA */
 246
 247 /*
 248  * Invoked from ide-dma.c at boot time.
 249  */
 250 static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
 251 {
 252         unsigned int cfgbase = 0;
 253         unsigned long flags;
 254         u8 reg = 0;
 255         struct pci_dev *dev = hwif->pci_dev;
 256
 257         hwif->no_lba48 = 1;
 258         hwif->chipset = ide_trm290;
 259         cfgbase = pci_resource_start(dev, 4);
 260         if ((dev->class & 5) && cfgbase) {
 261                 hwif->config_data = cfgbase;
 262                 printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
 263                         hwif->config_data);
 264         } else {
 265                 hwif->config_data = 0x3df0;
 266                 printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
 267                         hwif->config_data);
 268         }
 269
 270         local_irq_save(flags);
 271         /* put config reg into first byte of hwif->select_data */
 272         hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
 273         /* select PIO as default */
 274         hwif->select_data = 0x21;
 275         hwif->OUTB(hwif->select_data, hwif->config_data);
 276         /* get IRQ info */
 277         reg = hwif->INB(hwif->config_data+3);
 278         /* mask IRQs for both ports */
 279         reg = (reg & 0x10) | 0x03;
 280         hwif->OUTB(reg, hwif->config_data+3);
 281         local_irq_restore(flags);
 282
 283         if ((reg & 0x10))
 284                 /* legacy mode */
 285                 hwif->irq = hwif->channel ? 15 : 14;
 286         else if (!hwif->irq && hwif->mate && hwif->mate->irq)
 287                 /* sharing IRQ with mate */
 288                 hwif->irq = hwif->mate->irq;
 289
 290         ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
 291
 292 #ifdef CONFIG_BLK_DEV_IDEDMA
 293         hwif->dma_setup = &trm290_ide_dma_setup;
 294         hwif->dma_exec_cmd = &trm290_ide_dma_exec_cmd;
 295         hwif->dma_start = &trm290_ide_dma_start;
 296         hwif->ide_dma_end = &trm290_ide_dma_end;
 297         hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
 298 #endif /* CONFIG_BLK_DEV_IDEDMA */
 299
 300         hwif->selectproc = &trm290_selectproc;
 301         hwif->autodma = 0;              /* play it safe for now */
 302         hwif->drives[0].autodma = hwif->autodma;
 303         hwif->drives[1].autodma = hwif->autodma;
 304 #if 1
 305         {
 306         /*
 307          * My trm290-based card doesn't seem to work with all possible values
 308          * for the control basereg, so this kludge ensures that we use only
 309          * values that are known to work.  Ugh.         -ml
 310          */
 311                 u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
 312                 static u16 next_offset = 0;
 313                 u8 old_mask;
 314
 315                 hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
 316                 old = hwif->INW(hwif->config_data);
 317                 old &= ~1;
 318                 old_mask = hwif->INB(old+2);
 319                 if (old != compat && old_mask == 0xff) {
 320                         /* leave lower 10 bits untouched */
 321                         compat += (next_offset += 0x400);
 322                         hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
 323                         hwif->OUTW(compat|1, hwif->config_data);
 324                         new = hwif->INW(hwif->config_data);
 325                         printk(KERN_INFO "%s: control basereg workaround: "
 326                                 "old=0x%04x, new=0x%04x\n",
 327                                 hwif->name, old, new & ~1);
 328                 }
 329         }
 330 #endif
 331 }
 332
 333 static ide_pci_device_t trm290_chipset __devinitdata = {
 334         .name           = "TRM290",
 335         .init_hwif      = init_hwif_trm290,
 336         .channels       = 2,
 337         .autodma        = NOAUTODMA,
 338         .bootable       = ON_BOARD,
 339 };
 340
 341 static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 342 {
 343         return ide_setup_pci_device(dev, &trm290_chipset);
 344 }
 345
 346 static struct pci_device_id trm290_pci_tbl[] = {
 347         { PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 348         { 0, },
 349 };
 350 MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
 351
 352 static struct pci_driver driver = {
 353         .name           = "TRM290_IDE",
 354         .id_table       = trm290_pci_tbl,
 355         .probe          = trm290_init_one,
 356 };
 357
 358 static int __init trm290_ide_init(void)
 359 {
 360         return ide_pci_register_driver(&driver);
 361 }
 362
 363 module_init(trm290_ide_init);
 364
 365 MODULE_AUTHOR("Mark Lord");
 366 MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
 367 MODULE_LICENSE("GPL");