2 * linux/drivers/ide/pci/siimage.c Version 1.19 Nov 16 2007
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
6 * Copyright (C) 2007 MontaVista Software, Inc.
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
9 * May be copied or modified under the terms of the GNU General Public License
11 * Documentation for CMD680:
12 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
14 * Documentation for SiI 3112:
15 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
17 * Errata and other documentation only available under NDA.
21 * If you are using Marvell SATA-IDE adapters with Maxtor drives
22 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
24 * If you are using WD drives with SATA bridges you must set the
25 * drive to "Single". "Master" will hang
27 * If you have strange problems with nVidia chipset systems please
28 * see the SI support documentation and update your system BIOS
31 * The Dell DRAC4 has some interesting features including effectively hot
32 * unplugging/replugging the virtual CD interface when the DRAC is reset.
33 * This often causes drivers/ide/siimage to panic but is ok with the rather
34 * smarter code in libata.
41 #include <linux/types.h>
42 #include <linux/module.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/hdreg.h>
46 #include <linux/ide.h>
47 #include <linux/init.h>
52 * pdev_is_sata - check if device is SATA
53 * @pdev: PCI device to check
55 * Returns true if this is a SATA controller
58 static int pdev_is_sata(struct pci_dev
*pdev
)
60 #ifdef CONFIG_BLK_DEV_IDE_SATA
61 switch(pdev
->device
) {
62 case PCI_DEVICE_ID_SII_3112
:
63 case PCI_DEVICE_ID_SII_1210SA
:
65 case PCI_DEVICE_ID_SII_680
:
74 * is_sata - check if hwif is SATA
75 * @hwif: interface to check
77 * Returns true if this is a SATA controller
80 static inline int is_sata(ide_hwif_t
*hwif
)
82 return pdev_is_sata(hwif
->pci_dev
);
86 * siimage_selreg - return register base
90 * Turn a config register offset into the right address in either
91 * PCI space or MMIO space to access the control register in question
92 * Thankfully this is a configuration operation so isnt performance
96 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
98 unsigned long base
= (unsigned long)hwif
->hwif_data
;
101 base
+= (hwif
->channel
<< 6);
103 base
+= (hwif
->channel
<< 4);
108 * siimage_seldev - return register base
112 * Turn a config register offset into the right address in either
113 * PCI space or MMIO space to access the control register in question
114 * including accounting for the unit shift.
117 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
119 ide_hwif_t
*hwif
= HWIF(drive
);
120 unsigned long base
= (unsigned long)hwif
->hwif_data
;
123 base
+= (hwif
->channel
<< 6);
125 base
+= (hwif
->channel
<< 4);
126 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
131 * sil_udma_filter - compute UDMA mask
134 * Compute the available UDMA speeds for the device on the interface.
136 * For the CMD680 this depends on the clocking mode (scsc), for the
137 * SI3112 SATA controller life is a bit simpler.
140 static u8
sil_pata_udma_filter(ide_drive_t
*drive
)
142 ide_hwif_t
*hwif
= drive
->hwif
;
143 unsigned long base
= (unsigned long) hwif
->hwif_data
;
144 u8 mask
= 0, scsc
= 0;
147 scsc
= hwif
->INB(base
+ 0x4A);
149 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
151 if ((scsc
& 0x30) == 0x10) /* 133 */
153 else if ((scsc
& 0x30) == 0x20) /* 2xPCI */
155 else if ((scsc
& 0x30) == 0x00) /* 100 */
157 else /* Disabled ? */
163 static u8
sil_sata_udma_filter(ide_drive_t
*drive
)
165 return strstr(drive
->id
->model
, "Maxtor") ? ATA_UDMA5
: ATA_UDMA6
;
169 * sil_set_pio_mode - set host controller for PIO mode
171 * @pio: PIO mode number
173 * Load the timing settings for this device mode into the
174 * controller. If we are in PIO mode 3 or 4 turn on IORDY
175 * monitoring (bit 9). The TF timing is bits 31:16
178 static void sil_set_pio_mode(ide_drive_t
*drive
, u8 pio
)
180 const u16 tf_speed
[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
181 const u16 data_speed
[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
183 ide_hwif_t
*hwif
= HWIF(drive
);
184 ide_drive_t
*pair
= ide_get_paired_drive(drive
);
187 unsigned long addr
= siimage_seldev(drive
, 0x04);
188 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
189 unsigned long base
= (unsigned long)hwif
->hwif_data
;
191 u8 addr_mask
= hwif
->channel
? (hwif
->mmio
? 0xF4 : 0x84)
192 : (hwif
->mmio
? 0xB4 : 0x80);
194 u8 unit
= drive
->select
.b
.unit
;
196 /* trim *taskfile* PIO to the slowest of the master/slave */
198 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
200 if (pair_pio
< tf_pio
)
204 /* cheat for now and use the docs */
205 speedp
= data_speed
[pio
];
206 speedt
= tf_speed
[tf_pio
];
209 hwif
->OUTW(speedp
, addr
);
210 hwif
->OUTW(speedt
, tfaddr
);
211 /* Now set up IORDY */
213 hwif
->OUTW(hwif
->INW(tfaddr
-2)|0x200, tfaddr
-2);
215 hwif
->OUTW(hwif
->INW(tfaddr
-2)&~0x200, tfaddr
-2);
217 mode
= hwif
->INB(base
+ addr_mask
);
218 mode
&= ~(unit
? 0x30 : 0x03);
219 mode
|= (unit
? 0x10 : 0x01);
220 hwif
->OUTB(mode
, base
+ addr_mask
);
222 pci_write_config_word(hwif
->pci_dev
, addr
, speedp
);
223 pci_write_config_word(hwif
->pci_dev
, tfaddr
, speedt
);
224 pci_read_config_word(hwif
->pci_dev
, tfaddr
-2, &speedp
);
226 /* Set IORDY for mode 3 or 4 */
229 pci_write_config_word(hwif
->pci_dev
, tfaddr
-2, speedp
);
231 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
232 mode
&= ~(unit
? 0x30 : 0x03);
233 mode
|= (unit
? 0x10 : 0x01);
234 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
239 * sil_set_dma_mode - set host controller for DMA mode
243 * Tune the SiI chipset for the desired DMA mode.
246 static void sil_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
248 u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
249 u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
250 u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
252 ide_hwif_t
*hwif
= HWIF(drive
);
253 u16 ultra
= 0, multi
= 0;
254 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
255 unsigned long base
= (unsigned long)hwif
->hwif_data
;
256 u8 scsc
= 0, addr_mask
= ((hwif
->channel
) ?
257 ((hwif
->mmio
) ? 0xF4 : 0x84) :
258 ((hwif
->mmio
) ? 0xB4 : 0x80));
260 unsigned long ma
= siimage_seldev(drive
, 0x08);
261 unsigned long ua
= siimage_seldev(drive
, 0x0C);
264 scsc
= hwif
->INB(base
+ 0x4A);
265 mode
= hwif
->INB(base
+ addr_mask
);
266 multi
= hwif
->INW(ma
);
267 ultra
= hwif
->INW(ua
);
269 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
270 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
271 pci_read_config_word(hwif
->pci_dev
, ma
, &multi
);
272 pci_read_config_word(hwif
->pci_dev
, ua
, &ultra
);
275 mode
&= ~((unit
) ? 0x30 : 0x03);
277 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
279 scsc
= is_sata(hwif
) ? 1 : scsc
;
285 multi
= dma
[speed
- XFER_MW_DMA_0
];
286 mode
|= ((unit
) ? 0x20 : 0x02);
296 ultra
|= ((scsc
) ? (ultra6
[speed
- XFER_UDMA_0
]) :
297 (ultra5
[speed
- XFER_UDMA_0
]));
298 mode
|= ((unit
) ? 0x30 : 0x03);
305 hwif
->OUTB(mode
, base
+ addr_mask
);
306 hwif
->OUTW(multi
, ma
);
307 hwif
->OUTW(ultra
, ua
);
309 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
310 pci_write_config_word(hwif
->pci_dev
, ma
, multi
);
311 pci_write_config_word(hwif
->pci_dev
, ua
, ultra
);
315 /* returns 1 if dma irq issued, 0 otherwise */
316 static int siimage_io_ide_dma_test_irq (ide_drive_t
*drive
)
318 ide_hwif_t
*hwif
= HWIF(drive
);
320 unsigned long addr
= siimage_selreg(hwif
, 1);
322 /* return 1 if INTR asserted */
323 if ((hwif
->INB(hwif
->dma_status
) & 4) == 4)
326 /* return 1 if Device INTR asserted */
327 pci_read_config_byte(hwif
->pci_dev
, addr
, &dma_altstat
);
329 return 0; //return 1;
334 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
335 * @drive: drive we are testing
337 * Check if we caused an IDE DMA interrupt. We may also have caused
338 * SATA status interrupts, if so we clean them up and continue.
341 static int siimage_mmio_ide_dma_test_irq (ide_drive_t
*drive
)
343 ide_hwif_t
*hwif
= HWIF(drive
);
344 unsigned long addr
= siimage_selreg(hwif
, 0x1);
346 if (SATA_ERROR_REG
) {
347 unsigned long base
= (unsigned long)hwif
->hwif_data
;
349 u32 ext_stat
= readl((void __iomem
*)(base
+ 0x10));
351 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
352 u32 sata_error
= readl((void __iomem
*)SATA_ERROR_REG
);
353 writel(sata_error
, (void __iomem
*)SATA_ERROR_REG
);
354 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
355 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
356 "watchdog = %d, %s\n",
357 drive
->name
, sata_error
, watchdog
,
361 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
365 if (!(ext_stat
& 0x0404) && !watchdog
)
369 /* return 1 if INTR asserted */
370 if ((readb((void __iomem
*)hwif
->dma_status
) & 0x04) == 0x04)
373 /* return 1 if Device INTR asserted */
374 if ((readb((void __iomem
*)addr
) & 8) == 8)
375 return 0; //return 1;
381 * sil_sata_busproc - bus isolation IOCTL
382 * @drive: drive to isolate/restore
383 * @state: bus state to set
385 * Used by the SII3112 to handle bus isolation. As this is a
386 * SATA controller the work required is quite limited, we
387 * just have to clean up the statistics
390 static int sil_sata_busproc(ide_drive_t
* drive
, int state
)
392 ide_hwif_t
*hwif
= HWIF(drive
);
394 unsigned long addr
= siimage_selreg(hwif
, 0);
397 stat_config
= readl((void __iomem
*)addr
);
399 pci_read_config_dword(hwif
->pci_dev
, addr
, &stat_config
);
403 hwif
->drives
[0].failures
= 0;
404 hwif
->drives
[1].failures
= 0;
407 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
408 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
410 case BUSSTATE_TRISTATE
:
411 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
412 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
417 hwif
->bus_state
= state
;
422 * sil_sata_reset_poll - wait for SATA reset
423 * @drive: drive we are resetting
425 * Poll the SATA phy and see whether it has come back from the dead
429 static int sil_sata_reset_poll(ide_drive_t
*drive
)
431 if (SATA_STATUS_REG
) {
432 ide_hwif_t
*hwif
= HWIF(drive
);
434 /* SATA_STATUS_REG is valid only when in MMIO mode */
435 if ((readl((void __iomem
*)SATA_STATUS_REG
) & 0x03) != 0x03) {
436 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
437 hwif
->name
, readl((void __iomem
*)SATA_STATUS_REG
));
438 HWGROUP(drive
)->polling
= 0;
447 * sil_sata_pre_reset - reset hook
448 * @drive: IDE device being reset
450 * For the SATA devices we need to handle recalibration/geometry
454 static void sil_sata_pre_reset(ide_drive_t
*drive
)
456 if (drive
->media
== ide_disk
) {
457 drive
->special
.b
.set_geometry
= 0;
458 drive
->special
.b
.recalibrate
= 0;
463 * proc_reports_siimage - add siimage controller to proc
465 * @clocking: SCSC value
466 * @name: controller name
468 * Report the clocking mode of the controller and add it to
469 * the /proc interface layer
472 static void proc_reports_siimage (struct pci_dev
*dev
, u8 clocking
, const char *name
)
474 if (!pdev_is_sata(dev
)) {
475 printk(KERN_INFO
"%s: BASE CLOCK ", name
);
478 case 0x03: printk("DISABLED!\n"); break;
479 case 0x02: printk("== 2X PCI\n"); break;
480 case 0x01: printk("== 133\n"); break;
481 case 0x00: printk("== 100\n"); break;
487 * setup_mmio_siimage - switch an SI controller into MMIO
488 * @dev: PCI device we are configuring
491 * Attempt to put the device into mmio mode. There are some slight
492 * complications here with certain systems where the mmio bar isnt
493 * mapped so we have to be sure we can fall back to I/O.
496 static unsigned int setup_mmio_siimage (struct pci_dev
*dev
, const char *name
)
498 unsigned long bar5
= pci_resource_start(dev
, 5);
499 unsigned long barsize
= pci_resource_len(dev
, 5);
501 void __iomem
*ioaddr
;
505 * Drop back to PIO if we can't map the mmio. Some
506 * systems seem to get terminally confused in the PCI
510 if(!request_mem_region(bar5
, barsize
, name
))
512 printk(KERN_WARNING
"siimage: IDE controller MMIO ports not available.\n");
516 ioaddr
= ioremap(bar5
, barsize
);
520 release_mem_region(bar5
, barsize
);
525 pci_set_drvdata(dev
, (void *) ioaddr
);
527 if (pdev_is_sata(dev
)) {
528 /* make sure IDE0/1 interrupts are not masked */
529 irq_mask
= (1 << 22) | (1 << 23);
530 tmp
= readl(ioaddr
+ 0x48);
531 if (tmp
& irq_mask
) {
533 writel(tmp
, ioaddr
+ 0x48);
534 readl(ioaddr
+ 0x48); /* flush */
536 writel(0, ioaddr
+ 0x148);
537 writel(0, ioaddr
+ 0x1C8);
540 writeb(0, ioaddr
+ 0xB4);
541 writeb(0, ioaddr
+ 0xF4);
542 tmpbyte
= readb(ioaddr
+ 0x4A);
544 switch(tmpbyte
& 0x30) {
546 /* In 100 MHz clocking, try and switch to 133 */
547 writeb(tmpbyte
|0x10, ioaddr
+ 0x4A);
550 /* On 133Mhz clocking */
553 /* On PCIx2 clocking */
556 /* Clocking is disabled */
557 /* 133 clock attempt to force it on */
558 writeb(tmpbyte
& ~0x20, ioaddr
+ 0x4A);
562 writeb( 0x72, ioaddr
+ 0xA1);
563 writew( 0x328A, ioaddr
+ 0xA2);
564 writel(0x62DD62DD, ioaddr
+ 0xA4);
565 writel(0x43924392, ioaddr
+ 0xA8);
566 writel(0x40094009, ioaddr
+ 0xAC);
567 writeb( 0x72, ioaddr
+ 0xE1);
568 writew( 0x328A, ioaddr
+ 0xE2);
569 writel(0x62DD62DD, ioaddr
+ 0xE4);
570 writel(0x43924392, ioaddr
+ 0xE8);
571 writel(0x40094009, ioaddr
+ 0xEC);
573 if (pdev_is_sata(dev
)) {
574 writel(0xFFFF0000, ioaddr
+ 0x108);
575 writel(0xFFFF0000, ioaddr
+ 0x188);
576 writel(0x00680000, ioaddr
+ 0x148);
577 writel(0x00680000, ioaddr
+ 0x1C8);
580 tmpbyte
= readb(ioaddr
+ 0x4A);
582 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
587 * init_chipset_siimage - set up an SI device
591 * Perform the initial PCI set up for this device. Attempt to switch
592 * to 133MHz clocking if the system isn't already set up to do it.
595 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
, const char *name
)
597 u8 rev
= dev
->revision
, tmpbyte
= 0, BA5_EN
= 0;
599 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, rev
? 1 : 255);
601 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
602 if ((BA5_EN
& 0x01) || (pci_resource_start(dev
, 5))) {
603 if (setup_mmio_siimage(dev
, name
)) {
608 pci_write_config_byte(dev
, 0x80, 0x00);
609 pci_write_config_byte(dev
, 0x84, 0x00);
610 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
611 switch(tmpbyte
& 0x30) {
613 /* 133 clock attempt to force it on */
614 pci_write_config_byte(dev
, 0x8A, tmpbyte
|0x10);
616 /* if clocking is disabled */
617 /* 133 clock attempt to force it on */
618 pci_write_config_byte(dev
, 0x8A, tmpbyte
& ~0x20);
623 /* BIOS set PCI x2 clocking */
627 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
629 pci_write_config_byte(dev
, 0xA1, 0x72);
630 pci_write_config_word(dev
, 0xA2, 0x328A);
631 pci_write_config_dword(dev
, 0xA4, 0x62DD62DD);
632 pci_write_config_dword(dev
, 0xA8, 0x43924392);
633 pci_write_config_dword(dev
, 0xAC, 0x40094009);
634 pci_write_config_byte(dev
, 0xB1, 0x72);
635 pci_write_config_word(dev
, 0xB2, 0x328A);
636 pci_write_config_dword(dev
, 0xB4, 0x62DD62DD);
637 pci_write_config_dword(dev
, 0xB8, 0x43924392);
638 pci_write_config_dword(dev
, 0xBC, 0x40094009);
640 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
645 * init_mmio_iops_siimage - set up the iops for MMIO
646 * @hwif: interface to set up
648 * The basic setup here is fairly simple, we can use standard MMIO
649 * operations. However we do have to set the taskfile register offsets
650 * by hand as there isnt a standard defined layout for them this
653 * The hardware supports buffered taskfiles and also some rather nice
654 * extended PRD tables. For better SI3112 support use the libata driver
657 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
659 struct pci_dev
*dev
= hwif
->pci_dev
;
660 void *addr
= pci_get_drvdata(dev
);
661 u8 ch
= hwif
->channel
;
666 * Fill in the basic HWIF bits
669 default_hwif_mmiops(hwif
);
670 hwif
->hwif_data
= addr
;
673 * Now set up the hw. We have to do this ourselves as
674 * the MMIO layout isnt the same as the standard port
678 memset(&hw
, 0, sizeof(hw_regs_t
));
680 base
= (unsigned long)addr
;
687 * The buffered task file doesn't have status/control
688 * so we can't currently use it sanely since we want to
691 hw
.io_ports
[IDE_DATA_OFFSET
] = base
;
692 hw
.io_ports
[IDE_ERROR_OFFSET
] = base
+ 1;
693 hw
.io_ports
[IDE_NSECTOR_OFFSET
] = base
+ 2;
694 hw
.io_ports
[IDE_SECTOR_OFFSET
] = base
+ 3;
695 hw
.io_ports
[IDE_LCYL_OFFSET
] = base
+ 4;
696 hw
.io_ports
[IDE_HCYL_OFFSET
] = base
+ 5;
697 hw
.io_ports
[IDE_SELECT_OFFSET
] = base
+ 6;
698 hw
.io_ports
[IDE_STATUS_OFFSET
] = base
+ 7;
699 hw
.io_ports
[IDE_CONTROL_OFFSET
] = base
+ 10;
701 hw
.io_ports
[IDE_IRQ_OFFSET
] = 0;
703 if (pdev_is_sata(dev
)) {
704 base
= (unsigned long)addr
;
707 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
708 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
709 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
710 hwif
->sata_misc
[SATA_MISC_OFFSET
] = base
+ 0x140;
711 hwif
->sata_misc
[SATA_PHY_OFFSET
] = base
+ 0x144;
712 hwif
->sata_misc
[SATA_IEN_OFFSET
] = base
+ 0x148;
715 memcpy(hwif
->io_ports
, hw
.io_ports
, sizeof(hwif
->io_ports
));
717 hwif
->irq
= dev
->irq
;
719 hwif
->dma_base
= (unsigned long)addr
+ (ch
? 0x08 : 0x00);
724 static int is_dev_seagate_sata(ide_drive_t
*drive
)
726 const char *s
= &drive
->id
->model
[0];
732 len
= strnlen(s
, sizeof(drive
->id
->model
));
734 if ((len
> 4) && (!memcmp(s
, "ST", 2))) {
735 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
736 (!memcmp(s
+ len
- 3, "ASL", 3))) {
737 printk(KERN_INFO
"%s: applying pessimistic Seagate "
738 "errata fix\n", drive
->name
);
746 * siimage_fixup - post probe fixups
747 * @hwif: interface to fix up
749 * Called after drive probe we use this to decide whether the
750 * Seagate fixup must be applied. This used to be in init_iops but
751 * that can occur before we know what drives are present.
754 static void __devinit
siimage_fixup(ide_hwif_t
*hwif
)
756 /* Try and raise the rqsize */
757 if (!is_sata(hwif
) || !is_dev_seagate_sata(&hwif
->drives
[0]))
762 * init_iops_siimage - set up iops
763 * @hwif: interface to set up
765 * Do the basic setup for the SIIMAGE hardware interface
766 * and then do the MMIO setup if we can. This is the first
767 * look in we get for setting up the hwif so that we
768 * can get the iops right before using them.
771 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
773 hwif
->hwif_data
= NULL
;
775 /* Pessimal until we finish probing */
778 if (pci_get_drvdata(hwif
->pci_dev
) == NULL
)
781 init_mmio_iops_siimage(hwif
);
785 * ata66_siimage - check for 80 pin cable
786 * @hwif: interface to check
788 * Check for the presence of an ATA66 capable cable on the
792 static u8 __devinit
ata66_siimage(ide_hwif_t
*hwif
)
794 unsigned long addr
= siimage_selreg(hwif
, 0);
797 if (pci_get_drvdata(hwif
->pci_dev
) == NULL
)
798 pci_read_config_byte(hwif
->pci_dev
, addr
, &ata66
);
800 ata66
= hwif
->INB(addr
);
802 return (ata66
& 0x01) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
806 * init_hwif_siimage - set up hwif structs
807 * @hwif: interface to set up
809 * We do the basic set up of the interface structure. The SIIMAGE
810 * requires several custom handlers so we override the default
811 * ide DMA handlers appropriately
814 static void __devinit
init_hwif_siimage(ide_hwif_t
*hwif
)
816 u8 sata
= is_sata(hwif
);
818 hwif
->set_pio_mode
= &sil_set_pio_mode
;
819 hwif
->set_dma_mode
= &sil_set_dma_mode
;
822 static int first
= 1;
824 hwif
->busproc
= &sil_sata_busproc
;
825 hwif
->reset_poll
= &sil_sata_reset_poll
;
826 hwif
->pre_reset
= &sil_sata_pre_reset
;
827 hwif
->udma_filter
= &sil_sata_udma_filter
;
830 printk(KERN_INFO
"siimage: For full SATA support you should use the libata sata_sil module.\n");
834 hwif
->udma_filter
= &sil_pata_udma_filter
;
836 if (hwif
->dma_base
== 0)
840 hwif
->host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
842 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
843 hwif
->cbl
= ata66_siimage(hwif
);
846 hwif
->ide_dma_test_irq
= &siimage_mmio_ide_dma_test_irq
;
848 hwif
->ide_dma_test_irq
= & siimage_io_ide_dma_test_irq
;
852 #define DECLARE_SII_DEV(name_str) \
855 .init_chipset = init_chipset_siimage, \
856 .init_iops = init_iops_siimage, \
857 .init_hwif = init_hwif_siimage, \
858 .fixup = siimage_fixup, \
859 .host_flags = IDE_HFLAG_BOOTABLE, \
860 .pio_mask = ATA_PIO4, \
861 .mwdma_mask = ATA_MWDMA2, \
862 .udma_mask = ATA_UDMA6, \
865 static const struct ide_port_info siimage_chipsets
[] __devinitdata
= {
866 /* 0 */ DECLARE_SII_DEV("SiI680"),
867 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
868 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
872 * siimage_init_one - pci layer discovery entry
874 * @id: ident table entry
876 * Called by the PCI code when it finds an SI680 or SI3112 controller.
877 * We then use the IDE PCI generic helper to do most of the work.
880 static int __devinit
siimage_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
882 return ide_setup_pci_device(dev
, &siimage_chipsets
[id
->driver_data
]);
885 static const struct pci_device_id siimage_pci_tbl
[] = {
886 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_680
), 0 },
887 #ifdef CONFIG_BLK_DEV_IDE_SATA
888 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_3112
), 1 },
889 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_1210SA
), 2 },
893 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
895 static struct pci_driver driver
= {
897 .id_table
= siimage_pci_tbl
,
898 .probe
= siimage_init_one
,
901 static int __init
siimage_ide_init(void)
903 return ide_pci_register_driver(&driver
);
906 module_init(siimage_ide_init
);
908 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
909 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
910 MODULE_LICENSE("GPL");