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IDE: sg chaining support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / sgiioc4.c
1 /*
2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 *
16 * For further information regarding this notice, see:
17 *
18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
19 */
20
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/timer.h>
29 #include <linux/mm.h>
30 #include <linux/ioport.h>
31 #include <linux/blkdev.h>
32 #include <linux/scatterlist.h>
33 #include <linux/ioc4.h>
34 #include <asm/io.h>
35
36 #include <linux/ide.h>
37
38 #define DRV_NAME "SGIIOC4"
39
40 /* IOC4 Specific Definitions */
41 #define IOC4_CMD_OFFSET 0x100
42 #define IOC4_CTRL_OFFSET 0x120
43 #define IOC4_DMA_OFFSET 0x140
44 #define IOC4_INTR_OFFSET 0x0
45
46 #define IOC4_TIMING 0x00
47 #define IOC4_DMA_PTR_L 0x01
48 #define IOC4_DMA_PTR_H 0x02
49 #define IOC4_DMA_ADDR_L 0x03
50 #define IOC4_DMA_ADDR_H 0x04
51 #define IOC4_BC_DEV 0x05
52 #define IOC4_BC_MEM 0x06
53 #define IOC4_DMA_CTRL 0x07
54 #define IOC4_DMA_END_ADDR 0x08
55
56 /* Bits in the IOC4 Control/Status Register */
57 #define IOC4_S_DMA_START 0x01
58 #define IOC4_S_DMA_STOP 0x02
59 #define IOC4_S_DMA_DIR 0x04
60 #define IOC4_S_DMA_ACTIVE 0x08
61 #define IOC4_S_DMA_ERROR 0x10
62 #define IOC4_ATA_MEMERR 0x02
63
64 /* Read/Write Directions */
65 #define IOC4_DMA_WRITE 0x04
66 #define IOC4_DMA_READ 0x00
67
68 /* Interrupt Register Offsets */
69 #define IOC4_INTR_REG 0x03
70 #define IOC4_INTR_SET 0x05
71 #define IOC4_INTR_CLEAR 0x07
72
73 #define IOC4_IDE_CACHELINE_SIZE 128
74 #define IOC4_CMD_CTL_BLK_SIZE 0x20
75 #define IOC4_SUPPORTED_FIRMWARE_REV 46
76
77 typedef struct {
78 u32 timing_reg0;
79 u32 timing_reg1;
80 u32 low_mem_ptr;
81 u32 high_mem_ptr;
82 u32 low_mem_addr;
83 u32 high_mem_addr;
84 u32 dev_byte_count;
85 u32 mem_byte_count;
86 u32 status;
87 } ioc4_dma_regs_t;
88
89 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
90 /* IOC4 has only 1 IDE channel */
91 #define IOC4_PRD_BYTES 16
92 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
93
94
95 static void
96 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
97 unsigned long ctrl_port, unsigned long irq_port)
98 {
99 unsigned long reg = data_port;
100 int i;
101
102 /* Registers are word (32 bit) aligned */
103 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
104 hw->io_ports[i] = reg + i * 4;
105
106 if (ctrl_port)
107 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
108
109 if (irq_port)
110 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
111 }
112
113 static void
114 sgiioc4_maskproc(ide_drive_t * drive, int mask)
115 {
116 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
117 (void __iomem *)IDE_CONTROL_REG);
118 }
119
120
121 static int
122 sgiioc4_checkirq(ide_hwif_t * hwif)
123 {
124 unsigned long intr_addr =
125 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
126
127 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
128 return 1;
129
130 return 0;
131 }
132
133 static u8 sgiioc4_INB(unsigned long);
134
135 static int
136 sgiioc4_clearirq(ide_drive_t * drive)
137 {
138 u32 intr_reg;
139 ide_hwif_t *hwif = HWIF(drive);
140 unsigned long other_ir =
141 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
142
143 /* Code to check for PCI error conditions */
144 intr_reg = readl((void __iomem *)other_ir);
145 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
146 /*
147 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
148 * of clearing the interrupt. The first read should clear it
149 * if it is set. The second read should return a "clear" status
150 * if it got cleared. If not, then spin for a bit trying to
151 * clear it.
152 */
153 u8 stat = sgiioc4_INB(IDE_STATUS_REG);
154 int count = 0;
155 stat = sgiioc4_INB(IDE_STATUS_REG);
156 while ((stat & 0x80) && (count++ < 100)) {
157 udelay(1);
158 stat = sgiioc4_INB(IDE_STATUS_REG);
159 }
160
161 if (intr_reg & 0x02) {
162 /* Error when transferring DMA data on PCI bus */
163 u32 pci_err_addr_low, pci_err_addr_high,
164 pci_stat_cmd_reg;
165
166 pci_err_addr_low =
167 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
168 pci_err_addr_high =
169 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
170 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
171 &pci_stat_cmd_reg);
172 printk(KERN_ERR
173 "%s(%s) : PCI Bus Error when doing DMA:"
174 " status-cmd reg is 0x%x\n",
175 __FUNCTION__, drive->name, pci_stat_cmd_reg);
176 printk(KERN_ERR
177 "%s(%s) : PCI Error Address is 0x%x%x\n",
178 __FUNCTION__, drive->name,
179 pci_err_addr_high, pci_err_addr_low);
180 /* Clear the PCI Error indicator */
181 pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
182 0x00000146);
183 }
184
185 /* Clear the Interrupt, Error bits on the IOC4 */
186 writel(0x03, (void __iomem *)other_ir);
187
188 intr_reg = readl((void __iomem *)other_ir);
189 }
190
191 return intr_reg & 3;
192 }
193
194 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
195 {
196 ide_hwif_t *hwif = HWIF(drive);
197 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
198 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
199 unsigned int temp_reg = reg | IOC4_S_DMA_START;
200
201 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
202 }
203
204 static u32
205 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
206 {
207 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
208 u32 ioc4_dma;
209 int count;
210
211 count = 0;
212 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
213 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
214 udelay(1);
215 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
216 }
217 return ioc4_dma;
218 }
219
220 /* Stops the IOC4 DMA Engine */
221 static int
222 sgiioc4_ide_dma_end(ide_drive_t * drive)
223 {
224 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
225 ide_hwif_t *hwif = HWIF(drive);
226 unsigned long dma_base = hwif->dma_base;
227 int dma_stat = 0;
228 unsigned long *ending_dma = ide_get_hwifdata(hwif);
229
230 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
231
232 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
233
234 if (ioc4_dma & IOC4_S_DMA_STOP) {
235 printk(KERN_ERR
236 "%s(%s): IOC4 DMA STOP bit is still 1 :"
237 "ioc4_dma_reg 0x%x\n",
238 __FUNCTION__, drive->name, ioc4_dma);
239 dma_stat = 1;
240 }
241
242 /*
243 * The IOC4 will DMA 1's to the ending dma area to indicate that
244 * previous data DMA is complete. This is necessary because of relaxed
245 * ordering between register reads and DMA writes on the Altix.
246 */
247 while ((cnt++ < 200) && (!valid)) {
248 for (num = 0; num < 16; num++) {
249 if (ending_dma[num]) {
250 valid = 1;
251 break;
252 }
253 }
254 udelay(1);
255 }
256 if (!valid) {
257 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
258 drive->name);
259 dma_stat = 1;
260 }
261
262 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
263 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
264
265 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
266 if (bc_dev > bc_mem + 8) {
267 printk(KERN_ERR
268 "%s(%s): WARNING!! byte_count_dev %d "
269 "!= byte_count_mem %d\n",
270 __FUNCTION__, drive->name, bc_dev, bc_mem);
271 }
272 }
273
274 drive->waiting_for_dma = 0;
275 ide_destroy_dmatable(drive);
276
277 return dma_stat;
278 }
279
280 static int
281 sgiioc4_ide_dma_on(ide_drive_t * drive)
282 {
283 drive->using_dma = 1;
284
285 return 0;
286 }
287
288 static void sgiioc4_dma_off_quietly(ide_drive_t *drive)
289 {
290 drive->using_dma = 0;
291
292 drive->hwif->dma_host_off(drive);
293 }
294
295 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
296 {
297 }
298
299 static int sgiioc4_ide_dma_check(ide_drive_t *drive)
300 {
301 if (ide_tune_dma(drive))
302 return 0;
303
304 /*
305 * ->set_pio_mode is not implemented currently
306 * so this is just for the completness
307 */
308 ide_set_max_pio(drive);
309
310 return -1;
311 }
312
313 /* returns 1 if dma irq issued, 0 otherwise */
314 static int
315 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
316 {
317 return sgiioc4_checkirq(HWIF(drive));
318 }
319
320 static void sgiioc4_dma_host_on(ide_drive_t * drive)
321 {
322 }
323
324 static void sgiioc4_dma_host_off(ide_drive_t * drive)
325 {
326 sgiioc4_clearirq(drive);
327 }
328
329 static void
330 sgiioc4_resetproc(ide_drive_t * drive)
331 {
332 sgiioc4_ide_dma_end(drive);
333 sgiioc4_clearirq(drive);
334 }
335
336 static void
337 sgiioc4_dma_lost_irq(ide_drive_t * drive)
338 {
339 sgiioc4_resetproc(drive);
340
341 ide_dma_lost_irq(drive);
342 }
343
344 static u8
345 sgiioc4_INB(unsigned long port)
346 {
347 u8 reg = (u8) readb((void __iomem *) port);
348
349 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
350 if (reg & 0x51) { /* Not busy...check for interrupt */
351 unsigned long other_ir = port - 0x110;
352 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
353
354 /* Clear the Interrupt, Error bits on the IOC4 */
355 if (intr_reg & 0x03) {
356 writel(0x03, (void __iomem *) other_ir);
357 intr_reg = (u32) readl((void __iomem *) other_ir);
358 }
359 }
360 }
361
362 return reg;
363 }
364
365 /* Creates a dma map for the scatter-gather list entries */
366 static int __devinit
367 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
368 {
369 void __iomem *virt_dma_base;
370 int num_ports = sizeof (ioc4_dma_regs_t);
371 void *pad;
372
373 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
374 dma_base, dma_base + num_ports - 1);
375
376 if (!request_mem_region(dma_base, num_ports, hwif->name)) {
377 printk(KERN_ERR
378 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
379 "ALREADY in use\n",
380 __FUNCTION__, hwif->name, (void *) dma_base,
381 (void *) dma_base + num_ports - 1);
382 return -1;
383 }
384
385 virt_dma_base = ioremap(dma_base, num_ports);
386 if (virt_dma_base == NULL) {
387 printk(KERN_ERR
388 "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
389 __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
390 goto dma_remap_failure;
391 }
392 hwif->dma_base = (unsigned long) virt_dma_base;
393
394 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
395 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
396 &hwif->dmatable_dma);
397
398 if (!hwif->dmatable_cpu)
399 goto dma_pci_alloc_failure;
400
401 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
402
403 pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE,
404 (dma_addr_t *) &(hwif->dma_status));
405
406 if (pad) {
407 ide_set_hwifdata(hwif, pad);
408 return 0;
409 }
410
411 pci_free_consistent(hwif->pci_dev,
412 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
413 hwif->dmatable_cpu, hwif->dmatable_dma);
414 printk(KERN_INFO
415 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
416 __FUNCTION__, hwif->name);
417 printk(KERN_INFO
418 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
419
420 dma_pci_alloc_failure:
421 iounmap(virt_dma_base);
422
423 dma_remap_failure:
424 release_mem_region(dma_base, num_ports);
425
426 return -1;
427 }
428
429 /* Initializes the IOC4 DMA Engine */
430 static void
431 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
432 {
433 u32 ioc4_dma;
434 ide_hwif_t *hwif = HWIF(drive);
435 unsigned long dma_base = hwif->dma_base;
436 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
437 u32 dma_addr, ending_dma_addr;
438
439 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
440
441 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
442 printk(KERN_WARNING
443 "%s(%s):Warning!! DMA from previous transfer was still active\n",
444 __FUNCTION__, drive->name);
445 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
446 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
447
448 if (ioc4_dma & IOC4_S_DMA_STOP)
449 printk(KERN_ERR
450 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
451 __FUNCTION__, drive->name);
452 }
453
454 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
455 if (ioc4_dma & IOC4_S_DMA_ERROR) {
456 printk(KERN_WARNING
457 "%s(%s) : Warning!! - DMA Error during Previous"
458 " transfer | status 0x%x\n",
459 __FUNCTION__, drive->name, ioc4_dma);
460 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
461 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
462
463 if (ioc4_dma & IOC4_S_DMA_STOP)
464 printk(KERN_ERR
465 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
466 __FUNCTION__, drive->name);
467 }
468
469 /* Address of the Scatter Gather List */
470 dma_addr = cpu_to_le32(hwif->dmatable_dma);
471 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
472
473 /* Address of the Ending DMA */
474 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
475 ending_dma_addr = cpu_to_le32(hwif->dma_status);
476 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
477
478 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
479 drive->waiting_for_dma = 1;
480 }
481
482 /* IOC4 Scatter Gather list Format */
483 /* 128 Bit entries to support 64 bit addresses in the future */
484 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
485 /* --------------------------------------------------------------------- */
486 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
487 /* --------------------------------------------------------------------- */
488 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
489 /* --------------------------------------------------------------------- */
490 /* Creates the scatter gather list, DMA Table */
491 static unsigned int
492 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
493 {
494 ide_hwif_t *hwif = HWIF(drive);
495 unsigned int *table = hwif->dmatable_cpu;
496 unsigned int count = 0, i = 1;
497 struct scatterlist *sg;
498
499 hwif->sg_nents = i = ide_build_sglist(drive, rq);
500
501 if (!i)
502 return 0; /* sglist of length Zero */
503
504 sg = hwif->sg_table;
505 while (i && sg_dma_len(sg)) {
506 dma_addr_t cur_addr;
507 int cur_len;
508 cur_addr = sg_dma_address(sg);
509 cur_len = sg_dma_len(sg);
510
511 while (cur_len) {
512 if (count++ >= IOC4_PRD_ENTRIES) {
513 printk(KERN_WARNING
514 "%s: DMA table too small\n",
515 drive->name);
516 goto use_pio_instead;
517 } else {
518 u32 bcount =
519 0x10000 - (cur_addr & 0xffff);
520
521 if (bcount > cur_len)
522 bcount = cur_len;
523
524 /* put the addr, length in
525 * the IOC4 dma-table format */
526 *table = 0x0;
527 table++;
528 *table = cpu_to_be32(cur_addr);
529 table++;
530 *table = 0x0;
531 table++;
532
533 *table = cpu_to_be32(bcount);
534 table++;
535
536 cur_addr += bcount;
537 cur_len -= bcount;
538 }
539 }
540
541 sg = sg_next(sg);
542 i--;
543 }
544
545 if (count) {
546 table--;
547 *table |= cpu_to_be32(0x80000000);
548 return count;
549 }
550
551 use_pio_instead:
552 pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
553 hwif->sg_dma_direction);
554
555 return 0; /* revert to PIO for this request */
556 }
557
558 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
559 {
560 struct request *rq = HWGROUP(drive)->rq;
561 unsigned int count = 0;
562 int ddir;
563
564 if (rq_data_dir(rq))
565 ddir = PCI_DMA_TODEVICE;
566 else
567 ddir = PCI_DMA_FROMDEVICE;
568
569 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
570 /* try PIO instead of DMA */
571 ide_map_sg(drive, rq);
572 return 1;
573 }
574
575 if (rq_data_dir(rq))
576 /* Writes TO the IOC4 FROM Main Memory */
577 ddir = IOC4_DMA_READ;
578 else
579 /* Writes FROM the IOC4 TO Main Memory */
580 ddir = IOC4_DMA_WRITE;
581
582 sgiioc4_configure_for_dma(ddir, drive);
583
584 return 0;
585 }
586
587 static void __devinit
588 ide_init_sgiioc4(ide_hwif_t * hwif)
589 {
590 hwif->mmio = 1;
591 hwif->pio_mask = 0x00;
592 hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */
593 hwif->set_dma_mode = &sgiioc4_set_dma_mode;
594 hwif->selectproc = NULL;/* Use the default routine to select drive */
595 hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
596 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
597 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
598 clear interrupts */
599 hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */
600 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
601 hwif->quirkproc = NULL;
602 hwif->busproc = NULL;
603
604 hwif->INB = &sgiioc4_INB;
605
606 if (hwif->dma_base == 0)
607 return;
608
609 hwif->atapi_dma = 1;
610 hwif->mwdma_mask = 0x04;
611
612 hwif->dma_setup = &sgiioc4_ide_dma_setup;
613 hwif->dma_start = &sgiioc4_ide_dma_start;
614 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
615 hwif->ide_dma_check = &sgiioc4_ide_dma_check;
616 hwif->ide_dma_on = &sgiioc4_ide_dma_on;
617 hwif->dma_off_quietly = &sgiioc4_dma_off_quietly;
618 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
619 hwif->dma_host_on = &sgiioc4_dma_host_on;
620 hwif->dma_host_off = &sgiioc4_dma_host_off;
621 hwif->dma_lost_irq = &sgiioc4_dma_lost_irq;
622 hwif->dma_timeout = &ide_dma_timeout;
623 }
624
625 static int __devinit
626 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
627 {
628 unsigned long cmd_base, dma_base, irqport;
629 unsigned long bar0, cmd_phys_base, ctl;
630 void __iomem *virt_base;
631 ide_hwif_t *hwif;
632 int h;
633
634 /*
635 * Find an empty HWIF; if none available, return -ENOMEM.
636 */
637 for (h = 0; h < MAX_HWIFS; ++h) {
638 hwif = &ide_hwifs[h];
639 if (hwif->chipset == ide_unknown)
640 break;
641 }
642 if (h == MAX_HWIFS) {
643 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n",
644 DRV_NAME);
645 return -ENOMEM;
646 }
647
648 /* Get the CmdBlk and CtrlBlk Base Registers */
649 bar0 = pci_resource_start(dev, 0);
650 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
651 if (virt_base == NULL) {
652 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
653 DRV_NAME, bar0);
654 return -ENOMEM;
655 }
656 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
657 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
658 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
659 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
660
661 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
662 if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
663 hwif->name)) {
664 printk(KERN_ERR
665 "%s : %s -- ERROR, Addresses "
666 "0x%p to 0x%p ALREADY in use\n",
667 __FUNCTION__, hwif->name, (void *) cmd_phys_base,
668 (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
669 return -ENOMEM;
670 }
671
672 if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
673 /* Initialize the IO registers */
674 sgiioc4_init_hwif_ports(&hwif->hw, cmd_base, ctl, irqport);
675 memcpy(hwif->io_ports, hwif->hw.io_ports,
676 sizeof (hwif->io_ports));
677 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
678 }
679
680 hwif->irq = dev->irq;
681 hwif->chipset = ide_pci;
682 hwif->pci_dev = dev;
683 hwif->channel = 0; /* Single Channel chip */
684 hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
685
686 /* The IOC4 uses MMIO rather than Port IO. */
687 default_hwif_mmiops(hwif);
688
689 /* Initializing chipset IRQ Registers */
690 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
691
692 hwif->autodma = 0;
693
694 if (dma_base && ide_dma_sgiioc4(hwif, dma_base) == 0) {
695 hwif->autodma = 1;
696 hwif->drives[1].autodma = hwif->drives[0].autodma = 1;
697 } else
698 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
699 hwif->name, DRV_NAME);
700
701 ide_init_sgiioc4(hwif);
702
703 if (probe_hwif_init(hwif))
704 return -EIO;
705
706 /* Create /proc/ide entries */
707 ide_proc_register_port(hwif);
708
709 return 0;
710 }
711
712 static unsigned int __devinit
713 pci_init_sgiioc4(struct pci_dev *dev)
714 {
715 unsigned int class_rev;
716 int ret;
717
718 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
719 class_rev &= 0xff;
720 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
721 DRV_NAME, pci_name(dev), class_rev);
722 if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
723 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
724 "firmware is obsolete - please upgrade to "
725 "revision46 or higher\n",
726 DRV_NAME, pci_name(dev));
727 ret = -EAGAIN;
728 goto out;
729 }
730 ret = sgiioc4_ide_setup_pci_device(dev);
731 out:
732 return ret;
733 }
734
735 int
736 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
737 {
738 /* PCI-RT does not bring out IDE connection.
739 * Do not attach to this particular IOC4.
740 */
741 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
742 return 0;
743
744 return pci_init_sgiioc4(idd->idd_pdev);
745 }
746
747 static struct ioc4_submodule ioc4_ide_submodule = {
748 .is_name = "IOC4_ide",
749 .is_owner = THIS_MODULE,
750 .is_probe = ioc4_ide_attach_one,
751 /* .is_remove = ioc4_ide_remove_one, */
752 };
753
754 static int __init ioc4_ide_init(void)
755 {
756 return ioc4_register_submodule(&ioc4_ide_submodule);
757 }
758
759 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
760
761 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
762 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
763 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)