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ide: add struct ide_port_ops (take 2)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / sgiioc4.c
1 /*
2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 *
16 * For further information regarding this notice, see:
17 *
18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
19 */
20
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/ioport.h>
29 #include <linux/blkdev.h>
30 #include <linux/scatterlist.h>
31 #include <linux/ioc4.h>
32 #include <asm/io.h>
33
34 #include <linux/ide.h>
35
36 #define DRV_NAME "SGIIOC4"
37
38 /* IOC4 Specific Definitions */
39 #define IOC4_CMD_OFFSET 0x100
40 #define IOC4_CTRL_OFFSET 0x120
41 #define IOC4_DMA_OFFSET 0x140
42 #define IOC4_INTR_OFFSET 0x0
43
44 #define IOC4_TIMING 0x00
45 #define IOC4_DMA_PTR_L 0x01
46 #define IOC4_DMA_PTR_H 0x02
47 #define IOC4_DMA_ADDR_L 0x03
48 #define IOC4_DMA_ADDR_H 0x04
49 #define IOC4_BC_DEV 0x05
50 #define IOC4_BC_MEM 0x06
51 #define IOC4_DMA_CTRL 0x07
52 #define IOC4_DMA_END_ADDR 0x08
53
54 /* Bits in the IOC4 Control/Status Register */
55 #define IOC4_S_DMA_START 0x01
56 #define IOC4_S_DMA_STOP 0x02
57 #define IOC4_S_DMA_DIR 0x04
58 #define IOC4_S_DMA_ACTIVE 0x08
59 #define IOC4_S_DMA_ERROR 0x10
60 #define IOC4_ATA_MEMERR 0x02
61
62 /* Read/Write Directions */
63 #define IOC4_DMA_WRITE 0x04
64 #define IOC4_DMA_READ 0x00
65
66 /* Interrupt Register Offsets */
67 #define IOC4_INTR_REG 0x03
68 #define IOC4_INTR_SET 0x05
69 #define IOC4_INTR_CLEAR 0x07
70
71 #define IOC4_IDE_CACHELINE_SIZE 128
72 #define IOC4_CMD_CTL_BLK_SIZE 0x20
73 #define IOC4_SUPPORTED_FIRMWARE_REV 46
74
75 typedef struct {
76 u32 timing_reg0;
77 u32 timing_reg1;
78 u32 low_mem_ptr;
79 u32 high_mem_ptr;
80 u32 low_mem_addr;
81 u32 high_mem_addr;
82 u32 dev_byte_count;
83 u32 mem_byte_count;
84 u32 status;
85 } ioc4_dma_regs_t;
86
87 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
88 /* IOC4 has only 1 IDE channel */
89 #define IOC4_PRD_BYTES 16
90 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
91
92
93 static void
94 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
95 unsigned long ctrl_port, unsigned long irq_port)
96 {
97 unsigned long reg = data_port;
98 int i;
99
100 /* Registers are word (32 bit) aligned */
101 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
102 hw->io_ports[i] = reg + i * 4;
103
104 if (ctrl_port)
105 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
106
107 if (irq_port)
108 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
109 }
110
111 static void
112 sgiioc4_maskproc(ide_drive_t * drive, int mask)
113 {
114 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
115 (void __iomem *)drive->hwif->io_ports[IDE_CONTROL_OFFSET]);
116 }
117
118 static int
119 sgiioc4_checkirq(ide_hwif_t * hwif)
120 {
121 unsigned long intr_addr =
122 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
123
124 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
125 return 1;
126
127 return 0;
128 }
129
130 static u8 sgiioc4_INB(unsigned long);
131
132 static int
133 sgiioc4_clearirq(ide_drive_t * drive)
134 {
135 u32 intr_reg;
136 ide_hwif_t *hwif = HWIF(drive);
137 unsigned long other_ir =
138 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
139
140 /* Code to check for PCI error conditions */
141 intr_reg = readl((void __iomem *)other_ir);
142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
143 /*
144 * Using sgiioc4_INB to read the Status register has a side
145 * effect of clearing the interrupt. The first read should
146 * clear it if it is set. The second read should return
147 * a "clear" status if it got cleared. If not, then spin
148 * for a bit trying to clear it.
149 */
150 u8 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
151 int count = 0;
152 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
153 while ((stat & 0x80) && (count++ < 100)) {
154 udelay(1);
155 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
156 }
157
158 if (intr_reg & 0x02) {
159 struct pci_dev *dev = to_pci_dev(hwif->dev);
160 /* Error when transferring DMA data on PCI bus */
161 u32 pci_err_addr_low, pci_err_addr_high,
162 pci_stat_cmd_reg;
163
164 pci_err_addr_low =
165 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
166 pci_err_addr_high =
167 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
168 pci_read_config_dword(dev, PCI_COMMAND,
169 &pci_stat_cmd_reg);
170 printk(KERN_ERR
171 "%s(%s) : PCI Bus Error when doing DMA:"
172 " status-cmd reg is 0x%x\n",
173 __FUNCTION__, drive->name, pci_stat_cmd_reg);
174 printk(KERN_ERR
175 "%s(%s) : PCI Error Address is 0x%x%x\n",
176 __FUNCTION__, drive->name,
177 pci_err_addr_high, pci_err_addr_low);
178 /* Clear the PCI Error indicator */
179 pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
180 }
181
182 /* Clear the Interrupt, Error bits on the IOC4 */
183 writel(0x03, (void __iomem *)other_ir);
184
185 intr_reg = readl((void __iomem *)other_ir);
186 }
187
188 return intr_reg & 3;
189 }
190
191 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
192 {
193 ide_hwif_t *hwif = HWIF(drive);
194 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
195 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
196 unsigned int temp_reg = reg | IOC4_S_DMA_START;
197
198 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
199 }
200
201 static u32
202 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
203 {
204 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
205 u32 ioc4_dma;
206 int count;
207
208 count = 0;
209 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
210 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
211 udelay(1);
212 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
213 }
214 return ioc4_dma;
215 }
216
217 /* Stops the IOC4 DMA Engine */
218 static int
219 sgiioc4_ide_dma_end(ide_drive_t * drive)
220 {
221 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
222 ide_hwif_t *hwif = HWIF(drive);
223 unsigned long dma_base = hwif->dma_base;
224 int dma_stat = 0;
225 unsigned long *ending_dma = ide_get_hwifdata(hwif);
226
227 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
228
229 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
230
231 if (ioc4_dma & IOC4_S_DMA_STOP) {
232 printk(KERN_ERR
233 "%s(%s): IOC4 DMA STOP bit is still 1 :"
234 "ioc4_dma_reg 0x%x\n",
235 __FUNCTION__, drive->name, ioc4_dma);
236 dma_stat = 1;
237 }
238
239 /*
240 * The IOC4 will DMA 1's to the ending dma area to indicate that
241 * previous data DMA is complete. This is necessary because of relaxed
242 * ordering between register reads and DMA writes on the Altix.
243 */
244 while ((cnt++ < 200) && (!valid)) {
245 for (num = 0; num < 16; num++) {
246 if (ending_dma[num]) {
247 valid = 1;
248 break;
249 }
250 }
251 udelay(1);
252 }
253 if (!valid) {
254 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
255 drive->name);
256 dma_stat = 1;
257 }
258
259 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
260 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
261
262 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
263 if (bc_dev > bc_mem + 8) {
264 printk(KERN_ERR
265 "%s(%s): WARNING!! byte_count_dev %d "
266 "!= byte_count_mem %d\n",
267 __FUNCTION__, drive->name, bc_dev, bc_mem);
268 }
269 }
270
271 drive->waiting_for_dma = 0;
272 ide_destroy_dmatable(drive);
273
274 return dma_stat;
275 }
276
277 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
278 {
279 }
280
281 /* returns 1 if dma irq issued, 0 otherwise */
282 static int
283 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
284 {
285 return sgiioc4_checkirq(HWIF(drive));
286 }
287
288 static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
289 {
290 if (!on)
291 sgiioc4_clearirq(drive);
292 }
293
294 static void
295 sgiioc4_resetproc(ide_drive_t * drive)
296 {
297 sgiioc4_ide_dma_end(drive);
298 sgiioc4_clearirq(drive);
299 }
300
301 static void
302 sgiioc4_dma_lost_irq(ide_drive_t * drive)
303 {
304 sgiioc4_resetproc(drive);
305
306 ide_dma_lost_irq(drive);
307 }
308
309 static u8
310 sgiioc4_INB(unsigned long port)
311 {
312 u8 reg = (u8) readb((void __iomem *) port);
313
314 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
315 if (reg & 0x51) { /* Not busy...check for interrupt */
316 unsigned long other_ir = port - 0x110;
317 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
318
319 /* Clear the Interrupt, Error bits on the IOC4 */
320 if (intr_reg & 0x03) {
321 writel(0x03, (void __iomem *) other_ir);
322 intr_reg = (u32) readl((void __iomem *) other_ir);
323 }
324 }
325 }
326
327 return reg;
328 }
329
330 /* Creates a dma map for the scatter-gather list entries */
331 static int __devinit
332 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
333 {
334 struct pci_dev *dev = to_pci_dev(hwif->dev);
335 void __iomem *virt_dma_base;
336 int num_ports = sizeof (ioc4_dma_regs_t);
337 void *pad;
338
339 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
340 dma_base, dma_base + num_ports - 1);
341
342 if (!request_mem_region(dma_base, num_ports, hwif->name)) {
343 printk(KERN_ERR
344 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
345 "ALREADY in use\n",
346 __FUNCTION__, hwif->name, (void *) dma_base,
347 (void *) dma_base + num_ports - 1);
348 return -1;
349 }
350
351 virt_dma_base = ioremap(dma_base, num_ports);
352 if (virt_dma_base == NULL) {
353 printk(KERN_ERR
354 "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
355 __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
356 goto dma_remap_failure;
357 }
358 hwif->dma_base = (unsigned long) virt_dma_base;
359
360 hwif->dmatable_cpu = pci_alloc_consistent(dev,
361 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
362 &hwif->dmatable_dma);
363
364 if (!hwif->dmatable_cpu)
365 goto dma_pci_alloc_failure;
366
367 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
368
369 pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
370 (dma_addr_t *) &(hwif->dma_status));
371
372 if (pad) {
373 ide_set_hwifdata(hwif, pad);
374 return 0;
375 }
376
377 pci_free_consistent(dev, IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
378 hwif->dmatable_cpu, hwif->dmatable_dma);
379 printk(KERN_INFO
380 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
381 __FUNCTION__, hwif->name);
382 printk(KERN_INFO
383 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
384
385 dma_pci_alloc_failure:
386 iounmap(virt_dma_base);
387
388 dma_remap_failure:
389 release_mem_region(dma_base, num_ports);
390
391 return -1;
392 }
393
394 /* Initializes the IOC4 DMA Engine */
395 static void
396 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
397 {
398 u32 ioc4_dma;
399 ide_hwif_t *hwif = HWIF(drive);
400 unsigned long dma_base = hwif->dma_base;
401 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
402 u32 dma_addr, ending_dma_addr;
403
404 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
405
406 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
407 printk(KERN_WARNING
408 "%s(%s):Warning!! DMA from previous transfer was still active\n",
409 __FUNCTION__, drive->name);
410 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
411 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
412
413 if (ioc4_dma & IOC4_S_DMA_STOP)
414 printk(KERN_ERR
415 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
416 __FUNCTION__, drive->name);
417 }
418
419 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
420 if (ioc4_dma & IOC4_S_DMA_ERROR) {
421 printk(KERN_WARNING
422 "%s(%s) : Warning!! - DMA Error during Previous"
423 " transfer | status 0x%x\n",
424 __FUNCTION__, drive->name, ioc4_dma);
425 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
426 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
427
428 if (ioc4_dma & IOC4_S_DMA_STOP)
429 printk(KERN_ERR
430 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
431 __FUNCTION__, drive->name);
432 }
433
434 /* Address of the Scatter Gather List */
435 dma_addr = cpu_to_le32(hwif->dmatable_dma);
436 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
437
438 /* Address of the Ending DMA */
439 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
440 ending_dma_addr = cpu_to_le32(hwif->dma_status);
441 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
442
443 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
444 drive->waiting_for_dma = 1;
445 }
446
447 /* IOC4 Scatter Gather list Format */
448 /* 128 Bit entries to support 64 bit addresses in the future */
449 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
450 /* --------------------------------------------------------------------- */
451 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
452 /* --------------------------------------------------------------------- */
453 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
454 /* --------------------------------------------------------------------- */
455 /* Creates the scatter gather list, DMA Table */
456 static unsigned int
457 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
458 {
459 ide_hwif_t *hwif = HWIF(drive);
460 unsigned int *table = hwif->dmatable_cpu;
461 unsigned int count = 0, i = 1;
462 struct scatterlist *sg;
463
464 hwif->sg_nents = i = ide_build_sglist(drive, rq);
465
466 if (!i)
467 return 0; /* sglist of length Zero */
468
469 sg = hwif->sg_table;
470 while (i && sg_dma_len(sg)) {
471 dma_addr_t cur_addr;
472 int cur_len;
473 cur_addr = sg_dma_address(sg);
474 cur_len = sg_dma_len(sg);
475
476 while (cur_len) {
477 if (count++ >= IOC4_PRD_ENTRIES) {
478 printk(KERN_WARNING
479 "%s: DMA table too small\n",
480 drive->name);
481 goto use_pio_instead;
482 } else {
483 u32 bcount =
484 0x10000 - (cur_addr & 0xffff);
485
486 if (bcount > cur_len)
487 bcount = cur_len;
488
489 /* put the addr, length in
490 * the IOC4 dma-table format */
491 *table = 0x0;
492 table++;
493 *table = cpu_to_be32(cur_addr);
494 table++;
495 *table = 0x0;
496 table++;
497
498 *table = cpu_to_be32(bcount);
499 table++;
500
501 cur_addr += bcount;
502 cur_len -= bcount;
503 }
504 }
505
506 sg = sg_next(sg);
507 i--;
508 }
509
510 if (count) {
511 table--;
512 *table |= cpu_to_be32(0x80000000);
513 return count;
514 }
515
516 use_pio_instead:
517 ide_destroy_dmatable(drive);
518
519 return 0; /* revert to PIO for this request */
520 }
521
522 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
523 {
524 struct request *rq = HWGROUP(drive)->rq;
525 unsigned int count = 0;
526 int ddir;
527
528 if (rq_data_dir(rq))
529 ddir = PCI_DMA_TODEVICE;
530 else
531 ddir = PCI_DMA_FROMDEVICE;
532
533 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
534 /* try PIO instead of DMA */
535 ide_map_sg(drive, rq);
536 return 1;
537 }
538
539 if (rq_data_dir(rq))
540 /* Writes TO the IOC4 FROM Main Memory */
541 ddir = IOC4_DMA_READ;
542 else
543 /* Writes FROM the IOC4 TO Main Memory */
544 ddir = IOC4_DMA_WRITE;
545
546 sgiioc4_configure_for_dma(ddir, drive);
547
548 return 0;
549 }
550
551 static void __devinit
552 ide_init_sgiioc4(ide_hwif_t * hwif)
553 {
554 hwif->mmio = 1;
555 hwif->INB = &sgiioc4_INB;
556
557 if (hwif->dma_base == 0)
558 return;
559
560 hwif->dma_host_set = &sgiioc4_dma_host_set;
561 hwif->dma_setup = &sgiioc4_ide_dma_setup;
562 hwif->dma_start = &sgiioc4_ide_dma_start;
563 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
564 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
565 hwif->dma_lost_irq = &sgiioc4_dma_lost_irq;
566 hwif->dma_timeout = &ide_dma_timeout;
567 }
568
569 static const struct ide_port_ops sgiioc4_port_ops = {
570 .set_dma_mode = sgiioc4_set_dma_mode,
571 /* reset DMA engine, clear IRQs */
572 .resetproc = sgiioc4_resetproc,
573 /* mask on/off NIEN register */
574 .maskproc = sgiioc4_maskproc,
575 };
576
577 static const struct ide_port_info sgiioc4_port_info __devinitdata = {
578 .chipset = ide_pci,
579 .port_ops = &sgiioc4_port_ops,
580 .host_flags = IDE_HFLAG_NO_DMA | /* no SFF-style DMA */
581 IDE_HFLAG_NO_AUTOTUNE,
582 .mwdma_mask = ATA_MWDMA2_ONLY,
583 };
584
585 static int __devinit
586 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
587 {
588 unsigned long cmd_base, dma_base, irqport;
589 unsigned long bar0, cmd_phys_base, ctl;
590 void __iomem *virt_base;
591 ide_hwif_t *hwif;
592 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
593 hw_regs_t hw;
594 struct ide_port_info d = sgiioc4_port_info;
595
596 hwif = ide_find_port();
597 if (hwif == NULL) {
598 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n",
599 DRV_NAME);
600 return -ENOMEM;
601 }
602
603 /* Get the CmdBlk and CtrlBlk Base Registers */
604 bar0 = pci_resource_start(dev, 0);
605 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
606 if (virt_base == NULL) {
607 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
608 DRV_NAME, bar0);
609 return -ENOMEM;
610 }
611 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
612 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
613 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
614 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
615
616 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
617 if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
618 hwif->name)) {
619 printk(KERN_ERR
620 "%s : %s -- ERROR, Addresses "
621 "0x%p to 0x%p ALREADY in use\n",
622 __FUNCTION__, hwif->name, (void *) cmd_phys_base,
623 (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
624 return -ENOMEM;
625 }
626
627 /* Initialize the IO registers */
628 memset(&hw, 0, sizeof(hw));
629 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
630 hw.irq = dev->irq;
631 hw.chipset = ide_pci;
632 hw.dev = &dev->dev;
633 ide_init_port_hw(hwif, &hw);
634
635 hwif->dev = &dev->dev;
636
637 /* The IOC4 uses MMIO rather than Port IO. */
638 default_hwif_mmiops(hwif);
639
640 /* Initializing chipset IRQ Registers */
641 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
642
643 if (dma_base == 0 || ide_dma_sgiioc4(hwif, dma_base)) {
644 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
645 hwif->name, DRV_NAME);
646 d.mwdma_mask = 0;
647 }
648
649 ide_init_sgiioc4(hwif);
650
651 idx[0] = hwif->index;
652
653 if (ide_device_add(idx, &d))
654 return -EIO;
655
656 return 0;
657 }
658
659 static unsigned int __devinit
660 pci_init_sgiioc4(struct pci_dev *dev)
661 {
662 int ret;
663
664 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
665 DRV_NAME, pci_name(dev), dev->revision);
666
667 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
668 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
669 "firmware is obsolete - please upgrade to "
670 "revision46 or higher\n",
671 DRV_NAME, pci_name(dev));
672 ret = -EAGAIN;
673 goto out;
674 }
675 ret = sgiioc4_ide_setup_pci_device(dev);
676 out:
677 return ret;
678 }
679
680 int
681 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
682 {
683 /* PCI-RT does not bring out IDE connection.
684 * Do not attach to this particular IOC4.
685 */
686 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
687 return 0;
688
689 return pci_init_sgiioc4(idd->idd_pdev);
690 }
691
692 static struct ioc4_submodule ioc4_ide_submodule = {
693 .is_name = "IOC4_ide",
694 .is_owner = THIS_MODULE,
695 .is_probe = ioc4_ide_attach_one,
696 /* .is_remove = ioc4_ide_remove_one, */
697 };
698
699 static int __init ioc4_ide_init(void)
700 {
701 return ioc4_register_submodule(&ioc4_ide_submodule);
702 }
703
704 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
705
706 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
707 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
708 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)