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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ide / pci / serverworks.c
1 /*
2 * linux/drivers/ide/pci/serverworks.c Version 0.11 Jun 2 2007
3 *
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Portions copyright (c) 2001 Sun Microsystems
9 *
10 *
11 * RCC/ServerWorks IDE driver for Linux
12 *
13 * OSB4: `Open South Bridge' IDE Interface (fn 1)
14 * supports UDMA mode 2 (33 MB/s)
15 *
16 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
17 * all revisions support UDMA mode 4 (66 MB/s)
18 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
19 *
20 * *** The CSB5 does not provide ANY register ***
21 * *** to detect 80-conductor cable presence. ***
22 *
23 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
24 *
25 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
26 * controller same as the CSB6. Single channel ATA100 only.
27 *
28 * Documentation:
29 * Available under NDA only. Errata info very hard to get.
30 *
31 */
32
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/hdreg.h>
39 #include <linux/ide.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42
43 #include <asm/io.h>
44
45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
47
48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
49 * can overrun their FIFOs when used with the CSB5 */
50 static const char *svwks_bad_ata100[] = {
51 "ST320011A",
52 "ST340016A",
53 "ST360021A",
54 "ST380021A",
55 NULL
56 };
57
58 static u8 svwks_revision = 0;
59 static struct pci_dev *isa_dev;
60
61 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
62 {
63 while (*list)
64 if (!strcmp(*list++, drive->id->model))
65 return 1;
66 return 0;
67 }
68
69 static u8 svwks_udma_filter(ide_drive_t *drive)
70 {
71 struct pci_dev *dev = HWIF(drive)->pci_dev;
72 u8 mask = 0;
73
74 if (!svwks_revision)
75 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
76
77 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
78 return 0x1f;
79 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
80 u32 reg = 0;
81 if (isa_dev)
82 pci_read_config_dword(isa_dev, 0x64, &reg);
83
84 /*
85 * Don't enable UDMA on disk devices for the moment
86 */
87 if(drive->media == ide_disk)
88 return 0;
89 /* Check the OSB4 DMA33 enable bit */
90 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
91 } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
92 return 0x07;
93 } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
94 u8 btr = 0, mode;
95 pci_read_config_byte(dev, 0x5A, &btr);
96 mode = btr & 0x3;
97
98 /* If someone decides to do UDMA133 on CSB5 the same
99 issue will bite so be inclusive */
100 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
101 mode = 2;
102
103 switch(mode) {
104 case 2: mask = 0x1f; break;
105 case 1: mask = 0x07; break;
106 default: mask = 0x00; break;
107 }
108 }
109 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
110 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
111 (!(PCI_FUNC(dev->devfn) & 1)))
112 mask = 0x1f;
113
114 return mask;
115 }
116
117 static u8 svwks_csb_check (struct pci_dev *dev)
118 {
119 switch (dev->device) {
120 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
121 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
122 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
123 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
124 return 1;
125 default:
126 break;
127 }
128 return 0;
129 }
130 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
131 {
132 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
133 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
134 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
135 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
136 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
137
138 ide_hwif_t *hwif = HWIF(drive);
139 struct pci_dev *dev = hwif->pci_dev;
140 u8 speed = ide_rate_filter(drive, xferspeed);
141 u8 pio = ide_get_best_pio_mode(drive, 255, 4, NULL);
142 u8 unit = (drive->select.b.unit & 0x01);
143 u8 csb5 = svwks_csb_check(dev);
144 u8 ultra_enable = 0, ultra_timing = 0;
145 u8 dma_timing = 0, pio_timing = 0;
146 u16 csb5_pio = 0;
147
148 /* If we are about to put a disk into UDMA mode we screwed up.
149 Our code assumes we never _ever_ do this on an OSB4 */
150
151 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
152 drive->media == ide_disk && speed >= XFER_UDMA_0)
153 BUG();
154
155 pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
156 pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
157 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
158 pci_read_config_word(dev, 0x4A, &csb5_pio);
159 pci_read_config_byte(dev, 0x54, &ultra_enable);
160
161 /* If we are in RAID mode (eg AMI MegaIDE) then we can't it
162 turns out trust the firmware configuration */
163
164 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
165 goto oem_setup_failed;
166
167 /* Per Specified Design by OEM, and ASIC Architect */
168 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
169 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
170 if (!drive->init_speed) {
171 u8 dma_stat = inb(hwif->dma_status);
172
173 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
174 ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
175 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
176 return 0;
177 } else if ((dma_timing) &&
178 ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
179 u8 dmaspeed;
180
181 switch (dma_timing & 0x77) {
182 case 0x20:
183 dmaspeed = XFER_MW_DMA_2;
184 break;
185 case 0x21:
186 dmaspeed = XFER_MW_DMA_1;
187 break;
188 case 0x77:
189 dmaspeed = XFER_MW_DMA_0;
190 break;
191 default:
192 goto dma_pio;
193 }
194
195 drive->current_speed = drive->init_speed = dmaspeed;
196 return 0;
197 }
198 dma_pio:
199 if (pio_timing) {
200 u8 piospeed;
201
202 switch (pio_timing & 0x7f) {
203 case 0x20:
204 piospeed = XFER_PIO_4;
205 break;
206 case 0x22:
207 piospeed = XFER_PIO_3;
208 break;
209 case 0x34:
210 piospeed = XFER_PIO_2;
211 break;
212 case 0x47:
213 piospeed = XFER_PIO_1;
214 break;
215 case 0x5d:
216 piospeed = XFER_PIO_0;
217 break;
218 default:
219 goto oem_setup_failed;
220 }
221
222 drive->current_speed = drive->init_speed = piospeed;
223 return 0;
224 }
225 }
226 }
227
228 oem_setup_failed:
229
230 pio_timing = 0;
231 dma_timing = 0;
232 ultra_timing &= ~(0x0F << (4*unit));
233 ultra_enable &= ~(0x01 << drive->dn);
234 csb5_pio &= ~(0x0F << (4*drive->dn));
235
236 switch(speed) {
237 case XFER_PIO_4:
238 case XFER_PIO_3:
239 case XFER_PIO_2:
240 case XFER_PIO_1:
241 case XFER_PIO_0:
242 pio_timing |= pio_modes[speed - XFER_PIO_0];
243 csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn));
244 break;
245
246 case XFER_MW_DMA_2:
247 case XFER_MW_DMA_1:
248 case XFER_MW_DMA_0:
249 /*
250 * TODO: always setup PIO mode so this won't be needed
251 */
252 pio_timing |= pio_modes[pio];
253 csb5_pio |= (pio << (4*drive->dn));
254 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
255 break;
256
257 case XFER_UDMA_5:
258 case XFER_UDMA_4:
259 case XFER_UDMA_3:
260 case XFER_UDMA_2:
261 case XFER_UDMA_1:
262 case XFER_UDMA_0:
263 /*
264 * TODO: always setup PIO mode so this won't be needed
265 */
266 pio_timing |= pio_modes[pio];
267 csb5_pio |= (pio << (4*drive->dn));
268 dma_timing |= dma_modes[2];
269 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
270 ultra_enable |= (0x01 << drive->dn);
271 default:
272 break;
273 }
274
275 pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
276 if (csb5)
277 pci_write_config_word(dev, 0x4A, csb5_pio);
278
279 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
280 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
281 pci_write_config_byte(dev, 0x54, ultra_enable);
282
283 return (ide_config_drive_speed(drive, speed));
284 }
285
286 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
287 {
288 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
289 (void)svwks_tune_chipset(drive, XFER_PIO_0 + pio);
290 }
291
292 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
293 {
294 drive->init_speed = 0;
295
296 if (ide_tune_dma(drive))
297 return 0;
298
299 if (ide_use_fast_pio(drive))
300 svwks_tune_drive(drive, 255);
301
302 return -1;
303 }
304
305 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
306 {
307 unsigned int reg;
308 u8 btr;
309
310 /* save revision id to determine DMA capability */
311 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
312
313 /* force Master Latency Timer value to 64 PCICLKs */
314 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
315
316 /* OSB4 : South Bridge and IDE */
317 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
318 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
319 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
320 if (isa_dev) {
321 pci_read_config_dword(isa_dev, 0x64, &reg);
322 reg &= ~0x00002000; /* disable 600ns interrupt mask */
323 if(!(reg & 0x00004000))
324 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
325 reg |= 0x00004000; /* enable UDMA/33 support */
326 pci_write_config_dword(isa_dev, 0x64, reg);
327 }
328 }
329
330 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
331 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
332 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
333 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
334
335 /* Third Channel Test */
336 if (!(PCI_FUNC(dev->devfn) & 1)) {
337 struct pci_dev * findev = NULL;
338 u32 reg4c = 0;
339 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
340 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
341 if (findev) {
342 pci_read_config_dword(findev, 0x4C, &reg4c);
343 reg4c &= ~0x000007FF;
344 reg4c |= 0x00000040;
345 reg4c |= 0x00000020;
346 pci_write_config_dword(findev, 0x4C, reg4c);
347 pci_dev_put(findev);
348 }
349 outb_p(0x06, 0x0c00);
350 dev->irq = inb_p(0x0c01);
351 } else {
352 struct pci_dev * findev = NULL;
353 u8 reg41 = 0;
354
355 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
356 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
357 if (findev) {
358 pci_read_config_byte(findev, 0x41, &reg41);
359 reg41 &= ~0x40;
360 pci_write_config_byte(findev, 0x41, reg41);
361 pci_dev_put(findev);
362 }
363 /*
364 * This is a device pin issue on CSB6.
365 * Since there will be a future raid mode,
366 * early versions of the chipset require the
367 * interrupt pin to be set, and it is a compatibility
368 * mode issue.
369 */
370 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
371 dev->irq = 0;
372 }
373 // pci_read_config_dword(dev, 0x40, &pioreg)
374 // pci_write_config_dword(dev, 0x40, 0x99999999);
375 // pci_read_config_dword(dev, 0x44, &dmareg);
376 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
377 /* setup the UDMA Control register
378 *
379 * 1. clear bit 6 to enable DMA
380 * 2. enable DMA modes with bits 0-1
381 * 00 : legacy
382 * 01 : udma2
383 * 10 : udma2/udma4
384 * 11 : udma2/udma4/udma5
385 */
386 pci_read_config_byte(dev, 0x5A, &btr);
387 btr &= ~0x40;
388 if (!(PCI_FUNC(dev->devfn) & 1))
389 btr |= 0x2;
390 else
391 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
392 pci_write_config_byte(dev, 0x5A, btr);
393 }
394 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
395 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
396 pci_read_config_byte(dev, 0x5A, &btr);
397 btr &= ~0x40;
398 btr |= 0x3;
399 pci_write_config_byte(dev, 0x5A, btr);
400 }
401
402 return dev->irq;
403 }
404
405 static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
406 {
407 return 1;
408 }
409
410 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
411 * of the subsystem device ID indicate presence of an 80-pin cable.
412 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
413 * Bit 15 set = secondary IDE channel has 80-pin cable.
414 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
415 * Bit 14 set = primary IDE channel has 80-pin cable.
416 */
417 static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
418 {
419 struct pci_dev *dev = hwif->pci_dev;
420 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
421 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
422 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
423 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
424 return ((1 << (hwif->channel + 14)) &
425 dev->subsystem_device) ? 1 : 0;
426 return 0;
427 }
428
429 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
430 * detect issue by attaching the drives directly to the board.
431 * This check follows the Dell precedent (how scary is that?!)
432 *
433 * WARNING: this only works on Alpine hardware!
434 */
435 static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
436 {
437 struct pci_dev *dev = hwif->pci_dev;
438 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
439 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
440 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
441 return ((1 << (hwif->channel + 14)) &
442 dev->subsystem_device) ? 1 : 0;
443 return 0;
444 }
445
446 static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
447 {
448 struct pci_dev *dev = hwif->pci_dev;
449
450 /* Server Works */
451 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
452 return ata66_svwks_svwks (hwif);
453
454 /* Dell PowerEdge */
455 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
456 return ata66_svwks_dell (hwif);
457
458 /* Cobalt Alpine */
459 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
460 return ata66_svwks_cobalt (hwif);
461
462 /* Per Specified Design by OEM, and ASIC Architect */
463 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
464 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
465 return 1;
466
467 return 0;
468 }
469
470 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
471 {
472 u8 dma_stat = 0;
473
474 if (!hwif->irq)
475 hwif->irq = hwif->channel ? 15 : 14;
476
477 hwif->tuneproc = &svwks_tune_drive;
478 hwif->speedproc = &svwks_tune_chipset;
479 hwif->udma_filter = &svwks_udma_filter;
480
481 hwif->atapi_dma = 1;
482
483 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
484 hwif->ultra_mask = 0x3f;
485
486 hwif->mwdma_mask = 0x07;
487
488 hwif->autodma = 0;
489
490 if (!hwif->dma_base) {
491 hwif->drives[0].autotune = 1;
492 hwif->drives[1].autotune = 1;
493 return;
494 }
495
496 hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
497 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
498 if (!hwif->udma_four)
499 hwif->udma_four = ata66_svwks(hwif);
500 }
501 if (!noautodma)
502 hwif->autodma = 1;
503
504 dma_stat = inb(hwif->dma_status);
505 hwif->drives[0].autodma = (dma_stat & 0x20);
506 hwif->drives[1].autodma = (dma_stat & 0x40);
507 hwif->drives[0].autotune = (!(dma_stat & 0x20));
508 hwif->drives[1].autotune = (!(dma_stat & 0x40));
509 }
510
511 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
512 {
513 return ide_setup_pci_device(dev, d);
514 }
515
516 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
517 {
518 if (!(PCI_FUNC(dev->devfn) & 1)) {
519 d->bootable = NEVER_BOARD;
520 if (dev->resource[0].start == 0x01f1)
521 d->bootable = ON_BOARD;
522 }
523
524 d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
525 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
526 (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
527
528 return ide_setup_pci_device(dev, d);
529 }
530
531 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
532 { /* 0 */
533 .name = "SvrWks OSB4",
534 .init_setup = init_setup_svwks,
535 .init_chipset = init_chipset_svwks,
536 .init_hwif = init_hwif_svwks,
537 .channels = 2,
538 .autodma = AUTODMA,
539 .bootable = ON_BOARD,
540 },{ /* 1 */
541 .name = "SvrWks CSB5",
542 .init_setup = init_setup_svwks,
543 .init_chipset = init_chipset_svwks,
544 .init_hwif = init_hwif_svwks,
545 .channels = 2,
546 .autodma = AUTODMA,
547 .bootable = ON_BOARD,
548 },{ /* 2 */
549 .name = "SvrWks CSB6",
550 .init_setup = init_setup_csb6,
551 .init_chipset = init_chipset_svwks,
552 .init_hwif = init_hwif_svwks,
553 .channels = 2,
554 .autodma = AUTODMA,
555 .bootable = ON_BOARD,
556 },{ /* 3 */
557 .name = "SvrWks CSB6",
558 .init_setup = init_setup_csb6,
559 .init_chipset = init_chipset_svwks,
560 .init_hwif = init_hwif_svwks,
561 .channels = 1, /* 2 */
562 .autodma = AUTODMA,
563 .bootable = ON_BOARD,
564 },{ /* 4 */
565 .name = "SvrWks HT1000",
566 .init_setup = init_setup_svwks,
567 .init_chipset = init_chipset_svwks,
568 .init_hwif = init_hwif_svwks,
569 .channels = 1, /* 2 */
570 .autodma = AUTODMA,
571 .bootable = ON_BOARD,
572 }
573 };
574
575 /**
576 * svwks_init_one - called when a OSB/CSB is found
577 * @dev: the svwks device
578 * @id: the matching pci id
579 *
580 * Called when the PCI registration layer (or the IDE initialization)
581 * finds a device matching our IDE device tables.
582 */
583
584 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
585 {
586 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
587
588 return d->init_setup(dev, d);
589 }
590
591 static struct pci_device_id svwks_pci_tbl[] = {
592 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
593 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
594 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
595 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
596 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
597 { 0, },
598 };
599 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
600
601 static struct pci_driver driver = {
602 .name = "Serverworks_IDE",
603 .id_table = svwks_pci_tbl,
604 .probe = svwks_init_one,
605 };
606
607 static int __init svwks_ide_init(void)
608 {
609 return ide_pci_register_driver(&driver);
610 }
611
612 module_init(svwks_ide_init);
613
614 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
615 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
616 MODULE_LICENSE("GPL");