drivers/ide/pci/serverworks.c

   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.22    Jun 27 2007
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   8  * Portions copyright (c) 2001 Sun Microsystems
   9  *
  10  *
  11  * RCC/ServerWorks IDE driver for Linux
  12  *
  13  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  14  *         supports UDMA mode 2 (33 MB/s)
  15  *
  16  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  17  *         all revisions support UDMA mode 4 (66 MB/s)
  18  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  19  *
  20  *         *** The CSB5 does not provide ANY register ***
  21  *         *** to detect 80-conductor cable presence. ***
  22  *
  23  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  24  *
  25  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  26  *   controller same as the CSB6. Single channel ATA100 only.
  27  *
  28  * Documentation:
  29  *      Available under NDA only. Errata info very hard to get.
  30  *
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/pci.h>
  38 #include <linux/hdreg.h>
  39 #include <linux/ide.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42
  43 #include <asm/io.h>
  44
  45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  46 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  47
  48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  49  * can overrun their FIFOs when used with the CSB5 */
  50 static const char *svwks_bad_ata100[] = {
  51         "ST320011A",
  52         "ST340016A",
  53         "ST360021A",
  54         "ST380021A",
  55         NULL
  56 };
  57
  58 static struct pci_dev *isa_dev;
  59
  60 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  61 {
  62         while (*list)
  63                 if (!strcmp(*list++, drive->id->model))
  64                         return 1;
  65         return 0;
  66 }
  67
  68 static u8 svwks_udma_filter(ide_drive_t *drive)
  69 {
  70         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  71         u8 mask = 0;
  72
  73         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  74                 return 0x1f;
  75         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  76                 u32 reg = 0;
  77                 if (isa_dev)
  78                         pci_read_config_dword(isa_dev, 0x64, &reg);
  79
  80                 /*
  81                  *      Don't enable UDMA on disk devices for the moment
  82                  */
  83                 if(drive->media == ide_disk)
  84                         return 0;
  85                 /* Check the OSB4 DMA33 enable bit */
  86                 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  87         } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  88                 return 0x07;
  89         } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
  90                 u8 btr = 0, mode;
  91                 pci_read_config_byte(dev, 0x5A, &btr);
  92                 mode = btr & 0x3;
  93
  94                 /* If someone decides to do UDMA133 on CSB5 the same
  95                    issue will bite so be inclusive */
  96                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  97                         mode = 2;
  98
  99                 switch(mode) {
 100                 case 3:  mask = 0x3f; break;
 101                 case 2:  mask = 0x1f; break;
 102                 case 1:  mask = 0x07; break;
 103                 default: mask = 0x00; break;
 104                 }
 105         }
 106         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 107              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 108             (!(PCI_FUNC(dev->devfn) & 1)))
 109                 mask = 0x1f;
 110
 111         return mask;
 112 }
 113
 114 static u8 svwks_csb_check (struct pci_dev *dev)
 115 {
 116         switch (dev->device) {
 117                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 118                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 119                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 120                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 121                         return 1;
 122                 default:
 123                         break;
 124         }
 125         return 0;
 126 }
 127
 128 static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
 129 {
 130         static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 131         static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
 132
 133         struct pci_dev *dev = drive->hwif->pci_dev;
 134
 135         pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
 136
 137         if (svwks_csb_check(dev)) {
 138                 u16 csb_pio = 0;
 139
 140                 pci_read_config_word(dev, 0x4a, &csb_pio);
 141
 142                 csb_pio &= ~(0x0f << (4 * drive->dn));
 143                 csb_pio |= (pio << (4 * drive->dn));
 144
 145                 pci_write_config_word(dev, 0x4a, csb_pio);
 146         }
 147 }
 148
 149 static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
 150 {
 151         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 152         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 153         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 154
 155         ide_hwif_t *hwif        = HWIF(drive);
 156         struct pci_dev *dev     = hwif->pci_dev;
 157         u8 unit                 = (drive->select.b.unit & 0x01);
 158
 159         u8 ultra_enable  = 0, ultra_timing = 0, dma_timing = 0;
 160
 161         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 162         pci_read_config_byte(dev, 0x54, &ultra_enable);
 163
 164         ultra_timing    &= ~(0x0F << (4*unit));
 165         ultra_enable    &= ~(0x01 << drive->dn);
 166
 167         if (speed >= XFER_UDMA_0) {
 168                 dma_timing   |= dma_modes[2];
 169                 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
 170                 ultra_enable |= (0x01 << drive->dn);
 171         } else if (speed >= XFER_MW_DMA_0)
 172                 dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];
 173
 174         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 175         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 176         pci_write_config_byte(dev, 0x54, ultra_enable);
 177 }
 178
 179 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 180 {
 181         unsigned int reg;
 182         u8 btr;
 183
 184         /* force Master Latency Timer value to 64 PCICLKs */
 185         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 186
 187         /* OSB4 : South Bridge and IDE */
 188         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 189                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 190                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 191                 if (isa_dev) {
 192                         pci_read_config_dword(isa_dev, 0x64, &reg);
 193                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 194                         if(!(reg & 0x00004000))
 195                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 196                         reg |=  0x00004000; /* enable UDMA/33 support */
 197                         pci_write_config_dword(isa_dev, 0x64, reg);
 198                 }
 199         }
 200
 201         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 202         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 203                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 204                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 205
 206                 /* Third Channel Test */
 207                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 208                         struct pci_dev * findev = NULL;
 209                         u32 reg4c = 0;
 210                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 211                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 212                         if (findev) {
 213                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 214                                 reg4c &= ~0x000007FF;
 215                                 reg4c |=  0x00000040;
 216                                 reg4c |=  0x00000020;
 217                                 pci_write_config_dword(findev, 0x4C, reg4c);
 218                                 pci_dev_put(findev);
 219                         }
 220                         outb_p(0x06, 0x0c00);
 221                         dev->irq = inb_p(0x0c01);
 222                 } else {
 223                         struct pci_dev * findev = NULL;
 224                         u8 reg41 = 0;
 225
 226                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 227                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 228                         if (findev) {
 229                                 pci_read_config_byte(findev, 0x41, &reg41);
 230                                 reg41 &= ~0x40;
 231                                 pci_write_config_byte(findev, 0x41, reg41);
 232                                 pci_dev_put(findev);
 233                         }
 234                         /*
 235                          * This is a device pin issue on CSB6.
 236                          * Since there will be a future raid mode,
 237                          * early versions of the chipset require the
 238                          * interrupt pin to be set, and it is a compatibility
 239                          * mode issue.
 240                          */
 241                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 242                                 dev->irq = 0;
 243                 }
 244 //              pci_read_config_dword(dev, 0x40, &pioreg)
 245 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 246 //              pci_read_config_dword(dev, 0x44, &dmareg);
 247 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 248                 /* setup the UDMA Control register
 249                  *
 250                  * 1. clear bit 6 to enable DMA
 251                  * 2. enable DMA modes with bits 0-1
 252                  *      00 : legacy
 253                  *      01 : udma2
 254                  *      10 : udma2/udma4
 255                  *      11 : udma2/udma4/udma5
 256                  */
 257                 pci_read_config_byte(dev, 0x5A, &btr);
 258                 btr &= ~0x40;
 259                 if (!(PCI_FUNC(dev->devfn) & 1))
 260                         btr |= 0x2;
 261                 else
 262                         btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 263                 pci_write_config_byte(dev, 0x5A, btr);
 264         }
 265         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 266         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 267                 pci_read_config_byte(dev, 0x5A, &btr);
 268                 btr &= ~0x40;
 269                 btr |= 0x3;
 270                 pci_write_config_byte(dev, 0x5A, btr);
 271         }
 272
 273         return dev->irq;
 274 }
 275
 276 static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
 277 {
 278         return ATA_CBL_PATA80;
 279 }
 280
 281 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 282  * of the subsystem device ID indicate presence of an 80-pin cable.
 283  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 284  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 285  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 286  * Bit 14 set   = primary IDE channel has 80-pin cable.
 287  */
 288 static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
 289 {
 290         struct pci_dev *dev = hwif->pci_dev;
 291         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 292             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 293             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 294              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 295                 return ((1 << (hwif->channel + 14)) &
 296                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 297         return ATA_CBL_PATA40;
 298 }
 299
 300 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 301  * detect issue by attaching the drives directly to the board.
 302  * This check follows the Dell precedent (how scary is that?!)
 303  *
 304  * WARNING: this only works on Alpine hardware!
 305  */
 306 static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
 307 {
 308         struct pci_dev *dev = hwif->pci_dev;
 309         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 310             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 311             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 312                 return ((1 << (hwif->channel + 14)) &
 313                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 314         return ATA_CBL_PATA40;
 315 }
 316
 317 static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
 318 {
 319         struct pci_dev *dev = hwif->pci_dev;
 320
 321         /* Server Works */
 322         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 323                 return ata66_svwks_svwks (hwif);
 324
 325         /* Dell PowerEdge */
 326         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 327                 return ata66_svwks_dell (hwif);
 328
 329         /* Cobalt Alpine */
 330         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 331                 return ata66_svwks_cobalt (hwif);
 332
 333         /* Per Specified Design by OEM, and ASIC Architect */
 334         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 335             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 336                 return ATA_CBL_PATA80;
 337
 338         return ATA_CBL_PATA40;
 339 }
 340
 341 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 342 {
 343         hwif->set_pio_mode = &svwks_set_pio_mode;
 344         hwif->set_dma_mode = &svwks_set_dma_mode;
 345         hwif->udma_filter = &svwks_udma_filter;
 346
 347         if (!hwif->dma_base)
 348                 return;
 349
 350         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 351                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 352                         hwif->cbl = ata66_svwks(hwif);
 353         }
 354 }
 355
 356 #define IDE_HFLAGS_SVWKS \
 357         (IDE_HFLAG_LEGACY_IRQS | \
 358          IDE_HFLAG_ABUSE_SET_DMA_MODE | \
 359          IDE_HFLAG_BOOTABLE)
 360
 361 static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
 362         {       /* 0 */
 363                 .name           = "SvrWks OSB4",
 364                 .init_chipset   = init_chipset_svwks,
 365                 .init_hwif      = init_hwif_svwks,
 366                 .host_flags     = IDE_HFLAGS_SVWKS,
 367                 .pio_mask       = ATA_PIO4,
 368                 .mwdma_mask     = ATA_MWDMA2,
 369                 .udma_mask      = 0x00, /* UDMA is problematic on OSB4 */
 370         },{     /* 1 */
 371                 .name           = "SvrWks CSB5",
 372                 .init_chipset   = init_chipset_svwks,
 373                 .init_hwif      = init_hwif_svwks,
 374                 .host_flags     = IDE_HFLAGS_SVWKS,
 375                 .pio_mask       = ATA_PIO4,
 376                 .mwdma_mask     = ATA_MWDMA2,
 377                 .udma_mask      = ATA_UDMA5,
 378         },{     /* 2 */
 379                 .name           = "SvrWks CSB6",
 380                 .init_chipset   = init_chipset_svwks,
 381                 .init_hwif      = init_hwif_svwks,
 382                 .host_flags     = IDE_HFLAGS_SVWKS,
 383                 .pio_mask       = ATA_PIO4,
 384                 .mwdma_mask     = ATA_MWDMA2,
 385                 .udma_mask      = ATA_UDMA5,
 386         },{     /* 3 */
 387                 .name           = "SvrWks CSB6",
 388                 .init_chipset   = init_chipset_svwks,
 389                 .init_hwif      = init_hwif_svwks,
 390                 .host_flags     = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
 391                 .pio_mask       = ATA_PIO4,
 392                 .mwdma_mask     = ATA_MWDMA2,
 393                 .udma_mask      = ATA_UDMA5,
 394         },{     /* 4 */
 395                 .name           = "SvrWks HT1000",
 396                 .init_chipset   = init_chipset_svwks,
 397                 .init_hwif      = init_hwif_svwks,
 398                 .host_flags     = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
 399                 .pio_mask       = ATA_PIO4,
 400                 .mwdma_mask     = ATA_MWDMA2,
 401                 .udma_mask      = ATA_UDMA5,
 402         }
 403 };
 404
 405 /**
 406  *      svwks_init_one  -       called when a OSB/CSB is found
 407  *      @dev: the svwks device
 408  *      @id: the matching pci id
 409  *
 410  *      Called when the PCI registration layer (or the IDE initialization)
 411  *      finds a device matching our IDE device tables.
 412  */
 413
 414 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 415 {
 416         struct ide_port_info d;
 417         u8 idx = id->driver_data;
 418
 419         d = serverworks_chipsets[idx];
 420
 421         if (idx == 1)
 422                 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
 423         else if (idx == 2 || idx == 3) {
 424                 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
 425                         if (pci_resource_start(dev, 0) != 0x01f1)
 426                                 d.host_flags &= ~IDE_HFLAG_BOOTABLE;
 427                         d.host_flags |= IDE_HFLAG_SINGLE;
 428                 } else
 429                         d.host_flags &= ~IDE_HFLAG_SINGLE;
 430         }
 431
 432         return ide_setup_pci_device(dev, &d);
 433 }
 434
 435 static const struct pci_device_id svwks_pci_tbl[] = {
 436         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
 437         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
 438         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
 439         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
 440         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
 441         { 0, },
 442 };
 443 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 444
 445 static struct pci_driver driver = {
 446         .name           = "Serverworks_IDE",
 447         .id_table       = svwks_pci_tbl,
 448         .probe          = svwks_init_one,
 449 };
 450
 451 static int __init svwks_ide_init(void)
 452 {
 453         return ide_pci_register_driver(&driver);
 454 }
 455
 456 module_init(svwks_ide_init);
 457
 458 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 459 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 460 MODULE_LICENSE("GPL");