2 * linux/drivers/ide/pci/piix.c Version 0.46 December 3, 2006
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
7 * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
9 * May be copied or modified under the terms of the GNU General Public License
11 * PIO mode setting function for Intel chipsets.
12 * For use instead of BIOS settings.
20 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
21 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
22 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
23 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
25 * sitre = word40 & 0x4000; primary
26 * sitre = word42 & 0x4000; secondary
28 * 44 8421|8421 hdd|hdb
30 * 48 8421 hdd|hdc|hdb|hda udma enabled
42 * ata-33/82801AB ata-66/82801AA
43 * 00|00 udma 0 00|00 reserved
44 * 01|01 udma 1 01|01 udma 3
45 * 10|10 udma 2 10|10 udma 4
46 * 11|11 reserved 11|11 reserved
48 * 54 8421|8421 ata66 drive|ata66 enable
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
53 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
54 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
55 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
58 * Publically available from Intel web site. Errata documentation
59 * is also publically available. As an aide to anyone hacking on this
60 * driver the list of errata that are relevant is below.going back to
61 * PIIX4. Older device documentation is now a bit tricky to find.
66 * PIIX4 errata #9 - Only on ultra obscure hw
67 * ICH3 errata #13 - Not observed to affect real hw
70 * Things we must deal with
71 * PIIX4 errata #10 - BM IDE hang with non UDMA
72 * (must stop/start dma to recover)
73 * 440MX errata #15 - As PIIX4 errata #10
74 * PIIX4 errata #15 - Must not read control registers
75 * during a PIO transfer
76 * 440MX errata #13 - As PIIX4 errata #15
77 * ICH2 errata #21 - DMA mode 0 doesn't work right
78 * ICH0/1 errata #55 - As ICH2 errata #21
79 * ICH2 spec c #9 - Extra operations needed to handle
80 * drive hotswap [NOT YET SUPPORTED]
81 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
82 * and must be dword aligned
83 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
85 * Should have been BIOS fixed:
86 * 450NX: errata #19 - DMA hangs on old 450NX
87 * 450NX: errata #20 - DMA hangs on old 450NX
88 * 450NX: errata #25 - Corruption with DMA on old 450NX
89 * ICH3 errata #15 - IDE deadlock under high load
90 * (BIOS must set dev 31 fn 0 bit 23)
91 * ICH3 errata #18 - Don't use native mode
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
106 static int no_piix_dma
;
109 * piix_ratemask - compute rate mask for PIIX IDE
110 * @drive: IDE drive to compute for
112 * Returns the available modes for the PIIX IDE controller.
115 static u8
piix_ratemask (ide_drive_t
*drive
)
117 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
120 switch(dev
->device
) {
121 case PCI_DEVICE_ID_INTEL_82801EB_1
:
124 /* UDMA 100 capable */
125 case PCI_DEVICE_ID_INTEL_82801BA_8
:
126 case PCI_DEVICE_ID_INTEL_82801BA_9
:
127 case PCI_DEVICE_ID_INTEL_82801CA_10
:
128 case PCI_DEVICE_ID_INTEL_82801CA_11
:
129 case PCI_DEVICE_ID_INTEL_82801E_11
:
130 case PCI_DEVICE_ID_INTEL_82801DB_1
:
131 case PCI_DEVICE_ID_INTEL_82801DB_10
:
132 case PCI_DEVICE_ID_INTEL_82801DB_11
:
133 case PCI_DEVICE_ID_INTEL_82801EB_11
:
134 case PCI_DEVICE_ID_INTEL_ESB_2
:
135 case PCI_DEVICE_ID_INTEL_ICH6_19
:
136 case PCI_DEVICE_ID_INTEL_ICH7_21
:
137 case PCI_DEVICE_ID_INTEL_ESB2_18
:
138 case PCI_DEVICE_ID_INTEL_ICH8_6
:
141 /* UDMA 66 capable */
142 case PCI_DEVICE_ID_INTEL_82801AA_1
:
143 case PCI_DEVICE_ID_INTEL_82372FB_1
:
146 /* UDMA 33 capable */
147 case PCI_DEVICE_ID_INTEL_82371AB
:
148 case PCI_DEVICE_ID_INTEL_82443MX_1
:
149 case PCI_DEVICE_ID_INTEL_82451NX
:
150 case PCI_DEVICE_ID_INTEL_82801AB_1
:
152 /* Non UDMA capable (MWDMA2) */
153 case PCI_DEVICE_ID_INTEL_82371SB_1
:
154 case PCI_DEVICE_ID_INTEL_82371FB_1
:
155 case PCI_DEVICE_ID_INTEL_82371FB_0
:
156 case PCI_DEVICE_ID_INTEL_82371MX
:
162 * If we are UDMA66 capable fall back to UDMA33
163 * if the drive cannot see an 80pin cable.
165 if (!eighty_ninty_three(drive
))
166 mode
= min_t(u8
, mode
, 1);
171 * piix_dma_2_pio - return the PIO mode matching DMA
172 * @xfer_rate: transfer speed
174 * Returns the nearest equivalent PIO timing for the PIO or DMA
175 * mode requested by the controller.
178 static u8
piix_dma_2_pio (u8 xfer_rate
) {
208 * piix_tune_drive - tune a drive attached to a PIIX
209 * @drive: drive to tune
210 * @pio: desired PIO mode
212 * Set the interface PIO mode based upon the settings done by AMI BIOS
213 * (might be useful if drive is not registered in CMOS for any reason).
215 static void piix_tune_drive (ide_drive_t
*drive
, u8 pio
)
217 ide_hwif_t
*hwif
= HWIF(drive
);
218 struct pci_dev
*dev
= hwif
->pci_dev
;
219 int is_slave
= drive
->dn
& 1;
220 int master_port
= hwif
->channel
? 0x42 : 0x40;
221 int slave_port
= 0x44;
225 static DEFINE_SPINLOCK(tune_lock
);
229 static const u8 timings
[][2]= {
236 pio
= ide_get_best_pio_mode(drive
, pio
, 4, NULL
);
239 * Master vs slave is synchronized above us but the slave register is
240 * shared by the two hwifs so the corner case of two slave timeouts in
241 * parallel must be locked.
243 spin_lock_irqsave(&tune_lock
, flags
);
244 pci_read_config_word(dev
, master_port
, &master_data
);
247 control
|= 1; /* Programmable timing on */
248 if (drive
->media
== ide_disk
)
249 control
|= 4; /* Prefetch, post write */
251 control
|= 2; /* IORDY */
253 master_data
|= 0x4000;
254 master_data
&= ~0x0070;
256 /* enable PPE, IE and TIME */
257 master_data
= master_data
| (control
<< 4);
259 pci_read_config_byte(dev
, slave_port
, &slave_data
);
260 slave_data
= slave_data
& (hwif
->channel
? 0x0f : 0xf0);
261 slave_data
= slave_data
| (((timings
[pio
][0] << 2) | timings
[pio
][1]) << (hwif
->channel
? 4 : 0));
263 master_data
&= ~0x3307;
265 /* enable PPE, IE and TIME */
266 master_data
= master_data
| control
;
268 master_data
= master_data
| (timings
[pio
][0] << 12) | (timings
[pio
][1] << 8);
270 pci_write_config_word(dev
, master_port
, master_data
);
272 pci_write_config_byte(dev
, slave_port
, slave_data
);
273 spin_unlock_irqrestore(&tune_lock
, flags
);
277 * piix_tune_chipset - tune a PIIX interface
278 * @drive: IDE drive to tune
279 * @xferspeed: speed to configure
281 * Set a PIIX interface channel to the desired speeds. This involves
282 * requires the right timing data into the PIIX configuration space
283 * then setting the drive parameters appropriately
286 static int piix_tune_chipset (ide_drive_t
*drive
, u8 xferspeed
)
288 ide_hwif_t
*hwif
= HWIF(drive
);
289 struct pci_dev
*dev
= hwif
->pci_dev
;
290 u8 maslave
= hwif
->channel
? 0x42 : 0x40;
291 u8 speed
= ide_rate_filter(piix_ratemask(drive
), xferspeed
);
292 int a_speed
= 3 << (drive
->dn
* 4);
293 int u_flag
= 1 << drive
->dn
;
294 int v_flag
= 0x01 << drive
->dn
;
295 int w_flag
= 0x10 << drive
->dn
;
299 u8 reg48
, reg54
, reg55
;
301 pci_read_config_word(dev
, maslave
, ®4042
);
302 sitre
= (reg4042
& 0x4000) ? 1 : 0;
303 pci_read_config_byte(dev
, 0x48, ®48
);
304 pci_read_config_word(dev
, 0x4a, ®4a
);
305 pci_read_config_byte(dev
, 0x54, ®54
);
306 pci_read_config_byte(dev
, 0x55, ®55
);
310 case XFER_UDMA_2
: u_speed
= 2 << (drive
->dn
* 4); break;
313 case XFER_UDMA_1
: u_speed
= 1 << (drive
->dn
* 4); break;
314 case XFER_UDMA_0
: u_speed
= 0 << (drive
->dn
* 4); break;
317 case XFER_SW_DMA_2
: break;
321 case XFER_PIO_0
: break;
325 if (speed
>= XFER_UDMA_0
) {
326 if (!(reg48
& u_flag
))
327 pci_write_config_byte(dev
, 0x48, reg48
| u_flag
);
328 if (speed
== XFER_UDMA_5
) {
329 pci_write_config_byte(dev
, 0x55, (u8
) reg55
|w_flag
);
331 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
333 if ((reg4a
& a_speed
) != u_speed
)
334 pci_write_config_word(dev
, 0x4a, (reg4a
& ~a_speed
) | u_speed
);
335 if (speed
> XFER_UDMA_2
) {
336 if (!(reg54
& v_flag
))
337 pci_write_config_byte(dev
, 0x54, reg54
| v_flag
);
339 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
342 pci_write_config_byte(dev
, 0x48, reg48
& ~u_flag
);
344 pci_write_config_word(dev
, 0x4a, reg4a
& ~a_speed
);
346 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
348 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
351 piix_tune_drive(drive
, piix_dma_2_pio(speed
));
352 return (ide_config_drive_speed(drive
, speed
));
356 * piix_config_drive_for_dma - configure drive for DMA
357 * @drive: IDE drive to configure
359 * Set up a PIIX interface channel for the best available speed.
360 * We prefer UDMA if it is available and then MWDMA. If DMA is
361 * not available we switch to PIO and return 0.
364 static int piix_config_drive_for_dma (ide_drive_t
*drive
)
366 u8 speed
= ide_dma_speed(drive
, piix_ratemask(drive
));
369 * If no DMA speed was available or the chipset has DMA bugs
370 * then disable DMA and use PIO
372 if (!speed
|| no_piix_dma
)
375 (void) piix_tune_chipset(drive
, speed
);
376 return ide_dma_enable(drive
);
380 * piix_config_drive_xfer_rate - set up an IDE device
381 * @drive: IDE drive to configure
383 * Set up the PIIX interface for the best available speed on this
384 * interface, preferring DMA to PIO.
387 static int piix_config_drive_xfer_rate (ide_drive_t
*drive
)
389 ide_hwif_t
*hwif
= HWIF(drive
);
390 struct hd_driveid
*id
= drive
->id
;
392 drive
->init_speed
= 0;
394 if ((id
->capability
& 1) && drive
->autodma
) {
396 if (ide_use_dma(drive
) && piix_config_drive_for_dma(drive
))
397 return hwif
->ide_dma_on(drive
);
401 } else if ((id
->capability
& 8) || (id
->field_valid
& 2)) {
403 /* Find best PIO mode. */
404 (void) hwif
->speedproc(drive
, XFER_PIO_0
+
405 ide_get_best_pio_mode(drive
, 255, 4, NULL
));
406 return hwif
->ide_dma_off_quietly(drive
);
408 /* IORDY not supported */
413 * init_chipset_piix - set up the PIIX chipset
414 * @dev: PCI device to set up
415 * @name: Name of the device
417 * Initialize the PCI device as required. For the PIIX this turns
418 * out to be nice and simple
421 static unsigned int __devinit
init_chipset_piix (struct pci_dev
*dev
, const char *name
)
423 switch(dev
->device
) {
424 case PCI_DEVICE_ID_INTEL_82801EB_1
:
425 case PCI_DEVICE_ID_INTEL_82801AA_1
:
426 case PCI_DEVICE_ID_INTEL_82801AB_1
:
427 case PCI_DEVICE_ID_INTEL_82801BA_8
:
428 case PCI_DEVICE_ID_INTEL_82801BA_9
:
429 case PCI_DEVICE_ID_INTEL_82801CA_10
:
430 case PCI_DEVICE_ID_INTEL_82801CA_11
:
431 case PCI_DEVICE_ID_INTEL_82801DB_1
:
432 case PCI_DEVICE_ID_INTEL_82801DB_10
:
433 case PCI_DEVICE_ID_INTEL_82801DB_11
:
434 case PCI_DEVICE_ID_INTEL_82801EB_11
:
435 case PCI_DEVICE_ID_INTEL_82801E_11
:
436 case PCI_DEVICE_ID_INTEL_ESB_2
:
437 case PCI_DEVICE_ID_INTEL_ICH6_19
:
438 case PCI_DEVICE_ID_INTEL_ICH7_21
:
439 case PCI_DEVICE_ID_INTEL_ESB2_18
:
440 case PCI_DEVICE_ID_INTEL_ICH8_6
:
442 unsigned int extra
= 0;
443 pci_read_config_dword(dev
, 0x54, &extra
);
444 pci_write_config_dword(dev
, 0x54, extra
|0x400);
454 * init_hwif_piix - fill in the hwif for the PIIX
455 * @hwif: IDE interface
457 * Set up the ide_hwif_t for the PIIX interface according to the
458 * capabilities of the hardware.
461 static void __devinit
init_hwif_piix(ide_hwif_t
*hwif
)
463 u8 reg54h
= 0, reg55h
= 0, ata66
= 0;
464 u8 mask
= hwif
->channel
? 0xc0 : 0x30;
468 hwif
->irq
= hwif
->channel
? 15 : 14;
469 #endif /* CONFIG_IA64 */
471 if (hwif
->pci_dev
->device
== PCI_DEVICE_ID_INTEL_82371MX
) {
472 /* This is a painful system best to let it self tune for now */
475 /* ESB2 appears to generate spurious DMA interrupts in PIO mode
476 when in native mode */
477 if (hwif
->pci_dev
->device
== PCI_DEVICE_ID_INTEL_ESB2_18
)
478 hwif
->atapi_irq_bogon
= 1;
481 hwif
->tuneproc
= &piix_tune_drive
;
482 hwif
->speedproc
= &piix_tune_chipset
;
483 hwif
->drives
[0].autotune
= 1;
484 hwif
->drives
[1].autotune
= 1;
490 hwif
->ultra_mask
= 0x3f;
491 hwif
->mwdma_mask
= 0x06;
492 hwif
->swdma_mask
= 0x04;
494 switch(hwif
->pci_dev
->device
) {
495 case PCI_DEVICE_ID_INTEL_82371MX
:
496 hwif
->mwdma_mask
= 0x80;
497 hwif
->swdma_mask
= 0x80;
498 case PCI_DEVICE_ID_INTEL_82371FB_0
:
499 case PCI_DEVICE_ID_INTEL_82371FB_1
:
500 case PCI_DEVICE_ID_INTEL_82371SB_1
:
501 hwif
->ultra_mask
= 0x80;
503 case PCI_DEVICE_ID_INTEL_82371AB
:
504 case PCI_DEVICE_ID_INTEL_82443MX_1
:
505 case PCI_DEVICE_ID_INTEL_82451NX
:
506 case PCI_DEVICE_ID_INTEL_82801AB_1
:
507 hwif
->ultra_mask
= 0x07;
510 pci_read_config_byte(hwif
->pci_dev
, 0x54, ®54h
);
511 pci_read_config_byte(hwif
->pci_dev
, 0x55, ®55h
);
512 ata66
= (reg54h
& mask
) ? 1 : 0;
516 if (!(hwif
->udma_four
))
517 hwif
->udma_four
= ata66
;
518 hwif
->ide_dma_check
= &piix_config_drive_xfer_rate
;
522 hwif
->drives
[1].autodma
= hwif
->autodma
;
523 hwif
->drives
[0].autodma
= hwif
->autodma
;
526 #define DECLARE_PIIX_DEV(name_str) \
529 .init_chipset = init_chipset_piix, \
530 .init_hwif = init_hwif_piix, \
532 .autodma = AUTODMA, \
533 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
534 .bootable = ON_BOARD, \
537 static ide_pci_device_t piix_pci_info
[] __devinitdata
= {
538 /* 0 */ DECLARE_PIIX_DEV("PIIXa"),
539 /* 1 */ DECLARE_PIIX_DEV("PIIXb"),
543 * MPIIX actually has only a single IDE channel mapped to
544 * the primary or secondary ports depending on the value
545 * of the bit 14 of the IDETIM register at offset 0x6c
548 .init_hwif
= init_hwif_piix
,
551 .enablebits
= {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
552 .bootable
= ON_BOARD
,
553 .flags
= IDEPCI_FLAG_ISA_PORTS
556 /* 3 */ DECLARE_PIIX_DEV("PIIX3"),
557 /* 4 */ DECLARE_PIIX_DEV("PIIX4"),
558 /* 5 */ DECLARE_PIIX_DEV("ICH0"),
559 /* 6 */ DECLARE_PIIX_DEV("PIIX4"),
560 /* 7 */ DECLARE_PIIX_DEV("ICH"),
561 /* 8 */ DECLARE_PIIX_DEV("PIIX4"),
562 /* 9 */ DECLARE_PIIX_DEV("PIIX4"),
563 /* 10 */ DECLARE_PIIX_DEV("ICH2"),
564 /* 11 */ DECLARE_PIIX_DEV("ICH2M"),
565 /* 12 */ DECLARE_PIIX_DEV("ICH3M"),
566 /* 13 */ DECLARE_PIIX_DEV("ICH3"),
567 /* 14 */ DECLARE_PIIX_DEV("ICH4"),
568 /* 15 */ DECLARE_PIIX_DEV("ICH5"),
569 /* 16 */ DECLARE_PIIX_DEV("C-ICH"),
570 /* 17 */ DECLARE_PIIX_DEV("ICH4"),
571 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
572 /* 19 */ DECLARE_PIIX_DEV("ICH5"),
573 /* 20 */ DECLARE_PIIX_DEV("ICH6"),
574 /* 21 */ DECLARE_PIIX_DEV("ICH7"),
575 /* 22 */ DECLARE_PIIX_DEV("ICH4"),
576 /* 23 */ DECLARE_PIIX_DEV("ESB2"),
577 /* 24 */ DECLARE_PIIX_DEV("ICH8M"),
581 * piix_init_one - called when a PIIX is found
582 * @dev: the piix device
583 * @id: the matching pci id
585 * Called when the PCI registration layer (or the IDE initialization)
586 * finds a device matching our IDE device tables.
589 static int __devinit
piix_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
591 ide_pci_device_t
*d
= &piix_pci_info
[id
->driver_data
];
593 return ide_setup_pci_device(dev
, d
);
597 * piix_check_450nx - Check for problem 450NX setup
599 * Check for the present of 450NX errata #19 and errata #25. If
600 * they are found, disable use of DMA IDE
603 static void __devinit
piix_check_450nx(void)
605 struct pci_dev
*pdev
= NULL
;
608 while((pdev
=pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
))!=NULL
)
610 /* Look for 450NX PXB. Check for problem configurations
611 A PCI quirk checks bit 6 already */
612 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
613 pci_read_config_word(pdev
, 0x41, &cfg
);
614 /* Only on the original revision: IDE DMA can hang */
617 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
618 else if(cfg
& (1<<14) && rev
< 5)
622 printk(KERN_WARNING
"piix: 450NX errata present, disabling IDE DMA.\n");
624 printk(KERN_WARNING
"piix: A BIOS update may resolve this.\n");
627 static struct pci_device_id piix_pci_tbl
[] = {
628 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371FB_0
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
629 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371FB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
630 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371MX
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
631 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
632 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 4},
633 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 5},
634 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 6},
635 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 7},
636 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82372FB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 8},
637 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82451NX
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 9},
638 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_9
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 10},
639 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_8
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 11},
640 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 12},
641 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 13},
642 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 14},
643 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 15},
644 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801E_11
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 16},
645 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_10
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 17},
646 #ifdef CONFIG_BLK_DEV_IDE_SATA
647 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 18},
649 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_2
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 19},
650 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_19
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 20},
651 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_21
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 21},
652 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 22},
653 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_18
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 23},
654 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_6
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 24},
657 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
659 static struct pci_driver driver
= {
661 .id_table
= piix_pci_tbl
,
662 .probe
= piix_init_one
,
665 static int __init
piix_ide_init(void)
668 return ide_pci_register_driver(&driver
);
671 module_init(piix_ide_init
);
673 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
674 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
675 MODULE_LICENSE("GPL");