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Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / pdc202xx_new.c
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2007 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #ifdef CONFIG_PPC_PMAC
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif
39
40 #undef DEBUG
41
42 #ifdef DEBUG
43 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
44 #else
45 #define DBG(fmt, args...)
46 #endif
47
48 static const char *pdc_quirk_drives[] = {
49 "QUANTUM FIREBALLlct08 08",
50 "QUANTUM FIREBALLP KA6.4",
51 "QUANTUM FIREBALLP KA9.1",
52 "QUANTUM FIREBALLP LM20.4",
53 "QUANTUM FIREBALLP KX13.6",
54 "QUANTUM FIREBALLP KX20.5",
55 "QUANTUM FIREBALLP KX27.3",
56 "QUANTUM FIREBALLP LM20.5",
57 NULL
58 };
59
60 static u8 max_dma_rate(struct pci_dev *pdev)
61 {
62 u8 mode;
63
64 switch(pdev->device) {
65 case PCI_DEVICE_ID_PROMISE_20277:
66 case PCI_DEVICE_ID_PROMISE_20276:
67 case PCI_DEVICE_ID_PROMISE_20275:
68 case PCI_DEVICE_ID_PROMISE_20271:
69 case PCI_DEVICE_ID_PROMISE_20269:
70 mode = 4;
71 break;
72 case PCI_DEVICE_ID_PROMISE_20270:
73 case PCI_DEVICE_ID_PROMISE_20268:
74 mode = 3;
75 break;
76 default:
77 return 0;
78 }
79
80 return mode;
81 }
82
83 /**
84 * get_indexed_reg - Get indexed register
85 * @hwif: for the port address
86 * @index: index of the indexed register
87 */
88 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
89 {
90 u8 value;
91
92 outb(index, hwif->dma_vendor1);
93 value = inb(hwif->dma_vendor3);
94
95 DBG("index[%02X] value[%02X]\n", index, value);
96 return value;
97 }
98
99 /**
100 * set_indexed_reg - Set indexed register
101 * @hwif: for the port address
102 * @index: index of the indexed register
103 */
104 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
105 {
106 outb(index, hwif->dma_vendor1);
107 outb(value, hwif->dma_vendor3);
108 DBG("index[%02X] value[%02X]\n", index, value);
109 }
110
111 /*
112 * ATA Timing Tables based on 133 MHz PLL output clock.
113 *
114 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
115 * the timing registers automatically when "set features" command is
116 * issued to the device. However, if the PLL output clock is 133 MHz,
117 * the following tables must be used.
118 */
119 static struct pio_timing {
120 u8 reg0c, reg0d, reg13;
121 } pio_timings [] = {
122 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
123 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
124 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
125 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
126 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
127 };
128
129 static struct mwdma_timing {
130 u8 reg0e, reg0f;
131 } mwdma_timings [] = {
132 { 0xdf, 0x5f }, /* MWDMA mode 0 */
133 { 0x6b, 0x27 }, /* MWDMA mode 1 */
134 { 0x69, 0x25 }, /* MWDMA mode 2 */
135 };
136
137 static struct udma_timing {
138 u8 reg10, reg11, reg12;
139 } udma_timings [] = {
140 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
141 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
142 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
143 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
144 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
145 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
147 };
148
149 static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed)
150 {
151 ide_hwif_t *hwif = HWIF(drive);
152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
153 int err;
154
155 /*
156 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
157 * automatically set the timing registers based on 100 MHz PLL output.
158 */
159 err = ide_config_drive_speed(drive, speed);
160
161 /*
162 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
163 * chips, we must override the default register settings...
164 */
165 if (max_dma_rate(hwif->pci_dev) == 4) {
166 u8 mode = speed & 0x07;
167
168 switch (speed) {
169 case XFER_UDMA_6:
170 case XFER_UDMA_5:
171 case XFER_UDMA_4:
172 case XFER_UDMA_3:
173 case XFER_UDMA_2:
174 case XFER_UDMA_1:
175 case XFER_UDMA_0:
176 set_indexed_reg(hwif, 0x10 + adj,
177 udma_timings[mode].reg10);
178 set_indexed_reg(hwif, 0x11 + adj,
179 udma_timings[mode].reg11);
180 set_indexed_reg(hwif, 0x12 + adj,
181 udma_timings[mode].reg12);
182 break;
183
184 case XFER_MW_DMA_2:
185 case XFER_MW_DMA_1:
186 case XFER_MW_DMA_0:
187 set_indexed_reg(hwif, 0x0e + adj,
188 mwdma_timings[mode].reg0e);
189 set_indexed_reg(hwif, 0x0f + adj,
190 mwdma_timings[mode].reg0f);
191 break;
192 case XFER_PIO_4:
193 case XFER_PIO_3:
194 case XFER_PIO_2:
195 case XFER_PIO_1:
196 case XFER_PIO_0:
197 set_indexed_reg(hwif, 0x0c + adj,
198 pio_timings[mode].reg0c);
199 set_indexed_reg(hwif, 0x0d + adj,
200 pio_timings[mode].reg0d);
201 set_indexed_reg(hwif, 0x13 + adj,
202 pio_timings[mode].reg13);
203 break;
204 default:
205 printk(KERN_ERR "pdc202xx_new: "
206 "Unknown speed %d ignored\n", speed);
207 }
208 } else if (speed == XFER_UDMA_2) {
209 /* Set tHOLD bit to 0 if using UDMA mode 2 */
210 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
211
212 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
213 }
214
215 return err;
216 }
217
218 static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
219 {
220 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
221 }
222
223 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
224 {
225 if (get_indexed_reg(hwif, 0x0b) & 0x04)
226 return ATA_CBL_PATA40;
227 else
228 return ATA_CBL_PATA80;
229 }
230
231 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
232 {
233 drive->init_speed = 0;
234
235 if (ide_tune_dma(drive))
236 return 0;
237
238 if (ide_use_fast_pio(drive))
239 ide_set_max_pio(drive);
240
241 return -1;
242 }
243
244 static int pdcnew_quirkproc(ide_drive_t *drive)
245 {
246 const char **list, *model = drive->id->model;
247
248 for (list = pdc_quirk_drives; *list != NULL; list++)
249 if (strstr(model, *list) != NULL)
250 return 2;
251 return 0;
252 }
253
254 static void pdcnew_reset(ide_drive_t *drive)
255 {
256 /*
257 * Deleted this because it is redundant from the caller.
258 */
259 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
260 HWIF(drive)->channel ? "Secondary" : "Primary");
261 }
262
263 /**
264 * read_counter - Read the byte count registers
265 * @dma_base: for the port address
266 */
267 static long __devinit read_counter(u32 dma_base)
268 {
269 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
270 u8 cnt0, cnt1, cnt2, cnt3;
271 long count = 0, last;
272 int retry = 3;
273
274 do {
275 last = count;
276
277 /* Read the current count */
278 outb(0x20, pri_dma_base + 0x01);
279 cnt0 = inb(pri_dma_base + 0x03);
280 outb(0x21, pri_dma_base + 0x01);
281 cnt1 = inb(pri_dma_base + 0x03);
282 outb(0x20, sec_dma_base + 0x01);
283 cnt2 = inb(sec_dma_base + 0x03);
284 outb(0x21, sec_dma_base + 0x01);
285 cnt3 = inb(sec_dma_base + 0x03);
286
287 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
288
289 /*
290 * The 30-bit decrementing counter is read in 4 pieces.
291 * Incorrect value may be read when the most significant bytes
292 * are changing...
293 */
294 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
295
296 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
297 cnt0, cnt1, cnt2, cnt3);
298
299 return count;
300 }
301
302 /**
303 * detect_pll_input_clock - Detect the PLL input clock in Hz.
304 * @dma_base: for the port address
305 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
306 */
307 static long __devinit detect_pll_input_clock(unsigned long dma_base)
308 {
309 struct timeval start_time, end_time;
310 long start_count, end_count;
311 long pll_input, usec_elapsed;
312 u8 scr1;
313
314 start_count = read_counter(dma_base);
315 do_gettimeofday(&start_time);
316
317 /* Start the test mode */
318 outb(0x01, dma_base + 0x01);
319 scr1 = inb(dma_base + 0x03);
320 DBG("scr1[%02X]\n", scr1);
321 outb(scr1 | 0x40, dma_base + 0x03);
322
323 /* Let the counter run for 10 ms. */
324 mdelay(10);
325
326 end_count = read_counter(dma_base);
327 do_gettimeofday(&end_time);
328
329 /* Stop the test mode */
330 outb(0x01, dma_base + 0x01);
331 scr1 = inb(dma_base + 0x03);
332 DBG("scr1[%02X]\n", scr1);
333 outb(scr1 & ~0x40, dma_base + 0x03);
334
335 /*
336 * Calculate the input clock in Hz
337 * (the clock counter is 30 bit wide and counts down)
338 */
339 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
340 (end_time.tv_usec - start_time.tv_usec);
341 pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
342 (10000000 / usec_elapsed);
343
344 DBG("start[%ld] end[%ld]\n", start_count, end_count);
345
346 return pll_input;
347 }
348
349 #ifdef CONFIG_PPC_PMAC
350 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
351 {
352 struct device_node *np = pci_device_to_OF_node(pdev);
353 unsigned int class_rev = 0;
354 u8 conf;
355
356 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
357 return;
358
359 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
360 class_rev &= 0xff;
361
362 if (class_rev >= 0x03) {
363 /* Setup chip magic config stuff (from darwin) */
364 pci_read_config_byte (pdev, 0x40, &conf);
365 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
366 }
367 }
368 #endif /* CONFIG_PPC_PMAC */
369
370 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
371 {
372 unsigned long dma_base = pci_resource_start(dev, 4);
373 unsigned long sec_dma_base = dma_base + 0x08;
374 long pll_input, pll_output, ratio;
375 int f, r;
376 u8 pll_ctl0, pll_ctl1;
377
378 if (dma_base == 0)
379 return -EFAULT;
380
381 #ifdef CONFIG_PPC_PMAC
382 apple_kiwi_init(dev);
383 #endif
384
385 /* Calculate the required PLL output frequency */
386 switch(max_dma_rate(dev)) {
387 case 4: /* it's 133 MHz for Ultra133 chips */
388 pll_output = 133333333;
389 break;
390 case 3: /* and 100 MHz for Ultra100 chips */
391 default:
392 pll_output = 100000000;
393 break;
394 }
395
396 /*
397 * Detect PLL input clock.
398 * On some systems, where PCI bus is running at non-standard clock rate
399 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
400 * PDC20268 and newer chips employ PLL circuit to help correct timing
401 * registers setting.
402 */
403 pll_input = detect_pll_input_clock(dma_base);
404 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
405
406 /* Sanity check */
407 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
408 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
409 name, pll_input);
410 goto out;
411 }
412
413 #ifdef DEBUG
414 DBG("pll_output is %ld Hz\n", pll_output);
415
416 /* Show the current clock value of PLL control register
417 * (maybe already configured by the BIOS)
418 */
419 outb(0x02, sec_dma_base + 0x01);
420 pll_ctl0 = inb(sec_dma_base + 0x03);
421 outb(0x03, sec_dma_base + 0x01);
422 pll_ctl1 = inb(sec_dma_base + 0x03);
423
424 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
425 #endif
426
427 /*
428 * Calculate the ratio of F, R and NO
429 * POUT = (F + 2) / (( R + 2) * NO)
430 */
431 ratio = pll_output / (pll_input / 1000);
432 if (ratio < 8600L) { /* 8.6x */
433 /* Using NO = 0x01, R = 0x0d */
434 r = 0x0d;
435 } else if (ratio < 12900L) { /* 12.9x */
436 /* Using NO = 0x01, R = 0x08 */
437 r = 0x08;
438 } else if (ratio < 16100L) { /* 16.1x */
439 /* Using NO = 0x01, R = 0x06 */
440 r = 0x06;
441 } else if (ratio < 64000L) { /* 64x */
442 r = 0x00;
443 } else {
444 /* Invalid ratio */
445 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
446 goto out;
447 }
448
449 f = (ratio * (r + 2)) / 1000 - 2;
450
451 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
452
453 if (unlikely(f < 0 || f > 127)) {
454 /* Invalid F */
455 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
456 goto out;
457 }
458
459 pll_ctl0 = (u8) f;
460 pll_ctl1 = (u8) r;
461
462 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
463
464 outb(0x02, sec_dma_base + 0x01);
465 outb(pll_ctl0, sec_dma_base + 0x03);
466 outb(0x03, sec_dma_base + 0x01);
467 outb(pll_ctl1, sec_dma_base + 0x03);
468
469 /* Wait the PLL circuit to be stable */
470 mdelay(30);
471
472 #ifdef DEBUG
473 /*
474 * Show the current clock value of PLL control register
475 */
476 outb(0x02, sec_dma_base + 0x01);
477 pll_ctl0 = inb(sec_dma_base + 0x03);
478 outb(0x03, sec_dma_base + 0x01);
479 pll_ctl1 = inb(sec_dma_base + 0x03);
480
481 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
482 #endif
483
484 out:
485 return dev->irq;
486 }
487
488 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
489 {
490 hwif->autodma = 0;
491
492 hwif->set_pio_mode = &pdcnew_set_pio_mode;
493
494 hwif->quirkproc = &pdcnew_quirkproc;
495 hwif->speedproc = &pdcnew_tune_chipset;
496 hwif->resetproc = &pdcnew_reset;
497
498 hwif->err_stops_fifo = 1;
499
500 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
501
502 if (hwif->dma_base == 0)
503 return;
504
505 hwif->atapi_dma = 1;
506
507 hwif->ultra_mask = hwif->cds->udma_mask;
508 hwif->mwdma_mask = 0x07;
509
510 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
511
512 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
513 hwif->cbl = pdcnew_cable_detect(hwif);
514
515 if (!noautodma)
516 hwif->autodma = 1;
517 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
518 }
519
520 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
521 {
522 return ide_setup_pci_device(dev, d);
523 }
524
525 static int __devinit init_setup_pdc20270(struct pci_dev *dev, ide_pci_device_t *d)
526 {
527 struct pci_dev *bridge = dev->bus->self;
528
529 if (bridge != NULL &&
530 bridge->vendor == PCI_VENDOR_ID_DEC &&
531 bridge->device == PCI_DEVICE_ID_DEC_21150) {
532 struct pci_dev *dev2;
533
534 if (PCI_SLOT(dev->devfn) & 2)
535 return -ENODEV;
536
537 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
538 PCI_FUNC(dev->devfn)));
539 if (dev2 != NULL &&
540 dev2->vendor == dev->vendor &&
541 dev2->device == dev->device) {
542 int ret;
543
544 if (dev2->irq != dev->irq) {
545 dev2->irq = dev->irq;
546
547 printk(KERN_WARNING "%s: PCI config space "
548 "interrupt fixed.\n", d->name);
549 }
550
551 ret = ide_setup_pci_devices(dev, dev2, d);
552 if (ret < 0)
553 pci_dev_put(dev2);
554 return ret;
555 }
556 }
557 return ide_setup_pci_device(dev, d);
558 }
559
560 static int __devinit init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d)
561 {
562 struct pci_dev *bridge = dev->bus->self;
563
564 if (bridge != NULL &&
565 bridge->vendor == PCI_VENDOR_ID_INTEL &&
566 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
567 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
568
569 printk(KERN_INFO "%s: attached to I2O RAID controller, "
570 "skipping.\n", d->name);
571 return -ENODEV;
572 }
573 return ide_setup_pci_device(dev, d);
574 }
575
576 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
577 { /* 0 */
578 .name = "PDC20268",
579 .init_setup = init_setup_pdcnew,
580 .init_chipset = init_chipset_pdcnew,
581 .init_hwif = init_hwif_pdc202new,
582 .autodma = AUTODMA,
583 .bootable = OFF_BOARD,
584 .pio_mask = ATA_PIO4,
585 .udma_mask = 0x3f, /* udma0-5 */
586 },{ /* 1 */
587 .name = "PDC20269",
588 .init_setup = init_setup_pdcnew,
589 .init_chipset = init_chipset_pdcnew,
590 .init_hwif = init_hwif_pdc202new,
591 .autodma = AUTODMA,
592 .bootable = OFF_BOARD,
593 .pio_mask = ATA_PIO4,
594 .udma_mask = 0x7f, /* udma0-6*/
595 },{ /* 2 */
596 .name = "PDC20270",
597 .init_setup = init_setup_pdc20270,
598 .init_chipset = init_chipset_pdcnew,
599 .init_hwif = init_hwif_pdc202new,
600 .autodma = AUTODMA,
601 .bootable = OFF_BOARD,
602 .pio_mask = ATA_PIO4,
603 .udma_mask = 0x3f, /* udma0-5 */
604 },{ /* 3 */
605 .name = "PDC20271",
606 .init_setup = init_setup_pdcnew,
607 .init_chipset = init_chipset_pdcnew,
608 .init_hwif = init_hwif_pdc202new,
609 .autodma = AUTODMA,
610 .bootable = OFF_BOARD,
611 .pio_mask = ATA_PIO4,
612 .udma_mask = 0x7f, /* udma0-6*/
613 },{ /* 4 */
614 .name = "PDC20275",
615 .init_setup = init_setup_pdcnew,
616 .init_chipset = init_chipset_pdcnew,
617 .init_hwif = init_hwif_pdc202new,
618 .autodma = AUTODMA,
619 .bootable = OFF_BOARD,
620 .pio_mask = ATA_PIO4,
621 .udma_mask = 0x7f, /* udma0-6*/
622 },{ /* 5 */
623 .name = "PDC20276",
624 .init_setup = init_setup_pdc20276,
625 .init_chipset = init_chipset_pdcnew,
626 .init_hwif = init_hwif_pdc202new,
627 .autodma = AUTODMA,
628 .bootable = OFF_BOARD,
629 .pio_mask = ATA_PIO4,
630 .udma_mask = 0x7f, /* udma0-6*/
631 },{ /* 6 */
632 .name = "PDC20277",
633 .init_setup = init_setup_pdcnew,
634 .init_chipset = init_chipset_pdcnew,
635 .init_hwif = init_hwif_pdc202new,
636 .autodma = AUTODMA,
637 .bootable = OFF_BOARD,
638 .pio_mask = ATA_PIO4,
639 .udma_mask = 0x7f, /* udma0-6*/
640 }
641 };
642
643 /**
644 * pdc202new_init_one - called when a pdc202xx is found
645 * @dev: the pdc202new device
646 * @id: the matching pci id
647 *
648 * Called when the PCI registration layer (or the IDE initialization)
649 * finds a device matching our IDE device tables.
650 */
651
652 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
653 {
654 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
655
656 return d->init_setup(dev, d);
657 }
658
659 static struct pci_device_id pdc202new_pci_tbl[] = {
660 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
661 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
662 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
663 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
664 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
665 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
666 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
667 { 0, },
668 };
669 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
670
671 static struct pci_driver driver = {
672 .name = "Promise_IDE",
673 .id_table = pdc202new_pci_tbl,
674 .probe = pdc202new_init_one,
675 };
676
677 static int __init pdc202new_ide_init(void)
678 {
679 return ide_pci_register_driver(&driver);
680 }
681
682 module_init(pdc202new_ide_init);
683
684 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
685 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
686 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)