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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / pdc202xx_new.c
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2007 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #ifdef CONFIG_PPC_PMAC
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif
39
40 #undef DEBUG
41
42 #ifdef DEBUG
43 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
44 #else
45 #define DBG(fmt, args...)
46 #endif
47
48 static const char *pdc_quirk_drives[] = {
49 "QUANTUM FIREBALLlct08 08",
50 "QUANTUM FIREBALLP KA6.4",
51 "QUANTUM FIREBALLP KA9.1",
52 "QUANTUM FIREBALLP LM20.4",
53 "QUANTUM FIREBALLP KX13.6",
54 "QUANTUM FIREBALLP KX20.5",
55 "QUANTUM FIREBALLP KX27.3",
56 "QUANTUM FIREBALLP LM20.5",
57 NULL
58 };
59
60 static u8 max_dma_rate(struct pci_dev *pdev)
61 {
62 u8 mode;
63
64 switch(pdev->device) {
65 case PCI_DEVICE_ID_PROMISE_20277:
66 case PCI_DEVICE_ID_PROMISE_20276:
67 case PCI_DEVICE_ID_PROMISE_20275:
68 case PCI_DEVICE_ID_PROMISE_20271:
69 case PCI_DEVICE_ID_PROMISE_20269:
70 mode = 4;
71 break;
72 case PCI_DEVICE_ID_PROMISE_20270:
73 case PCI_DEVICE_ID_PROMISE_20268:
74 mode = 3;
75 break;
76 default:
77 return 0;
78 }
79
80 return mode;
81 }
82
83 /**
84 * get_indexed_reg - Get indexed register
85 * @hwif: for the port address
86 * @index: index of the indexed register
87 */
88 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
89 {
90 u8 value;
91
92 outb(index, hwif->dma_vendor1);
93 value = inb(hwif->dma_vendor3);
94
95 DBG("index[%02X] value[%02X]\n", index, value);
96 return value;
97 }
98
99 /**
100 * set_indexed_reg - Set indexed register
101 * @hwif: for the port address
102 * @index: index of the indexed register
103 */
104 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
105 {
106 outb(index, hwif->dma_vendor1);
107 outb(value, hwif->dma_vendor3);
108 DBG("index[%02X] value[%02X]\n", index, value);
109 }
110
111 /*
112 * ATA Timing Tables based on 133 MHz PLL output clock.
113 *
114 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
115 * the timing registers automatically when "set features" command is
116 * issued to the device. However, if the PLL output clock is 133 MHz,
117 * the following tables must be used.
118 */
119 static struct pio_timing {
120 u8 reg0c, reg0d, reg13;
121 } pio_timings [] = {
122 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
123 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
124 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
125 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
126 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
127 };
128
129 static struct mwdma_timing {
130 u8 reg0e, reg0f;
131 } mwdma_timings [] = {
132 { 0xdf, 0x5f }, /* MWDMA mode 0 */
133 { 0x6b, 0x27 }, /* MWDMA mode 1 */
134 { 0x69, 0x25 }, /* MWDMA mode 2 */
135 };
136
137 static struct udma_timing {
138 u8 reg10, reg11, reg12;
139 } udma_timings [] = {
140 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
141 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
142 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
143 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
144 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
145 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
147 };
148
149 static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
150 {
151 ide_hwif_t *hwif = HWIF(drive);
152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
153
154 /*
155 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
156 * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
157 * automatically set the timing registers based on 100 MHz PLL output.
158 *
159 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
160 * chips, we must override the default register settings...
161 */
162 if (max_dma_rate(hwif->pci_dev) == 4) {
163 u8 mode = speed & 0x07;
164
165 switch (speed) {
166 case XFER_UDMA_6:
167 case XFER_UDMA_5:
168 case XFER_UDMA_4:
169 case XFER_UDMA_3:
170 case XFER_UDMA_2:
171 case XFER_UDMA_1:
172 case XFER_UDMA_0:
173 set_indexed_reg(hwif, 0x10 + adj,
174 udma_timings[mode].reg10);
175 set_indexed_reg(hwif, 0x11 + adj,
176 udma_timings[mode].reg11);
177 set_indexed_reg(hwif, 0x12 + adj,
178 udma_timings[mode].reg12);
179 break;
180
181 case XFER_MW_DMA_2:
182 case XFER_MW_DMA_1:
183 case XFER_MW_DMA_0:
184 set_indexed_reg(hwif, 0x0e + adj,
185 mwdma_timings[mode].reg0e);
186 set_indexed_reg(hwif, 0x0f + adj,
187 mwdma_timings[mode].reg0f);
188 break;
189 case XFER_PIO_4:
190 case XFER_PIO_3:
191 case XFER_PIO_2:
192 case XFER_PIO_1:
193 case XFER_PIO_0:
194 set_indexed_reg(hwif, 0x0c + adj,
195 pio_timings[mode].reg0c);
196 set_indexed_reg(hwif, 0x0d + adj,
197 pio_timings[mode].reg0d);
198 set_indexed_reg(hwif, 0x13 + adj,
199 pio_timings[mode].reg13);
200 break;
201 default:
202 printk(KERN_ERR "pdc202xx_new: "
203 "Unknown speed %d ignored\n", speed);
204 }
205 } else if (speed == XFER_UDMA_2) {
206 /* Set tHOLD bit to 0 if using UDMA mode 2 */
207 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
208
209 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
210 }
211 }
212
213 static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
214 {
215 pdcnew_set_mode(drive, XFER_PIO_0 + pio);
216 }
217
218 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
219 {
220 if (get_indexed_reg(hwif, 0x0b) & 0x04)
221 return ATA_CBL_PATA40;
222 else
223 return ATA_CBL_PATA80;
224 }
225
226 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
227 {
228 drive->init_speed = 0;
229
230 if (ide_tune_dma(drive))
231 return 0;
232
233 if (ide_use_fast_pio(drive))
234 ide_set_max_pio(drive);
235
236 return -1;
237 }
238
239 static int pdcnew_quirkproc(ide_drive_t *drive)
240 {
241 const char **list, *model = drive->id->model;
242
243 for (list = pdc_quirk_drives; *list != NULL; list++)
244 if (strstr(model, *list) != NULL)
245 return 2;
246 return 0;
247 }
248
249 static void pdcnew_reset(ide_drive_t *drive)
250 {
251 /*
252 * Deleted this because it is redundant from the caller.
253 */
254 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
255 HWIF(drive)->channel ? "Secondary" : "Primary");
256 }
257
258 /**
259 * read_counter - Read the byte count registers
260 * @dma_base: for the port address
261 */
262 static long __devinit read_counter(u32 dma_base)
263 {
264 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
265 u8 cnt0, cnt1, cnt2, cnt3;
266 long count = 0, last;
267 int retry = 3;
268
269 do {
270 last = count;
271
272 /* Read the current count */
273 outb(0x20, pri_dma_base + 0x01);
274 cnt0 = inb(pri_dma_base + 0x03);
275 outb(0x21, pri_dma_base + 0x01);
276 cnt1 = inb(pri_dma_base + 0x03);
277 outb(0x20, sec_dma_base + 0x01);
278 cnt2 = inb(sec_dma_base + 0x03);
279 outb(0x21, sec_dma_base + 0x01);
280 cnt3 = inb(sec_dma_base + 0x03);
281
282 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
283
284 /*
285 * The 30-bit decrementing counter is read in 4 pieces.
286 * Incorrect value may be read when the most significant bytes
287 * are changing...
288 */
289 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
290
291 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
292 cnt0, cnt1, cnt2, cnt3);
293
294 return count;
295 }
296
297 /**
298 * detect_pll_input_clock - Detect the PLL input clock in Hz.
299 * @dma_base: for the port address
300 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
301 */
302 static long __devinit detect_pll_input_clock(unsigned long dma_base)
303 {
304 struct timeval start_time, end_time;
305 long start_count, end_count;
306 long pll_input, usec_elapsed;
307 u8 scr1;
308
309 start_count = read_counter(dma_base);
310 do_gettimeofday(&start_time);
311
312 /* Start the test mode */
313 outb(0x01, dma_base + 0x01);
314 scr1 = inb(dma_base + 0x03);
315 DBG("scr1[%02X]\n", scr1);
316 outb(scr1 | 0x40, dma_base + 0x03);
317
318 /* Let the counter run for 10 ms. */
319 mdelay(10);
320
321 end_count = read_counter(dma_base);
322 do_gettimeofday(&end_time);
323
324 /* Stop the test mode */
325 outb(0x01, dma_base + 0x01);
326 scr1 = inb(dma_base + 0x03);
327 DBG("scr1[%02X]\n", scr1);
328 outb(scr1 & ~0x40, dma_base + 0x03);
329
330 /*
331 * Calculate the input clock in Hz
332 * (the clock counter is 30 bit wide and counts down)
333 */
334 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
335 (end_time.tv_usec - start_time.tv_usec);
336 pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
337 (10000000 / usec_elapsed);
338
339 DBG("start[%ld] end[%ld]\n", start_count, end_count);
340
341 return pll_input;
342 }
343
344 #ifdef CONFIG_PPC_PMAC
345 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
346 {
347 struct device_node *np = pci_device_to_OF_node(pdev);
348 unsigned int class_rev = 0;
349 u8 conf;
350
351 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
352 return;
353
354 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
355 class_rev &= 0xff;
356
357 if (class_rev >= 0x03) {
358 /* Setup chip magic config stuff (from darwin) */
359 pci_read_config_byte (pdev, 0x40, &conf);
360 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
361 }
362 }
363 #endif /* CONFIG_PPC_PMAC */
364
365 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
366 {
367 unsigned long dma_base = pci_resource_start(dev, 4);
368 unsigned long sec_dma_base = dma_base + 0x08;
369 long pll_input, pll_output, ratio;
370 int f, r;
371 u8 pll_ctl0, pll_ctl1;
372
373 if (dma_base == 0)
374 return -EFAULT;
375
376 #ifdef CONFIG_PPC_PMAC
377 apple_kiwi_init(dev);
378 #endif
379
380 /* Calculate the required PLL output frequency */
381 switch(max_dma_rate(dev)) {
382 case 4: /* it's 133 MHz for Ultra133 chips */
383 pll_output = 133333333;
384 break;
385 case 3: /* and 100 MHz for Ultra100 chips */
386 default:
387 pll_output = 100000000;
388 break;
389 }
390
391 /*
392 * Detect PLL input clock.
393 * On some systems, where PCI bus is running at non-standard clock rate
394 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
395 * PDC20268 and newer chips employ PLL circuit to help correct timing
396 * registers setting.
397 */
398 pll_input = detect_pll_input_clock(dma_base);
399 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
400
401 /* Sanity check */
402 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
403 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
404 name, pll_input);
405 goto out;
406 }
407
408 #ifdef DEBUG
409 DBG("pll_output is %ld Hz\n", pll_output);
410
411 /* Show the current clock value of PLL control register
412 * (maybe already configured by the BIOS)
413 */
414 outb(0x02, sec_dma_base + 0x01);
415 pll_ctl0 = inb(sec_dma_base + 0x03);
416 outb(0x03, sec_dma_base + 0x01);
417 pll_ctl1 = inb(sec_dma_base + 0x03);
418
419 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
420 #endif
421
422 /*
423 * Calculate the ratio of F, R and NO
424 * POUT = (F + 2) / (( R + 2) * NO)
425 */
426 ratio = pll_output / (pll_input / 1000);
427 if (ratio < 8600L) { /* 8.6x */
428 /* Using NO = 0x01, R = 0x0d */
429 r = 0x0d;
430 } else if (ratio < 12900L) { /* 12.9x */
431 /* Using NO = 0x01, R = 0x08 */
432 r = 0x08;
433 } else if (ratio < 16100L) { /* 16.1x */
434 /* Using NO = 0x01, R = 0x06 */
435 r = 0x06;
436 } else if (ratio < 64000L) { /* 64x */
437 r = 0x00;
438 } else {
439 /* Invalid ratio */
440 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
441 goto out;
442 }
443
444 f = (ratio * (r + 2)) / 1000 - 2;
445
446 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
447
448 if (unlikely(f < 0 || f > 127)) {
449 /* Invalid F */
450 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
451 goto out;
452 }
453
454 pll_ctl0 = (u8) f;
455 pll_ctl1 = (u8) r;
456
457 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
458
459 outb(0x02, sec_dma_base + 0x01);
460 outb(pll_ctl0, sec_dma_base + 0x03);
461 outb(0x03, sec_dma_base + 0x01);
462 outb(pll_ctl1, sec_dma_base + 0x03);
463
464 /* Wait the PLL circuit to be stable */
465 mdelay(30);
466
467 #ifdef DEBUG
468 /*
469 * Show the current clock value of PLL control register
470 */
471 outb(0x02, sec_dma_base + 0x01);
472 pll_ctl0 = inb(sec_dma_base + 0x03);
473 outb(0x03, sec_dma_base + 0x01);
474 pll_ctl1 = inb(sec_dma_base + 0x03);
475
476 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
477 #endif
478
479 out:
480 return dev->irq;
481 }
482
483 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
484 {
485 hwif->autodma = 0;
486
487 hwif->set_pio_mode = &pdcnew_set_pio_mode;
488 hwif->set_dma_mode = &pdcnew_set_mode;
489
490 hwif->quirkproc = &pdcnew_quirkproc;
491 hwif->resetproc = &pdcnew_reset;
492
493 hwif->err_stops_fifo = 1;
494
495 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
496
497 if (hwif->dma_base == 0)
498 return;
499
500 hwif->atapi_dma = 1;
501
502 hwif->ultra_mask = hwif->cds->udma_mask;
503 hwif->mwdma_mask = 0x07;
504
505 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
506
507 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
508 hwif->cbl = pdcnew_cable_detect(hwif);
509
510 if (!noautodma)
511 hwif->autodma = 1;
512 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
513 }
514
515 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
516 {
517 return ide_setup_pci_device(dev, d);
518 }
519
520 static int __devinit init_setup_pdc20270(struct pci_dev *dev, ide_pci_device_t *d)
521 {
522 struct pci_dev *bridge = dev->bus->self;
523
524 if (bridge != NULL &&
525 bridge->vendor == PCI_VENDOR_ID_DEC &&
526 bridge->device == PCI_DEVICE_ID_DEC_21150) {
527 struct pci_dev *dev2;
528
529 if (PCI_SLOT(dev->devfn) & 2)
530 return -ENODEV;
531
532 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
533 PCI_FUNC(dev->devfn)));
534 if (dev2 != NULL &&
535 dev2->vendor == dev->vendor &&
536 dev2->device == dev->device) {
537 int ret;
538
539 if (dev2->irq != dev->irq) {
540 dev2->irq = dev->irq;
541
542 printk(KERN_WARNING "%s: PCI config space "
543 "interrupt fixed.\n", d->name);
544 }
545
546 ret = ide_setup_pci_devices(dev, dev2, d);
547 if (ret < 0)
548 pci_dev_put(dev2);
549 return ret;
550 }
551 }
552 return ide_setup_pci_device(dev, d);
553 }
554
555 static int __devinit init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d)
556 {
557 struct pci_dev *bridge = dev->bus->self;
558
559 if (bridge != NULL &&
560 bridge->vendor == PCI_VENDOR_ID_INTEL &&
561 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
562 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
563
564 printk(KERN_INFO "%s: attached to I2O RAID controller, "
565 "skipping.\n", d->name);
566 return -ENODEV;
567 }
568 return ide_setup_pci_device(dev, d);
569 }
570
571 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
572 { /* 0 */
573 .name = "PDC20268",
574 .init_setup = init_setup_pdcnew,
575 .init_chipset = init_chipset_pdcnew,
576 .init_hwif = init_hwif_pdc202new,
577 .autodma = AUTODMA,
578 .bootable = OFF_BOARD,
579 .pio_mask = ATA_PIO4,
580 .udma_mask = 0x3f, /* udma0-5 */
581 .host_flags = IDE_HFLAG_POST_SET_MODE,
582 },{ /* 1 */
583 .name = "PDC20269",
584 .init_setup = init_setup_pdcnew,
585 .init_chipset = init_chipset_pdcnew,
586 .init_hwif = init_hwif_pdc202new,
587 .autodma = AUTODMA,
588 .bootable = OFF_BOARD,
589 .pio_mask = ATA_PIO4,
590 .udma_mask = 0x7f, /* udma0-6*/
591 .host_flags = IDE_HFLAG_POST_SET_MODE,
592 },{ /* 2 */
593 .name = "PDC20270",
594 .init_setup = init_setup_pdc20270,
595 .init_chipset = init_chipset_pdcnew,
596 .init_hwif = init_hwif_pdc202new,
597 .autodma = AUTODMA,
598 .bootable = OFF_BOARD,
599 .pio_mask = ATA_PIO4,
600 .udma_mask = 0x3f, /* udma0-5 */
601 .host_flags = IDE_HFLAG_POST_SET_MODE,
602 },{ /* 3 */
603 .name = "PDC20271",
604 .init_setup = init_setup_pdcnew,
605 .init_chipset = init_chipset_pdcnew,
606 .init_hwif = init_hwif_pdc202new,
607 .autodma = AUTODMA,
608 .bootable = OFF_BOARD,
609 .pio_mask = ATA_PIO4,
610 .udma_mask = 0x7f, /* udma0-6*/
611 .host_flags = IDE_HFLAG_POST_SET_MODE,
612 },{ /* 4 */
613 .name = "PDC20275",
614 .init_setup = init_setup_pdcnew,
615 .init_chipset = init_chipset_pdcnew,
616 .init_hwif = init_hwif_pdc202new,
617 .autodma = AUTODMA,
618 .bootable = OFF_BOARD,
619 .pio_mask = ATA_PIO4,
620 .udma_mask = 0x7f, /* udma0-6*/
621 .host_flags = IDE_HFLAG_POST_SET_MODE,
622 },{ /* 5 */
623 .name = "PDC20276",
624 .init_setup = init_setup_pdc20276,
625 .init_chipset = init_chipset_pdcnew,
626 .init_hwif = init_hwif_pdc202new,
627 .autodma = AUTODMA,
628 .bootable = OFF_BOARD,
629 .pio_mask = ATA_PIO4,
630 .udma_mask = 0x7f, /* udma0-6*/
631 .host_flags = IDE_HFLAG_POST_SET_MODE,
632 },{ /* 6 */
633 .name = "PDC20277",
634 .init_setup = init_setup_pdcnew,
635 .init_chipset = init_chipset_pdcnew,
636 .init_hwif = init_hwif_pdc202new,
637 .autodma = AUTODMA,
638 .bootable = OFF_BOARD,
639 .pio_mask = ATA_PIO4,
640 .udma_mask = 0x7f, /* udma0-6*/
641 .host_flags = IDE_HFLAG_POST_SET_MODE,
642 }
643 };
644
645 /**
646 * pdc202new_init_one - called when a pdc202xx is found
647 * @dev: the pdc202new device
648 * @id: the matching pci id
649 *
650 * Called when the PCI registration layer (or the IDE initialization)
651 * finds a device matching our IDE device tables.
652 */
653
654 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
655 {
656 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
657
658 return d->init_setup(dev, d);
659 }
660
661 static struct pci_device_id pdc202new_pci_tbl[] = {
662 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
663 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
664 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
665 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
666 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
667 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
668 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
669 { 0, },
670 };
671 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
672
673 static struct pci_driver driver = {
674 .name = "Promise_IDE",
675 .id_table = pdc202new_pci_tbl,
676 .probe = pdc202new_init_one,
677 };
678
679 static int __init pdc202new_ide_init(void)
680 {
681 return ide_pci_register_driver(&driver);
682 }
683
684 module_init(pdc202new_ide_init);
685
686 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
687 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
688 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)