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ide: remove hwif->autodma and drive->autodma
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / pdc202xx_new.c
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2007 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #ifdef CONFIG_PPC_PMAC
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif
39
40 #undef DEBUG
41
42 #ifdef DEBUG
43 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
44 #else
45 #define DBG(fmt, args...)
46 #endif
47
48 static const char *pdc_quirk_drives[] = {
49 "QUANTUM FIREBALLlct08 08",
50 "QUANTUM FIREBALLP KA6.4",
51 "QUANTUM FIREBALLP KA9.1",
52 "QUANTUM FIREBALLP LM20.4",
53 "QUANTUM FIREBALLP KX13.6",
54 "QUANTUM FIREBALLP KX20.5",
55 "QUANTUM FIREBALLP KX27.3",
56 "QUANTUM FIREBALLP LM20.5",
57 NULL
58 };
59
60 static u8 max_dma_rate(struct pci_dev *pdev)
61 {
62 u8 mode;
63
64 switch(pdev->device) {
65 case PCI_DEVICE_ID_PROMISE_20277:
66 case PCI_DEVICE_ID_PROMISE_20276:
67 case PCI_DEVICE_ID_PROMISE_20275:
68 case PCI_DEVICE_ID_PROMISE_20271:
69 case PCI_DEVICE_ID_PROMISE_20269:
70 mode = 4;
71 break;
72 case PCI_DEVICE_ID_PROMISE_20270:
73 case PCI_DEVICE_ID_PROMISE_20268:
74 mode = 3;
75 break;
76 default:
77 return 0;
78 }
79
80 return mode;
81 }
82
83 /**
84 * get_indexed_reg - Get indexed register
85 * @hwif: for the port address
86 * @index: index of the indexed register
87 */
88 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
89 {
90 u8 value;
91
92 outb(index, hwif->dma_vendor1);
93 value = inb(hwif->dma_vendor3);
94
95 DBG("index[%02X] value[%02X]\n", index, value);
96 return value;
97 }
98
99 /**
100 * set_indexed_reg - Set indexed register
101 * @hwif: for the port address
102 * @index: index of the indexed register
103 */
104 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
105 {
106 outb(index, hwif->dma_vendor1);
107 outb(value, hwif->dma_vendor3);
108 DBG("index[%02X] value[%02X]\n", index, value);
109 }
110
111 /*
112 * ATA Timing Tables based on 133 MHz PLL output clock.
113 *
114 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
115 * the timing registers automatically when "set features" command is
116 * issued to the device. However, if the PLL output clock is 133 MHz,
117 * the following tables must be used.
118 */
119 static struct pio_timing {
120 u8 reg0c, reg0d, reg13;
121 } pio_timings [] = {
122 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
123 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
124 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
125 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
126 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
127 };
128
129 static struct mwdma_timing {
130 u8 reg0e, reg0f;
131 } mwdma_timings [] = {
132 { 0xdf, 0x5f }, /* MWDMA mode 0 */
133 { 0x6b, 0x27 }, /* MWDMA mode 1 */
134 { 0x69, 0x25 }, /* MWDMA mode 2 */
135 };
136
137 static struct udma_timing {
138 u8 reg10, reg11, reg12;
139 } udma_timings [] = {
140 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
141 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
142 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
143 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
144 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
145 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
147 };
148
149 static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
150 {
151 ide_hwif_t *hwif = HWIF(drive);
152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
153
154 /*
155 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
156 * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
157 * automatically set the timing registers based on 100 MHz PLL output.
158 *
159 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
160 * chips, we must override the default register settings...
161 */
162 if (max_dma_rate(hwif->pci_dev) == 4) {
163 u8 mode = speed & 0x07;
164
165 switch (speed) {
166 case XFER_UDMA_6:
167 case XFER_UDMA_5:
168 case XFER_UDMA_4:
169 case XFER_UDMA_3:
170 case XFER_UDMA_2:
171 case XFER_UDMA_1:
172 case XFER_UDMA_0:
173 set_indexed_reg(hwif, 0x10 + adj,
174 udma_timings[mode].reg10);
175 set_indexed_reg(hwif, 0x11 + adj,
176 udma_timings[mode].reg11);
177 set_indexed_reg(hwif, 0x12 + adj,
178 udma_timings[mode].reg12);
179 break;
180
181 case XFER_MW_DMA_2:
182 case XFER_MW_DMA_1:
183 case XFER_MW_DMA_0:
184 set_indexed_reg(hwif, 0x0e + adj,
185 mwdma_timings[mode].reg0e);
186 set_indexed_reg(hwif, 0x0f + adj,
187 mwdma_timings[mode].reg0f);
188 break;
189 case XFER_PIO_4:
190 case XFER_PIO_3:
191 case XFER_PIO_2:
192 case XFER_PIO_1:
193 case XFER_PIO_0:
194 set_indexed_reg(hwif, 0x0c + adj,
195 pio_timings[mode].reg0c);
196 set_indexed_reg(hwif, 0x0d + adj,
197 pio_timings[mode].reg0d);
198 set_indexed_reg(hwif, 0x13 + adj,
199 pio_timings[mode].reg13);
200 break;
201 default:
202 printk(KERN_ERR "pdc202xx_new: "
203 "Unknown speed %d ignored\n", speed);
204 }
205 } else if (speed == XFER_UDMA_2) {
206 /* Set tHOLD bit to 0 if using UDMA mode 2 */
207 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
208
209 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
210 }
211 }
212
213 static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
214 {
215 pdcnew_set_mode(drive, XFER_PIO_0 + pio);
216 }
217
218 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
219 {
220 if (get_indexed_reg(hwif, 0x0b) & 0x04)
221 return ATA_CBL_PATA40;
222 else
223 return ATA_CBL_PATA80;
224 }
225
226 static int pdcnew_quirkproc(ide_drive_t *drive)
227 {
228 const char **list, *model = drive->id->model;
229
230 for (list = pdc_quirk_drives; *list != NULL; list++)
231 if (strstr(model, *list) != NULL)
232 return 2;
233 return 0;
234 }
235
236 static void pdcnew_reset(ide_drive_t *drive)
237 {
238 /*
239 * Deleted this because it is redundant from the caller.
240 */
241 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
242 HWIF(drive)->channel ? "Secondary" : "Primary");
243 }
244
245 /**
246 * read_counter - Read the byte count registers
247 * @dma_base: for the port address
248 */
249 static long __devinit read_counter(u32 dma_base)
250 {
251 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
252 u8 cnt0, cnt1, cnt2, cnt3;
253 long count = 0, last;
254 int retry = 3;
255
256 do {
257 last = count;
258
259 /* Read the current count */
260 outb(0x20, pri_dma_base + 0x01);
261 cnt0 = inb(pri_dma_base + 0x03);
262 outb(0x21, pri_dma_base + 0x01);
263 cnt1 = inb(pri_dma_base + 0x03);
264 outb(0x20, sec_dma_base + 0x01);
265 cnt2 = inb(sec_dma_base + 0x03);
266 outb(0x21, sec_dma_base + 0x01);
267 cnt3 = inb(sec_dma_base + 0x03);
268
269 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
270
271 /*
272 * The 30-bit decrementing counter is read in 4 pieces.
273 * Incorrect value may be read when the most significant bytes
274 * are changing...
275 */
276 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
277
278 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
279 cnt0, cnt1, cnt2, cnt3);
280
281 return count;
282 }
283
284 /**
285 * detect_pll_input_clock - Detect the PLL input clock in Hz.
286 * @dma_base: for the port address
287 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
288 */
289 static long __devinit detect_pll_input_clock(unsigned long dma_base)
290 {
291 struct timeval start_time, end_time;
292 long start_count, end_count;
293 long pll_input, usec_elapsed;
294 u8 scr1;
295
296 start_count = read_counter(dma_base);
297 do_gettimeofday(&start_time);
298
299 /* Start the test mode */
300 outb(0x01, dma_base + 0x01);
301 scr1 = inb(dma_base + 0x03);
302 DBG("scr1[%02X]\n", scr1);
303 outb(scr1 | 0x40, dma_base + 0x03);
304
305 /* Let the counter run for 10 ms. */
306 mdelay(10);
307
308 end_count = read_counter(dma_base);
309 do_gettimeofday(&end_time);
310
311 /* Stop the test mode */
312 outb(0x01, dma_base + 0x01);
313 scr1 = inb(dma_base + 0x03);
314 DBG("scr1[%02X]\n", scr1);
315 outb(scr1 & ~0x40, dma_base + 0x03);
316
317 /*
318 * Calculate the input clock in Hz
319 * (the clock counter is 30 bit wide and counts down)
320 */
321 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
322 (end_time.tv_usec - start_time.tv_usec);
323 pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
324 (10000000 / usec_elapsed);
325
326 DBG("start[%ld] end[%ld]\n", start_count, end_count);
327
328 return pll_input;
329 }
330
331 #ifdef CONFIG_PPC_PMAC
332 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
333 {
334 struct device_node *np = pci_device_to_OF_node(pdev);
335 unsigned int class_rev = 0;
336 u8 conf;
337
338 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
339 return;
340
341 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
342 class_rev &= 0xff;
343
344 if (class_rev >= 0x03) {
345 /* Setup chip magic config stuff (from darwin) */
346 pci_read_config_byte (pdev, 0x40, &conf);
347 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
348 }
349 }
350 #endif /* CONFIG_PPC_PMAC */
351
352 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
353 {
354 unsigned long dma_base = pci_resource_start(dev, 4);
355 unsigned long sec_dma_base = dma_base + 0x08;
356 long pll_input, pll_output, ratio;
357 int f, r;
358 u8 pll_ctl0, pll_ctl1;
359
360 if (dma_base == 0)
361 return -EFAULT;
362
363 #ifdef CONFIG_PPC_PMAC
364 apple_kiwi_init(dev);
365 #endif
366
367 /* Calculate the required PLL output frequency */
368 switch(max_dma_rate(dev)) {
369 case 4: /* it's 133 MHz for Ultra133 chips */
370 pll_output = 133333333;
371 break;
372 case 3: /* and 100 MHz for Ultra100 chips */
373 default:
374 pll_output = 100000000;
375 break;
376 }
377
378 /*
379 * Detect PLL input clock.
380 * On some systems, where PCI bus is running at non-standard clock rate
381 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
382 * PDC20268 and newer chips employ PLL circuit to help correct timing
383 * registers setting.
384 */
385 pll_input = detect_pll_input_clock(dma_base);
386 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
387
388 /* Sanity check */
389 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
390 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
391 name, pll_input);
392 goto out;
393 }
394
395 #ifdef DEBUG
396 DBG("pll_output is %ld Hz\n", pll_output);
397
398 /* Show the current clock value of PLL control register
399 * (maybe already configured by the BIOS)
400 */
401 outb(0x02, sec_dma_base + 0x01);
402 pll_ctl0 = inb(sec_dma_base + 0x03);
403 outb(0x03, sec_dma_base + 0x01);
404 pll_ctl1 = inb(sec_dma_base + 0x03);
405
406 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
407 #endif
408
409 /*
410 * Calculate the ratio of F, R and NO
411 * POUT = (F + 2) / (( R + 2) * NO)
412 */
413 ratio = pll_output / (pll_input / 1000);
414 if (ratio < 8600L) { /* 8.6x */
415 /* Using NO = 0x01, R = 0x0d */
416 r = 0x0d;
417 } else if (ratio < 12900L) { /* 12.9x */
418 /* Using NO = 0x01, R = 0x08 */
419 r = 0x08;
420 } else if (ratio < 16100L) { /* 16.1x */
421 /* Using NO = 0x01, R = 0x06 */
422 r = 0x06;
423 } else if (ratio < 64000L) { /* 64x */
424 r = 0x00;
425 } else {
426 /* Invalid ratio */
427 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
428 goto out;
429 }
430
431 f = (ratio * (r + 2)) / 1000 - 2;
432
433 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
434
435 if (unlikely(f < 0 || f > 127)) {
436 /* Invalid F */
437 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
438 goto out;
439 }
440
441 pll_ctl0 = (u8) f;
442 pll_ctl1 = (u8) r;
443
444 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
445
446 outb(0x02, sec_dma_base + 0x01);
447 outb(pll_ctl0, sec_dma_base + 0x03);
448 outb(0x03, sec_dma_base + 0x01);
449 outb(pll_ctl1, sec_dma_base + 0x03);
450
451 /* Wait the PLL circuit to be stable */
452 mdelay(30);
453
454 #ifdef DEBUG
455 /*
456 * Show the current clock value of PLL control register
457 */
458 outb(0x02, sec_dma_base + 0x01);
459 pll_ctl0 = inb(sec_dma_base + 0x03);
460 outb(0x03, sec_dma_base + 0x01);
461 pll_ctl1 = inb(sec_dma_base + 0x03);
462
463 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
464 #endif
465
466 out:
467 return dev->irq;
468 }
469
470 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
471 {
472 hwif->set_pio_mode = &pdcnew_set_pio_mode;
473 hwif->set_dma_mode = &pdcnew_set_mode;
474
475 hwif->quirkproc = &pdcnew_quirkproc;
476 hwif->resetproc = &pdcnew_reset;
477
478 hwif->err_stops_fifo = 1;
479
480 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
481
482 if (hwif->dma_base == 0)
483 return;
484
485 hwif->atapi_dma = 1;
486
487 hwif->ultra_mask = hwif->cds->udma_mask;
488 hwif->mwdma_mask = 0x07;
489
490 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
491 hwif->cbl = pdcnew_cable_detect(hwif);
492 }
493
494 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
495 {
496 return ide_setup_pci_device(dev, d);
497 }
498
499 static int __devinit init_setup_pdc20270(struct pci_dev *dev, ide_pci_device_t *d)
500 {
501 struct pci_dev *bridge = dev->bus->self;
502
503 if (bridge != NULL &&
504 bridge->vendor == PCI_VENDOR_ID_DEC &&
505 bridge->device == PCI_DEVICE_ID_DEC_21150) {
506 struct pci_dev *dev2;
507
508 if (PCI_SLOT(dev->devfn) & 2)
509 return -ENODEV;
510
511 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 2,
512 PCI_FUNC(dev->devfn)));
513 if (dev2 != NULL &&
514 dev2->vendor == dev->vendor &&
515 dev2->device == dev->device) {
516 int ret;
517
518 if (dev2->irq != dev->irq) {
519 dev2->irq = dev->irq;
520
521 printk(KERN_WARNING "%s: PCI config space "
522 "interrupt fixed.\n", d->name);
523 }
524
525 ret = ide_setup_pci_devices(dev, dev2, d);
526 if (ret < 0)
527 pci_dev_put(dev2);
528 return ret;
529 }
530 }
531 return ide_setup_pci_device(dev, d);
532 }
533
534 static int __devinit init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d)
535 {
536 struct pci_dev *bridge = dev->bus->self;
537
538 if (bridge != NULL &&
539 bridge->vendor == PCI_VENDOR_ID_INTEL &&
540 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
541 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
542
543 printk(KERN_INFO "%s: attached to I2O RAID controller, "
544 "skipping.\n", d->name);
545 return -ENODEV;
546 }
547 return ide_setup_pci_device(dev, d);
548 }
549
550 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
551 { /* 0 */
552 .name = "PDC20268",
553 .init_setup = init_setup_pdcnew,
554 .init_chipset = init_chipset_pdcnew,
555 .init_hwif = init_hwif_pdc202new,
556 .autodma = AUTODMA,
557 .bootable = OFF_BOARD,
558 .pio_mask = ATA_PIO4,
559 .udma_mask = 0x3f, /* udma0-5 */
560 .host_flags = IDE_HFLAG_POST_SET_MODE,
561 },{ /* 1 */
562 .name = "PDC20269",
563 .init_setup = init_setup_pdcnew,
564 .init_chipset = init_chipset_pdcnew,
565 .init_hwif = init_hwif_pdc202new,
566 .autodma = AUTODMA,
567 .bootable = OFF_BOARD,
568 .pio_mask = ATA_PIO4,
569 .udma_mask = 0x7f, /* udma0-6*/
570 .host_flags = IDE_HFLAG_POST_SET_MODE,
571 },{ /* 2 */
572 .name = "PDC20270",
573 .init_setup = init_setup_pdc20270,
574 .init_chipset = init_chipset_pdcnew,
575 .init_hwif = init_hwif_pdc202new,
576 .autodma = AUTODMA,
577 .bootable = OFF_BOARD,
578 .pio_mask = ATA_PIO4,
579 .udma_mask = 0x3f, /* udma0-5 */
580 .host_flags = IDE_HFLAG_POST_SET_MODE,
581 },{ /* 3 */
582 .name = "PDC20271",
583 .init_setup = init_setup_pdcnew,
584 .init_chipset = init_chipset_pdcnew,
585 .init_hwif = init_hwif_pdc202new,
586 .autodma = AUTODMA,
587 .bootable = OFF_BOARD,
588 .pio_mask = ATA_PIO4,
589 .udma_mask = 0x7f, /* udma0-6*/
590 .host_flags = IDE_HFLAG_POST_SET_MODE,
591 },{ /* 4 */
592 .name = "PDC20275",
593 .init_setup = init_setup_pdcnew,
594 .init_chipset = init_chipset_pdcnew,
595 .init_hwif = init_hwif_pdc202new,
596 .autodma = AUTODMA,
597 .bootable = OFF_BOARD,
598 .pio_mask = ATA_PIO4,
599 .udma_mask = 0x7f, /* udma0-6*/
600 .host_flags = IDE_HFLAG_POST_SET_MODE,
601 },{ /* 5 */
602 .name = "PDC20276",
603 .init_setup = init_setup_pdc20276,
604 .init_chipset = init_chipset_pdcnew,
605 .init_hwif = init_hwif_pdc202new,
606 .autodma = AUTODMA,
607 .bootable = OFF_BOARD,
608 .pio_mask = ATA_PIO4,
609 .udma_mask = 0x7f, /* udma0-6*/
610 .host_flags = IDE_HFLAG_POST_SET_MODE,
611 },{ /* 6 */
612 .name = "PDC20277",
613 .init_setup = init_setup_pdcnew,
614 .init_chipset = init_chipset_pdcnew,
615 .init_hwif = init_hwif_pdc202new,
616 .autodma = AUTODMA,
617 .bootable = OFF_BOARD,
618 .pio_mask = ATA_PIO4,
619 .udma_mask = 0x7f, /* udma0-6*/
620 .host_flags = IDE_HFLAG_POST_SET_MODE,
621 }
622 };
623
624 /**
625 * pdc202new_init_one - called when a pdc202xx is found
626 * @dev: the pdc202new device
627 * @id: the matching pci id
628 *
629 * Called when the PCI registration layer (or the IDE initialization)
630 * finds a device matching our IDE device tables.
631 */
632
633 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
634 {
635 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
636
637 return d->init_setup(dev, d);
638 }
639
640 static const struct pci_device_id pdc202new_pci_tbl[] = {
641 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
642 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
643 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
644 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
645 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
646 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
647 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
648 { 0, },
649 };
650 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
651
652 static struct pci_driver driver = {
653 .name = "Promise_IDE",
654 .id_table = pdc202new_pci_tbl,
655 .probe = pdc202new_init_one,
656 };
657
658 static int __init pdc202new_ide_init(void)
659 {
660 return ide_pci_register_driver(&driver);
661 }
662
663 module_init(pdc202new_ide_init);
664
665 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
666 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
667 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)