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ide: make void and rename ide_dma_timeout() method
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / hpt366.c
1 /*
2 * linux/drivers/ide/pci/hpt366.c Version 1.06 Jun 27, 2007
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
8 *
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
13 *
14 *
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
20 *
21 * Note that final HPT370 support was done by force extraction of GPL.
22 *
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
37 *
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
43 *
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
46 *
47 * On hpt366:
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
51 *
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * keeping me sane.
56 * Alan Cox <alan@redhat.com>
57 *
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the rate masking/filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * supported DMA mode, and the chip settings table pointer filled, then, at
103 * the init_chipset stage, allocate per-chip instance and fill it with the
104 * rest of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
116 */
117
118 #include <linux/types.h>
119 #include <linux/module.h>
120 #include <linux/kernel.h>
121 #include <linux/delay.h>
122 #include <linux/timer.h>
123 #include <linux/mm.h>
124 #include <linux/ioport.h>
125 #include <linux/blkdev.h>
126 #include <linux/hdreg.h>
127
128 #include <linux/interrupt.h>
129 #include <linux/pci.h>
130 #include <linux/init.h>
131 #include <linux/ide.h>
132
133 #include <asm/uaccess.h>
134 #include <asm/io.h>
135 #include <asm/irq.h>
136
137 /* various tuning parameters */
138 #define HPT_RESET_STATE_ENGINE
139 #undef HPT_DELAY_INTERRUPT
140 #define HPT_SERIALIZE_IO 0
141
142 static const char *quirk_drives[] = {
143 "QUANTUM FIREBALLlct08 08",
144 "QUANTUM FIREBALLP KA6.4",
145 "QUANTUM FIREBALLP LM20.4",
146 "QUANTUM FIREBALLP LM20.5",
147 NULL
148 };
149
150 static const char *bad_ata100_5[] = {
151 "IBM-DTLA-307075",
152 "IBM-DTLA-307060",
153 "IBM-DTLA-307045",
154 "IBM-DTLA-307030",
155 "IBM-DTLA-307020",
156 "IBM-DTLA-307015",
157 "IBM-DTLA-305040",
158 "IBM-DTLA-305030",
159 "IBM-DTLA-305020",
160 "IC35L010AVER07-0",
161 "IC35L020AVER07-0",
162 "IC35L030AVER07-0",
163 "IC35L040AVER07-0",
164 "IC35L060AVER07-0",
165 "WDC AC310200R",
166 NULL
167 };
168
169 static const char *bad_ata66_4[] = {
170 "IBM-DTLA-307075",
171 "IBM-DTLA-307060",
172 "IBM-DTLA-307045",
173 "IBM-DTLA-307030",
174 "IBM-DTLA-307020",
175 "IBM-DTLA-307015",
176 "IBM-DTLA-305040",
177 "IBM-DTLA-305030",
178 "IBM-DTLA-305020",
179 "IC35L010AVER07-0",
180 "IC35L020AVER07-0",
181 "IC35L030AVER07-0",
182 "IC35L040AVER07-0",
183 "IC35L060AVER07-0",
184 "WDC AC310200R",
185 "MAXTOR STM3320620A",
186 NULL
187 };
188
189 static const char *bad_ata66_3[] = {
190 "WDC AC310200R",
191 NULL
192 };
193
194 static const char *bad_ata33[] = {
195 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
196 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
197 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
198 "Maxtor 90510D4",
199 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
200 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
201 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
202 NULL
203 };
204
205 static u8 xfer_speeds[] = {
206 XFER_UDMA_6,
207 XFER_UDMA_5,
208 XFER_UDMA_4,
209 XFER_UDMA_3,
210 XFER_UDMA_2,
211 XFER_UDMA_1,
212 XFER_UDMA_0,
213
214 XFER_MW_DMA_2,
215 XFER_MW_DMA_1,
216 XFER_MW_DMA_0,
217
218 XFER_PIO_4,
219 XFER_PIO_3,
220 XFER_PIO_2,
221 XFER_PIO_1,
222 XFER_PIO_0
223 };
224
225 /* Key for bus clock timings
226 * 36x 37x
227 * bits bits
228 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
229 * cycles = value + 1
230 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
231 * cycles = value + 1
232 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
233 * register access.
234 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
235 * register access.
236 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
237 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
238 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
239 * MW DMA xfer.
240 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
241 * task file register access.
242 * 28 28 UDMA enable.
243 * 29 29 DMA enable.
244 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
245 * PIO xfer.
246 * 31 31 FIFO enable.
247 */
248
249 static u32 forty_base_hpt36x[] = {
250 /* XFER_UDMA_6 */ 0x900fd943,
251 /* XFER_UDMA_5 */ 0x900fd943,
252 /* XFER_UDMA_4 */ 0x900fd943,
253 /* XFER_UDMA_3 */ 0x900ad943,
254 /* XFER_UDMA_2 */ 0x900bd943,
255 /* XFER_UDMA_1 */ 0x9008d943,
256 /* XFER_UDMA_0 */ 0x9008d943,
257
258 /* XFER_MW_DMA_2 */ 0xa008d943,
259 /* XFER_MW_DMA_1 */ 0xa010d955,
260 /* XFER_MW_DMA_0 */ 0xa010d9fc,
261
262 /* XFER_PIO_4 */ 0xc008d963,
263 /* XFER_PIO_3 */ 0xc010d974,
264 /* XFER_PIO_2 */ 0xc010d997,
265 /* XFER_PIO_1 */ 0xc010d9c7,
266 /* XFER_PIO_0 */ 0xc018d9d9
267 };
268
269 static u32 thirty_three_base_hpt36x[] = {
270 /* XFER_UDMA_6 */ 0x90c9a731,
271 /* XFER_UDMA_5 */ 0x90c9a731,
272 /* XFER_UDMA_4 */ 0x90c9a731,
273 /* XFER_UDMA_3 */ 0x90cfa731,
274 /* XFER_UDMA_2 */ 0x90caa731,
275 /* XFER_UDMA_1 */ 0x90cba731,
276 /* XFER_UDMA_0 */ 0x90c8a731,
277
278 /* XFER_MW_DMA_2 */ 0xa0c8a731,
279 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
280 /* XFER_MW_DMA_0 */ 0xa0c8a797,
281
282 /* XFER_PIO_4 */ 0xc0c8a731,
283 /* XFER_PIO_3 */ 0xc0c8a742,
284 /* XFER_PIO_2 */ 0xc0d0a753,
285 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
286 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
287 };
288
289 static u32 twenty_five_base_hpt36x[] = {
290 /* XFER_UDMA_6 */ 0x90c98521,
291 /* XFER_UDMA_5 */ 0x90c98521,
292 /* XFER_UDMA_4 */ 0x90c98521,
293 /* XFER_UDMA_3 */ 0x90cf8521,
294 /* XFER_UDMA_2 */ 0x90cf8521,
295 /* XFER_UDMA_1 */ 0x90cb8521,
296 /* XFER_UDMA_0 */ 0x90cb8521,
297
298 /* XFER_MW_DMA_2 */ 0xa0ca8521,
299 /* XFER_MW_DMA_1 */ 0xa0ca8532,
300 /* XFER_MW_DMA_0 */ 0xa0ca8575,
301
302 /* XFER_PIO_4 */ 0xc0ca8521,
303 /* XFER_PIO_3 */ 0xc0ca8532,
304 /* XFER_PIO_2 */ 0xc0ca8542,
305 /* XFER_PIO_1 */ 0xc0d08572,
306 /* XFER_PIO_0 */ 0xc0d08585
307 };
308
309 static u32 thirty_three_base_hpt37x[] = {
310 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
311 /* XFER_UDMA_5 */ 0x12446231,
312 /* XFER_UDMA_4 */ 0x12446231,
313 /* XFER_UDMA_3 */ 0x126c6231,
314 /* XFER_UDMA_2 */ 0x12486231,
315 /* XFER_UDMA_1 */ 0x124c6233,
316 /* XFER_UDMA_0 */ 0x12506297,
317
318 /* XFER_MW_DMA_2 */ 0x22406c31,
319 /* XFER_MW_DMA_1 */ 0x22406c33,
320 /* XFER_MW_DMA_0 */ 0x22406c97,
321
322 /* XFER_PIO_4 */ 0x06414e31,
323 /* XFER_PIO_3 */ 0x06414e42,
324 /* XFER_PIO_2 */ 0x06414e53,
325 /* XFER_PIO_1 */ 0x06814e93,
326 /* XFER_PIO_0 */ 0x06814ea7
327 };
328
329 static u32 fifty_base_hpt37x[] = {
330 /* XFER_UDMA_6 */ 0x12848242,
331 /* XFER_UDMA_5 */ 0x12848242,
332 /* XFER_UDMA_4 */ 0x12ac8242,
333 /* XFER_UDMA_3 */ 0x128c8242,
334 /* XFER_UDMA_2 */ 0x120c8242,
335 /* XFER_UDMA_1 */ 0x12148254,
336 /* XFER_UDMA_0 */ 0x121882ea,
337
338 /* XFER_MW_DMA_2 */ 0x22808242,
339 /* XFER_MW_DMA_1 */ 0x22808254,
340 /* XFER_MW_DMA_0 */ 0x228082ea,
341
342 /* XFER_PIO_4 */ 0x0a81f442,
343 /* XFER_PIO_3 */ 0x0a81f443,
344 /* XFER_PIO_2 */ 0x0a81f454,
345 /* XFER_PIO_1 */ 0x0ac1f465,
346 /* XFER_PIO_0 */ 0x0ac1f48a
347 };
348
349 static u32 sixty_six_base_hpt37x[] = {
350 /* XFER_UDMA_6 */ 0x1c869c62,
351 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
352 /* XFER_UDMA_4 */ 0x1c8a9c62,
353 /* XFER_UDMA_3 */ 0x1c8e9c62,
354 /* XFER_UDMA_2 */ 0x1c929c62,
355 /* XFER_UDMA_1 */ 0x1c9a9c62,
356 /* XFER_UDMA_0 */ 0x1c829c62,
357
358 /* XFER_MW_DMA_2 */ 0x2c829c62,
359 /* XFER_MW_DMA_1 */ 0x2c829c66,
360 /* XFER_MW_DMA_0 */ 0x2c829d2e,
361
362 /* XFER_PIO_4 */ 0x0c829c62,
363 /* XFER_PIO_3 */ 0x0c829c84,
364 /* XFER_PIO_2 */ 0x0c829ca6,
365 /* XFER_PIO_1 */ 0x0d029d26,
366 /* XFER_PIO_0 */ 0x0d029d5e
367 };
368
369 #define HPT366_DEBUG_DRIVE_INFO 0
370 #define HPT371_ALLOW_ATA133_6 1
371 #define HPT302_ALLOW_ATA133_6 1
372 #define HPT372_ALLOW_ATA133_6 1
373 #define HPT370_ALLOW_ATA100_5 0
374 #define HPT366_ALLOW_ATA66_4 1
375 #define HPT366_ALLOW_ATA66_3 1
376 #define HPT366_MAX_DEVS 8
377
378 /* Supported ATA clock frequencies */
379 enum ata_clock {
380 ATA_CLOCK_25MHZ,
381 ATA_CLOCK_33MHZ,
382 ATA_CLOCK_40MHZ,
383 ATA_CLOCK_50MHZ,
384 ATA_CLOCK_66MHZ,
385 NUM_ATA_CLOCKS
386 };
387
388 /*
389 * Hold all the HighPoint chip information in one place.
390 */
391
392 struct hpt_info {
393 u8 chip_type; /* Chip type */
394 u8 max_mode; /* Speeds allowed */
395 u8 dpll_clk; /* DPLL clock in MHz */
396 u8 pci_clk; /* PCI clock in MHz */
397 u32 **settings; /* Chipset settings table */
398 };
399
400 /* Supported HighPoint chips */
401 enum {
402 HPT36x,
403 HPT370,
404 HPT370A,
405 HPT374,
406 HPT372,
407 HPT372A,
408 HPT302,
409 HPT371,
410 HPT372N,
411 HPT302N,
412 HPT371N
413 };
414
415 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
416 twenty_five_base_hpt36x,
417 thirty_three_base_hpt36x,
418 forty_base_hpt36x,
419 NULL,
420 NULL
421 };
422
423 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
424 NULL,
425 thirty_three_base_hpt37x,
426 NULL,
427 fifty_base_hpt37x,
428 sixty_six_base_hpt37x
429 };
430
431 static struct hpt_info hpt36x __devinitdata = {
432 .chip_type = HPT36x,
433 .max_mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
434 .dpll_clk = 0, /* no DPLL */
435 .settings = hpt36x_settings
436 };
437
438 static struct hpt_info hpt370 __devinitdata = {
439 .chip_type = HPT370,
440 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
441 .dpll_clk = 48,
442 .settings = hpt37x_settings
443 };
444
445 static struct hpt_info hpt370a __devinitdata = {
446 .chip_type = HPT370A,
447 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
448 .dpll_clk = 48,
449 .settings = hpt37x_settings
450 };
451
452 static struct hpt_info hpt374 __devinitdata = {
453 .chip_type = HPT374,
454 .max_mode = 3,
455 .dpll_clk = 48,
456 .settings = hpt37x_settings
457 };
458
459 static struct hpt_info hpt372 __devinitdata = {
460 .chip_type = HPT372,
461 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
462 .dpll_clk = 55,
463 .settings = hpt37x_settings
464 };
465
466 static struct hpt_info hpt372a __devinitdata = {
467 .chip_type = HPT372A,
468 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
469 .dpll_clk = 66,
470 .settings = hpt37x_settings
471 };
472
473 static struct hpt_info hpt302 __devinitdata = {
474 .chip_type = HPT302,
475 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
476 .dpll_clk = 66,
477 .settings = hpt37x_settings
478 };
479
480 static struct hpt_info hpt371 __devinitdata = {
481 .chip_type = HPT371,
482 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
483 .dpll_clk = 66,
484 .settings = hpt37x_settings
485 };
486
487 static struct hpt_info hpt372n __devinitdata = {
488 .chip_type = HPT372N,
489 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
490 .dpll_clk = 77,
491 .settings = hpt37x_settings
492 };
493
494 static struct hpt_info hpt302n __devinitdata = {
495 .chip_type = HPT302N,
496 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
497 .dpll_clk = 77,
498 .settings = hpt37x_settings
499 };
500
501 static struct hpt_info hpt371n __devinitdata = {
502 .chip_type = HPT371N,
503 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
504 .dpll_clk = 77,
505 .settings = hpt37x_settings
506 };
507
508 static int check_in_drive_list(ide_drive_t *drive, const char **list)
509 {
510 struct hd_driveid *id = drive->id;
511
512 while (*list)
513 if (!strcmp(*list++,id->model))
514 return 1;
515 return 0;
516 }
517
518 /*
519 * Note for the future; the SATA hpt37x we must set
520 * either PIO or UDMA modes 0,4,5
521 */
522
523 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
524 {
525 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
526 u8 chip_type = info->chip_type;
527 u8 mode = info->max_mode;
528 u8 mask;
529
530 switch (mode) {
531 case 0x04:
532 mask = 0x7f;
533 break;
534 case 0x03:
535 mask = 0x3f;
536 if (chip_type >= HPT374)
537 break;
538 if (!check_in_drive_list(drive, bad_ata100_5))
539 goto check_bad_ata33;
540 /* fall thru */
541 case 0x02:
542 mask = 0x1f;
543
544 /*
545 * CHECK ME, Does this need to be changed to HPT374 ??
546 */
547 if (chip_type >= HPT370)
548 goto check_bad_ata33;
549 if (HPT366_ALLOW_ATA66_4 &&
550 !check_in_drive_list(drive, bad_ata66_4))
551 goto check_bad_ata33;
552
553 mask = 0x0f;
554 if (HPT366_ALLOW_ATA66_3 &&
555 !check_in_drive_list(drive, bad_ata66_3))
556 goto check_bad_ata33;
557 /* fall thru */
558 case 0x01:
559 mask = 0x07;
560
561 check_bad_ata33:
562 if (chip_type >= HPT370A)
563 break;
564 if (!check_in_drive_list(drive, bad_ata33))
565 break;
566 /* fall thru */
567 case 0x00:
568 default:
569 mask = 0x00;
570 break;
571 }
572 return mask;
573 }
574
575 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
576 {
577 int i;
578
579 /*
580 * Lookup the transfer mode table to get the index into
581 * the timing table.
582 *
583 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
584 */
585 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
586 if (xfer_speeds[i] == speed)
587 break;
588 /*
589 * NOTE: info->settings only points to the pointer
590 * to the list of the actual register values
591 */
592 return (*info->settings)[i];
593 }
594
595 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
596 {
597 ide_hwif_t *hwif = HWIF(drive);
598 struct pci_dev *dev = hwif->pci_dev;
599 struct hpt_info *info = pci_get_drvdata(dev);
600 u8 speed = ide_rate_filter(drive, xferspeed);
601 u8 itr_addr = drive->dn ? 0x44 : 0x40;
602 u32 old_itr = 0;
603 u32 itr_mask, new_itr;
604
605 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
606 if (drive->media != ide_disk)
607 speed = min_t(u8, speed, XFER_PIO_4);
608
609 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
610 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
611
612 new_itr = get_speed_setting(speed, info);
613
614 /*
615 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
616 * to avoid problems handling I/O errors later
617 */
618 pci_read_config_dword(dev, itr_addr, &old_itr);
619 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
620 new_itr &= ~0xc0000000;
621
622 pci_write_config_dword(dev, itr_addr, new_itr);
623
624 return ide_config_drive_speed(drive, speed);
625 }
626
627 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
628 {
629 ide_hwif_t *hwif = HWIF(drive);
630 struct pci_dev *dev = hwif->pci_dev;
631 struct hpt_info *info = pci_get_drvdata(dev);
632 u8 speed = ide_rate_filter(drive, xferspeed);
633 u8 itr_addr = 0x40 + (drive->dn * 4);
634 u32 old_itr = 0;
635 u32 itr_mask, new_itr;
636
637 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
638 if (drive->media != ide_disk)
639 speed = min_t(u8, speed, XFER_PIO_4);
640
641 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
642 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
643
644 new_itr = get_speed_setting(speed, info);
645
646 pci_read_config_dword(dev, itr_addr, &old_itr);
647 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
648
649 if (speed < XFER_MW_DMA_0)
650 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
651 pci_write_config_dword(dev, itr_addr, new_itr);
652
653 return ide_config_drive_speed(drive, speed);
654 }
655
656 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
657 {
658 ide_hwif_t *hwif = HWIF(drive);
659 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
660
661 if (info->chip_type >= HPT370)
662 return hpt37x_tune_chipset(drive, speed);
663 else /* hpt368: hpt_minimum_revision(dev, 2) */
664 return hpt36x_tune_chipset(drive, speed);
665 }
666
667 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
668 {
669 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
670 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
671 }
672
673 static int hpt3xx_quirkproc(ide_drive_t *drive)
674 {
675 struct hd_driveid *id = drive->id;
676 const char **list = quirk_drives;
677
678 while (*list)
679 if (strstr(id->model, *list++))
680 return 1;
681 return 0;
682 }
683
684 static void hpt3xx_intrproc(ide_drive_t *drive)
685 {
686 ide_hwif_t *hwif = HWIF(drive);
687
688 if (drive->quirk_list)
689 return;
690 /* drives in the quirk_list may not like intr setups/cleanups */
691 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
692 }
693
694 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
695 {
696 ide_hwif_t *hwif = HWIF(drive);
697 struct pci_dev *dev = hwif->pci_dev;
698 struct hpt_info *info = pci_get_drvdata(dev);
699
700 if (drive->quirk_list) {
701 if (info->chip_type >= HPT370) {
702 u8 scr1 = 0;
703
704 pci_read_config_byte(dev, 0x5a, &scr1);
705 if (((scr1 & 0x10) >> 4) != mask) {
706 if (mask)
707 scr1 |= 0x10;
708 else
709 scr1 &= ~0x10;
710 pci_write_config_byte(dev, 0x5a, scr1);
711 }
712 } else {
713 if (mask)
714 disable_irq(hwif->irq);
715 else
716 enable_irq (hwif->irq);
717 }
718 } else
719 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
720 IDE_CONTROL_REG);
721 }
722
723 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
724 {
725 drive->init_speed = 0;
726
727 if (ide_tune_dma(drive))
728 return 0;
729
730 if (ide_use_fast_pio(drive))
731 hpt3xx_tune_drive(drive, 255);
732
733 return -1;
734 }
735
736 /*
737 * This is specific to the HPT366 UDMA chipset
738 * by HighPoint|Triones Technologies, Inc.
739 */
740 static void hpt366_dma_lost_irq(ide_drive_t *drive)
741 {
742 struct pci_dev *dev = HWIF(drive)->pci_dev;
743 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
744
745 pci_read_config_byte(dev, 0x50, &mcr1);
746 pci_read_config_byte(dev, 0x52, &mcr3);
747 pci_read_config_byte(dev, 0x5a, &scr1);
748 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
749 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
750 if (scr1 & 0x10)
751 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
752 ide_dma_lost_irq(drive);
753 }
754
755 static void hpt370_clear_engine(ide_drive_t *drive)
756 {
757 ide_hwif_t *hwif = HWIF(drive);
758
759 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
760 udelay(10);
761 }
762
763 static void hpt370_irq_timeout(ide_drive_t *drive)
764 {
765 ide_hwif_t *hwif = HWIF(drive);
766 u16 bfifo = 0;
767 u8 dma_cmd;
768
769 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
770 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
771
772 /* get DMA command mode */
773 dma_cmd = hwif->INB(hwif->dma_command);
774 /* stop DMA */
775 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
776 hpt370_clear_engine(drive);
777 }
778
779 static void hpt370_ide_dma_start(ide_drive_t *drive)
780 {
781 #ifdef HPT_RESET_STATE_ENGINE
782 hpt370_clear_engine(drive);
783 #endif
784 ide_dma_start(drive);
785 }
786
787 static int hpt370_ide_dma_end(ide_drive_t *drive)
788 {
789 ide_hwif_t *hwif = HWIF(drive);
790 u8 dma_stat = hwif->INB(hwif->dma_status);
791
792 if (dma_stat & 0x01) {
793 /* wait a little */
794 udelay(20);
795 dma_stat = hwif->INB(hwif->dma_status);
796 if (dma_stat & 0x01)
797 hpt370_irq_timeout(drive);
798 }
799 return __ide_dma_end(drive);
800 }
801
802 static void hpt370_dma_timeout(ide_drive_t *drive)
803 {
804 hpt370_irq_timeout(drive);
805 ide_dma_timeout(drive);
806 }
807
808 /* returns 1 if DMA IRQ issued, 0 otherwise */
809 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
810 {
811 ide_hwif_t *hwif = HWIF(drive);
812 u16 bfifo = 0;
813 u8 dma_stat;
814
815 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
816 if (bfifo & 0x1FF) {
817 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
818 return 0;
819 }
820
821 dma_stat = inb(hwif->dma_status);
822 /* return 1 if INTR asserted */
823 if (dma_stat & 4)
824 return 1;
825
826 if (!drive->waiting_for_dma)
827 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
828 drive->name, __FUNCTION__);
829 return 0;
830 }
831
832 static int hpt374_ide_dma_end(ide_drive_t *drive)
833 {
834 ide_hwif_t *hwif = HWIF(drive);
835 struct pci_dev *dev = hwif->pci_dev;
836 u8 mcr = 0, mcr_addr = hwif->select_data;
837 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
838
839 pci_read_config_byte(dev, 0x6a, &bwsr);
840 pci_read_config_byte(dev, mcr_addr, &mcr);
841 if (bwsr & mask)
842 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
843 return __ide_dma_end(drive);
844 }
845
846 /**
847 * hpt3xxn_set_clock - perform clock switching dance
848 * @hwif: hwif to switch
849 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
850 *
851 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
852 */
853
854 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
855 {
856 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
857
858 if ((scr2 & 0x7f) == mode)
859 return;
860
861 /* Tristate the bus */
862 hwif->OUTB(0x80, hwif->dma_master + 0x73);
863 hwif->OUTB(0x80, hwif->dma_master + 0x77);
864
865 /* Switch clock and reset channels */
866 hwif->OUTB(mode, hwif->dma_master + 0x7b);
867 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
868
869 /*
870 * Reset the state machines.
871 * NOTE: avoid accidentally enabling the disabled channels.
872 */
873 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
874 hwif->dma_master + 0x70);
875 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
876 hwif->dma_master + 0x74);
877
878 /* Complete reset */
879 hwif->OUTB(0x00, hwif->dma_master + 0x79);
880
881 /* Reconnect channels to bus */
882 hwif->OUTB(0x00, hwif->dma_master + 0x73);
883 hwif->OUTB(0x00, hwif->dma_master + 0x77);
884 }
885
886 /**
887 * hpt3xxn_rw_disk - prepare for I/O
888 * @drive: drive for command
889 * @rq: block request structure
890 *
891 * This is called when a disk I/O is issued to HPT3xxN.
892 * We need it because of the clock switching.
893 */
894
895 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
896 {
897 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
898 }
899
900 /*
901 * Set/get power state for a drive.
902 * NOTE: affects both drives on each channel.
903 *
904 * When we turn the power back on, we need to re-initialize things.
905 */
906 #define TRISTATE_BIT 0x8000
907
908 static int hpt3xx_busproc(ide_drive_t *drive, int state)
909 {
910 ide_hwif_t *hwif = HWIF(drive);
911 struct pci_dev *dev = hwif->pci_dev;
912 u8 mcr_addr = hwif->select_data + 2;
913 u8 resetmask = hwif->channel ? 0x80 : 0x40;
914 u8 bsr2 = 0;
915 u16 mcr = 0;
916
917 hwif->bus_state = state;
918
919 /* Grab the status. */
920 pci_read_config_word(dev, mcr_addr, &mcr);
921 pci_read_config_byte(dev, 0x59, &bsr2);
922
923 /*
924 * Set the state. We don't set it if we don't need to do so.
925 * Make sure that the drive knows that it has failed if it's off.
926 */
927 switch (state) {
928 case BUSSTATE_ON:
929 if (!(bsr2 & resetmask))
930 return 0;
931 hwif->drives[0].failures = hwif->drives[1].failures = 0;
932
933 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
934 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
935 return 0;
936 case BUSSTATE_OFF:
937 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
938 return 0;
939 mcr &= ~TRISTATE_BIT;
940 break;
941 case BUSSTATE_TRISTATE:
942 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
943 return 0;
944 mcr |= TRISTATE_BIT;
945 break;
946 default:
947 return -EINVAL;
948 }
949
950 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
951 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
952
953 pci_write_config_word(dev, mcr_addr, mcr);
954 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
955 return 0;
956 }
957
958 /**
959 * hpt37x_calibrate_dpll - calibrate the DPLL
960 * @dev: PCI device
961 *
962 * Perform a calibration cycle on the DPLL.
963 * Returns 1 if this succeeds
964 */
965 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
966 {
967 u32 dpll = (f_high << 16) | f_low | 0x100;
968 u8 scr2;
969 int i;
970
971 pci_write_config_dword(dev, 0x5c, dpll);
972
973 /* Wait for oscillator ready */
974 for(i = 0; i < 0x5000; ++i) {
975 udelay(50);
976 pci_read_config_byte(dev, 0x5b, &scr2);
977 if (scr2 & 0x80)
978 break;
979 }
980 /* See if it stays ready (we'll just bail out if it's not yet) */
981 for(i = 0; i < 0x1000; ++i) {
982 pci_read_config_byte(dev, 0x5b, &scr2);
983 /* DPLL destabilized? */
984 if(!(scr2 & 0x80))
985 return 0;
986 }
987 /* Turn off tuning, we have the DPLL set */
988 pci_read_config_dword (dev, 0x5c, &dpll);
989 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
990 return 1;
991 }
992
993 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
994 {
995 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
996 unsigned long io_base = pci_resource_start(dev, 4);
997 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
998 enum ata_clock clock;
999
1000 if (info == NULL) {
1001 printk(KERN_ERR "%s: out of memory!\n", name);
1002 return -ENOMEM;
1003 }
1004
1005 /*
1006 * Copy everything from a static "template" structure
1007 * to just allocated per-chip hpt_info structure.
1008 */
1009 *info = *(struct hpt_info *)pci_get_drvdata(dev);
1010
1011 /*
1012 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1013 * We don't seem to be using it.
1014 */
1015 if (dev->resource[PCI_ROM_RESOURCE].start)
1016 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1017 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1018
1019 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1020 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1021 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1022 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1023
1024 /*
1025 * First, try to estimate the PCI clock frequency...
1026 */
1027 if (info->chip_type >= HPT370) {
1028 u8 scr1 = 0;
1029 u16 f_cnt = 0;
1030 u32 temp = 0;
1031
1032 /* Interrupt force enable. */
1033 pci_read_config_byte(dev, 0x5a, &scr1);
1034 if (scr1 & 0x10)
1035 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1036
1037 /*
1038 * HighPoint does this for HPT372A.
1039 * NOTE: This register is only writeable via I/O space.
1040 */
1041 if (info->chip_type == HPT372A)
1042 outb(0x0e, io_base + 0x9c);
1043
1044 /*
1045 * Default to PCI clock. Make sure MA15/16 are set to output
1046 * to prevent drives having problems with 40-pin cables.
1047 */
1048 pci_write_config_byte(dev, 0x5b, 0x23);
1049
1050 /*
1051 * We'll have to read f_CNT value in order to determine
1052 * the PCI clock frequency according to the following ratio:
1053 *
1054 * f_CNT = Fpci * 192 / Fdpll
1055 *
1056 * First try reading the register in which the HighPoint BIOS
1057 * saves f_CNT value before reprogramming the DPLL from its
1058 * default setting (which differs for the various chips).
1059 * NOTE: This register is only accessible via I/O space.
1060 *
1061 * In case the signature check fails, we'll have to resort to
1062 * reading the f_CNT register itself in hopes that nobody has
1063 * touched the DPLL yet...
1064 */
1065 temp = inl(io_base + 0x90);
1066 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1067 int i;
1068
1069 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1070 name);
1071
1072 /* Calculate the average value of f_CNT. */
1073 for (temp = i = 0; i < 128; i++) {
1074 pci_read_config_word(dev, 0x78, &f_cnt);
1075 temp += f_cnt & 0x1ff;
1076 mdelay(1);
1077 }
1078 f_cnt = temp / 128;
1079 } else
1080 f_cnt = temp & 0x1ff;
1081
1082 dpll_clk = info->dpll_clk;
1083 pci_clk = (f_cnt * dpll_clk) / 192;
1084
1085 /* Clamp PCI clock to bands. */
1086 if (pci_clk < 40)
1087 pci_clk = 33;
1088 else if(pci_clk < 45)
1089 pci_clk = 40;
1090 else if(pci_clk < 55)
1091 pci_clk = 50;
1092 else
1093 pci_clk = 66;
1094
1095 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1096 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1097 } else {
1098 u32 itr1 = 0;
1099
1100 pci_read_config_dword(dev, 0x40, &itr1);
1101
1102 /* Detect PCI clock by looking at cmd_high_time. */
1103 switch((itr1 >> 8) & 0x07) {
1104 case 0x09:
1105 pci_clk = 40;
1106 break;
1107 case 0x05:
1108 pci_clk = 25;
1109 break;
1110 case 0x07:
1111 default:
1112 pci_clk = 33;
1113 break;
1114 }
1115 }
1116
1117 /* Let's assume we'll use PCI clock for the ATA clock... */
1118 switch (pci_clk) {
1119 case 25:
1120 clock = ATA_CLOCK_25MHZ;
1121 break;
1122 case 33:
1123 default:
1124 clock = ATA_CLOCK_33MHZ;
1125 break;
1126 case 40:
1127 clock = ATA_CLOCK_40MHZ;
1128 break;
1129 case 50:
1130 clock = ATA_CLOCK_50MHZ;
1131 break;
1132 case 66:
1133 clock = ATA_CLOCK_66MHZ;
1134 break;
1135 }
1136
1137 /*
1138 * Only try the DPLL if we don't have a table for the PCI clock that
1139 * we are running at for HPT370/A, always use it for anything newer...
1140 *
1141 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1142 * We also don't like using the DPLL because this causes glitches
1143 * on PRST-/SRST- when the state engine gets reset...
1144 */
1145 if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1146 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1147 int adjust;
1148
1149 /*
1150 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1151 * supported/enabled, use 50 MHz DPLL clock otherwise...
1152 */
1153 if (info->max_mode == 0x04) {
1154 dpll_clk = 66;
1155 clock = ATA_CLOCK_66MHZ;
1156 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1157 dpll_clk = 50;
1158 clock = ATA_CLOCK_50MHZ;
1159 }
1160
1161 if (info->settings[clock] == NULL) {
1162 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1163 kfree(info);
1164 return -EIO;
1165 }
1166
1167 /* Select the DPLL clock. */
1168 pci_write_config_byte(dev, 0x5b, 0x21);
1169
1170 /*
1171 * Adjust the DPLL based upon PCI clock, enable it,
1172 * and wait for stabilization...
1173 */
1174 f_low = (pci_clk * 48) / dpll_clk;
1175
1176 for (adjust = 0; adjust < 8; adjust++) {
1177 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1178 break;
1179
1180 /*
1181 * See if it'll settle at a fractionally different clock
1182 */
1183 if (adjust & 1)
1184 f_low -= adjust >> 1;
1185 else
1186 f_low += adjust >> 1;
1187 }
1188 if (adjust == 8) {
1189 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1190 kfree(info);
1191 return -EIO;
1192 }
1193
1194 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1195 } else {
1196 /* Mark the fact that we're not using the DPLL. */
1197 dpll_clk = 0;
1198
1199 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1200 }
1201
1202 /*
1203 * Advance the table pointer to a slot which points to the list
1204 * of the register values settings matching the clock being used.
1205 */
1206 info->settings += clock;
1207
1208 /* Store the clock frequencies. */
1209 info->dpll_clk = dpll_clk;
1210 info->pci_clk = pci_clk;
1211
1212 /* Point to this chip's own instance of the hpt_info structure. */
1213 pci_set_drvdata(dev, info);
1214
1215 if (info->chip_type >= HPT370) {
1216 u8 mcr1, mcr4;
1217
1218 /*
1219 * Reset the state engines.
1220 * NOTE: Avoid accidentally enabling the disabled channels.
1221 */
1222 pci_read_config_byte (dev, 0x50, &mcr1);
1223 pci_read_config_byte (dev, 0x54, &mcr4);
1224 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1225 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1226 udelay(100);
1227 }
1228
1229 /*
1230 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1231 * the MISC. register to stretch the UltraDMA Tss timing.
1232 * NOTE: This register is only writeable via I/O space.
1233 */
1234 if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1235
1236 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1237
1238 return dev->irq;
1239 }
1240
1241 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1242 {
1243 struct pci_dev *dev = hwif->pci_dev;
1244 struct hpt_info *info = pci_get_drvdata(dev);
1245 int serialize = HPT_SERIALIZE_IO;
1246 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
1247 u8 chip_type = info->chip_type;
1248 u8 new_mcr, old_mcr = 0;
1249
1250 /* Cache the channel's MISC. control registers' offset */
1251 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1252
1253 hwif->tuneproc = &hpt3xx_tune_drive;
1254 hwif->speedproc = &hpt3xx_tune_chipset;
1255 hwif->quirkproc = &hpt3xx_quirkproc;
1256 hwif->intrproc = &hpt3xx_intrproc;
1257 hwif->maskproc = &hpt3xx_maskproc;
1258 hwif->busproc = &hpt3xx_busproc;
1259 hwif->udma_filter = &hpt3xx_udma_filter;
1260
1261 /*
1262 * HPT3xxN chips have some complications:
1263 *
1264 * - on 33 MHz PCI we must clock switch
1265 * - on 66 MHz PCI we must NOT use the PCI clock
1266 */
1267 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1268 /*
1269 * Clock is shared between the channels,
1270 * so we'll have to serialize them... :-(
1271 */
1272 serialize = 1;
1273 hwif->rw_disk = &hpt3xxn_rw_disk;
1274 }
1275
1276 /* Serialize access to this device if needed */
1277 if (serialize && hwif->mate)
1278 hwif->serialized = hwif->mate->serialized = 1;
1279
1280 /*
1281 * Disable the "fast interrupt" prediction. Don't hold off
1282 * on interrupts. (== 0x01 despite what the docs say)
1283 */
1284 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1285
1286 if (info->chip_type >= HPT374)
1287 new_mcr = old_mcr & ~0x07;
1288 else if (info->chip_type >= HPT370) {
1289 new_mcr = old_mcr;
1290 new_mcr &= ~0x02;
1291
1292 #ifdef HPT_DELAY_INTERRUPT
1293 new_mcr &= ~0x01;
1294 #else
1295 new_mcr |= 0x01;
1296 #endif
1297 } else /* HPT366 and HPT368 */
1298 new_mcr = old_mcr & ~0x80;
1299
1300 if (new_mcr != old_mcr)
1301 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1302
1303 if (!hwif->dma_base) {
1304 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1305 return;
1306 }
1307
1308 hwif->ultra_mask = 0x7f;
1309 hwif->mwdma_mask = 0x07;
1310
1311 /*
1312 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1313 * address lines to access an external EEPROM. To read valid
1314 * cable detect state the pins must be enabled as inputs.
1315 */
1316 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1317 /*
1318 * HPT374 PCI function 1
1319 * - set bit 15 of reg 0x52 to enable TCBLID as input
1320 * - set bit 15 of reg 0x56 to enable FCBLID as input
1321 */
1322 u8 mcr_addr = hwif->select_data + 2;
1323 u16 mcr;
1324
1325 pci_read_config_word (dev, mcr_addr, &mcr);
1326 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1327 /* now read cable id register */
1328 pci_read_config_byte (dev, 0x5a, &scr1);
1329 pci_write_config_word(dev, mcr_addr, mcr);
1330 } else if (chip_type >= HPT370) {
1331 /*
1332 * HPT370/372 and 374 pcifn 0
1333 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1334 */
1335 u8 scr2 = 0;
1336
1337 pci_read_config_byte (dev, 0x5b, &scr2);
1338 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1339 /* now read cable id register */
1340 pci_read_config_byte (dev, 0x5a, &scr1);
1341 pci_write_config_byte(dev, 0x5b, scr2);
1342 } else
1343 pci_read_config_byte (dev, 0x5a, &scr1);
1344
1345 if (!hwif->udma_four)
1346 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1347
1348 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1349
1350 if (chip_type >= HPT374) {
1351 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1352 hwif->ide_dma_end = &hpt374_ide_dma_end;
1353 } else if (chip_type >= HPT370) {
1354 hwif->dma_start = &hpt370_ide_dma_start;
1355 hwif->ide_dma_end = &hpt370_ide_dma_end;
1356 hwif->dma_timeout = &hpt370_dma_timeout;
1357 } else
1358 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
1359
1360 if (!noautodma)
1361 hwif->autodma = 1;
1362 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1363 }
1364
1365 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1366 {
1367 struct pci_dev *dev = hwif->pci_dev;
1368 u8 masterdma = 0, slavedma = 0;
1369 u8 dma_new = 0, dma_old = 0;
1370 unsigned long flags;
1371
1372 dma_old = hwif->INB(dmabase + 2);
1373
1374 local_irq_save(flags);
1375
1376 dma_new = dma_old;
1377 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1378 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1379
1380 if (masterdma & 0x30) dma_new |= 0x20;
1381 if ( slavedma & 0x30) dma_new |= 0x40;
1382 if (dma_new != dma_old)
1383 hwif->OUTB(dma_new, dmabase + 2);
1384
1385 local_irq_restore(flags);
1386
1387 ide_setup_dma(hwif, dmabase, 8);
1388 }
1389
1390 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1391 {
1392 struct pci_dev *dev2;
1393
1394 if (PCI_FUNC(dev->devfn) & 1)
1395 return -ENODEV;
1396
1397 pci_set_drvdata(dev, &hpt374);
1398
1399 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1400 int ret;
1401
1402 pci_set_drvdata(dev2, &hpt374);
1403
1404 if (dev2->irq != dev->irq) {
1405 /* FIXME: we need a core pci_set_interrupt() */
1406 dev2->irq = dev->irq;
1407 printk(KERN_WARNING "%s: PCI config space interrupt "
1408 "fixed.\n", d->name);
1409 }
1410 ret = ide_setup_pci_devices(dev, dev2, d);
1411 if (ret < 0)
1412 pci_dev_put(dev2);
1413 return ret;
1414 }
1415 return ide_setup_pci_device(dev, d);
1416 }
1417
1418 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1419 {
1420 pci_set_drvdata(dev, &hpt372n);
1421
1422 return ide_setup_pci_device(dev, d);
1423 }
1424
1425 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1426 {
1427 struct hpt_info *info;
1428 u8 rev = 0, mcr1 = 0;
1429
1430 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1431
1432 if (rev > 1) {
1433 d->name = "HPT371N";
1434
1435 info = &hpt371n;
1436 } else
1437 info = &hpt371;
1438
1439 /*
1440 * HPT371 chips physically have only one channel, the secondary one,
1441 * but the primary channel registers do exist! Go figure...
1442 * So, we manually disable the non-existing channel here
1443 * (if the BIOS hasn't done this already).
1444 */
1445 pci_read_config_byte(dev, 0x50, &mcr1);
1446 if (mcr1 & 0x04)
1447 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1448
1449 pci_set_drvdata(dev, info);
1450
1451 return ide_setup_pci_device(dev, d);
1452 }
1453
1454 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1455 {
1456 struct hpt_info *info;
1457 u8 rev = 0;
1458
1459 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1460
1461 if (rev > 1) {
1462 d->name = "HPT372N";
1463
1464 info = &hpt372n;
1465 } else
1466 info = &hpt372a;
1467 pci_set_drvdata(dev, info);
1468
1469 return ide_setup_pci_device(dev, d);
1470 }
1471
1472 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1473 {
1474 struct hpt_info *info;
1475 u8 rev = 0;
1476
1477 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1478
1479 if (rev > 1) {
1480 d->name = "HPT302N";
1481
1482 info = &hpt302n;
1483 } else
1484 info = &hpt302;
1485 pci_set_drvdata(dev, info);
1486
1487 return ide_setup_pci_device(dev, d);
1488 }
1489
1490 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1491 {
1492 struct pci_dev *dev2;
1493 u8 rev = 0;
1494 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1495 "HPT370", "HPT370A", "HPT372",
1496 "HPT372N" };
1497 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1498 &hpt370, &hpt370a, &hpt372,
1499 &hpt372n };
1500
1501 if (PCI_FUNC(dev->devfn) & 1)
1502 return -ENODEV;
1503
1504 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1505
1506 if (rev > 6)
1507 rev = 6;
1508
1509 d->name = chipset_names[rev];
1510
1511 pci_set_drvdata(dev, info[rev]);
1512
1513 if (rev > 2)
1514 goto init_single;
1515
1516 /*
1517 * HPT36x chips have one channel per function and have
1518 * both channel enable bits located differently and visible
1519 * to both functions -- really stupid design decision... :-(
1520 * Bit 4 is for the primary channel, bit 5 for the secondary.
1521 */
1522 d->channels = 1;
1523 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1524
1525 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1526 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1527 int ret;
1528
1529 pci_set_drvdata(dev2, info[rev]);
1530
1531 /*
1532 * Now we'll have to force both channels enabled if
1533 * at least one of them has been enabled by BIOS...
1534 */
1535 pci_read_config_byte(dev, 0x50, &mcr1);
1536 if (mcr1 & 0x30)
1537 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1538
1539 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1540 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1541 if (pin1 != pin2 && dev->irq == dev2->irq) {
1542 d->bootable = ON_BOARD;
1543 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1544 d->name, pin1, pin2);
1545 }
1546 ret = ide_setup_pci_devices(dev, dev2, d);
1547 if (ret < 0)
1548 pci_dev_put(dev2);
1549 return ret;
1550 }
1551 init_single:
1552 return ide_setup_pci_device(dev, d);
1553 }
1554
1555 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1556 { /* 0 */
1557 .name = "HPT366",
1558 .init_setup = init_setup_hpt366,
1559 .init_chipset = init_chipset_hpt366,
1560 .init_hwif = init_hwif_hpt366,
1561 .init_dma = init_dma_hpt366,
1562 .channels = 2,
1563 .autodma = AUTODMA,
1564 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1565 .bootable = OFF_BOARD,
1566 .extra = 240
1567 },{ /* 1 */
1568 .name = "HPT372A",
1569 .init_setup = init_setup_hpt372a,
1570 .init_chipset = init_chipset_hpt366,
1571 .init_hwif = init_hwif_hpt366,
1572 .init_dma = init_dma_hpt366,
1573 .channels = 2,
1574 .autodma = AUTODMA,
1575 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1576 .bootable = OFF_BOARD,
1577 .extra = 240
1578 },{ /* 2 */
1579 .name = "HPT302",
1580 .init_setup = init_setup_hpt302,
1581 .init_chipset = init_chipset_hpt366,
1582 .init_hwif = init_hwif_hpt366,
1583 .init_dma = init_dma_hpt366,
1584 .channels = 2,
1585 .autodma = AUTODMA,
1586 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1587 .bootable = OFF_BOARD,
1588 .extra = 240
1589 },{ /* 3 */
1590 .name = "HPT371",
1591 .init_setup = init_setup_hpt371,
1592 .init_chipset = init_chipset_hpt366,
1593 .init_hwif = init_hwif_hpt366,
1594 .init_dma = init_dma_hpt366,
1595 .channels = 2,
1596 .autodma = AUTODMA,
1597 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1598 .bootable = OFF_BOARD,
1599 .extra = 240
1600 },{ /* 4 */
1601 .name = "HPT374",
1602 .init_setup = init_setup_hpt374,
1603 .init_chipset = init_chipset_hpt366,
1604 .init_hwif = init_hwif_hpt366,
1605 .init_dma = init_dma_hpt366,
1606 .channels = 2, /* 4 */
1607 .autodma = AUTODMA,
1608 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1609 .bootable = OFF_BOARD,
1610 .extra = 240
1611 },{ /* 5 */
1612 .name = "HPT372N",
1613 .init_setup = init_setup_hpt372n,
1614 .init_chipset = init_chipset_hpt366,
1615 .init_hwif = init_hwif_hpt366,
1616 .init_dma = init_dma_hpt366,
1617 .channels = 2, /* 4 */
1618 .autodma = AUTODMA,
1619 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1620 .bootable = OFF_BOARD,
1621 .extra = 240
1622 }
1623 };
1624
1625 /**
1626 * hpt366_init_one - called when an HPT366 is found
1627 * @dev: the hpt366 device
1628 * @id: the matching pci id
1629 *
1630 * Called when the PCI registration layer (or the IDE initialization)
1631 * finds a device matching our IDE device tables.
1632 *
1633 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1634 * structure depending on the chip's revision, we'd better pass a local
1635 * copy down the call chain...
1636 */
1637 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1638 {
1639 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1640
1641 return d.init_setup(dev, &d);
1642 }
1643
1644 static struct pci_device_id hpt366_pci_tbl[] = {
1645 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1646 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1647 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1648 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1649 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1650 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1651 { 0, },
1652 };
1653 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1654
1655 static struct pci_driver driver = {
1656 .name = "HPT366_IDE",
1657 .id_table = hpt366_pci_tbl,
1658 .probe = hpt366_init_one,
1659 };
1660
1661 static int __init hpt366_ide_init(void)
1662 {
1663 return ide_pci_register_driver(&driver);
1664 }
1665
1666 module_init(hpt366_ide_init);
1667
1668 MODULE_AUTHOR("Andre Hedrick");
1669 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1670 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)