2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
5 * CYPRESS CY82C693 chipset IDE controller
7 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
8 * Writing the driver was quite simple, since most of the job is
9 * done by the generic pci-ide support.
10 * The hard part was finding the CY82C693's datasheet on Cypress's
11 * web page :-(. But Altavista solved this problem :-).
15 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
16 * a large and fast disk - the results look great, so I'd say the
17 * driver is working fine :-)
18 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
19 * - this is my first linux driver, so there's probably a lot of room
20 * for optimizations and bug fixing, so feel free to do it.
21 * - use idebus=xx parameter to set PCI bus speed - needed to calc
22 * timings for PIO modes (default will be 40)
23 * - if using PIO mode it's a good idea to set the PIO mode and
24 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
25 * - I had some problems with my IBM DHEA with PIO modes < 2
26 * (lost interrupts) ?????
27 * - first tests with DMA look okay, they seem to work, but there is a
28 * problem with sound - the BusMaster IDE TimeOut should fixed this
31 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
32 * ASK@1999-01-23: v0.33 made a few minor code clean ups
33 * removed DMA clock speed setting by default
35 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
36 * added support to set DMA Controller Clock Speed
37 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
39 * ASK@1998-10-29: v0.3 added support to set DMA modes
40 * ASK@1998-10-28: v0.2 added support to set PIO modes
41 * ASK@1998-10-27: v0.1 first version - chipset detection
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/delay.h>
49 #include <linux/ide.h>
50 #include <linux/init.h>
54 /* the current version */
55 #define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
58 * The following are used to debug the driver.
60 #define CY82C693_DEBUG_LOGS 0
61 #define CY82C693_DEBUG_INFO 0
63 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
64 #undef CY82C693_SETDMA_CLOCK
67 * NOTE: the value for busmaster timeout is tricky and I got it by
68 * trial and error! By using a to low value will cause DMA timeouts
69 * and drop IDE performance, and by using a to high value will cause
70 * audio playback to scatter.
71 * If you know a better value or how to calc it, please let me know.
74 /* twice the value written in cy82c693ub datasheet */
75 #define BUSMASTER_TIMEOUT 0x50
77 * the value above was tested on my machine and it seems to work okay
80 /* here are the offset definitions for the registers */
81 #define CY82_IDE_CMDREG 0x04
82 #define CY82_IDE_ADDRSETUP 0x48
83 #define CY82_IDE_MASTER_IOR 0x4C
84 #define CY82_IDE_MASTER_IOW 0x4D
85 #define CY82_IDE_SLAVE_IOR 0x4E
86 #define CY82_IDE_SLAVE_IOW 0x4F
87 #define CY82_IDE_MASTER_8BIT 0x50
88 #define CY82_IDE_SLAVE_8BIT 0x51
90 #define CY82_INDEX_PORT 0x22
91 #define CY82_DATA_PORT 0x23
93 #define CY82_INDEX_CTRLREG1 0x01
94 #define CY82_INDEX_CHANNEL0 0x30
95 #define CY82_INDEX_CHANNEL1 0x31
96 #define CY82_INDEX_TIMEOUT 0x32
98 /* the min and max PCI bus speed in MHz - from datasheet */
99 #define CY82C963_MIN_BUS_SPEED 25
100 #define CY82C963_MAX_BUS_SPEED 33
102 /* the struct for the PIO mode timings */
103 typedef struct pio_clocks_s
{
104 u8 address_time
; /* Address setup (clocks) */
105 u8 time_16r
; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
106 u8 time_16w
; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
107 u8 time_8
; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
111 * calc clocks using bus_speed
112 * returns (rounded up) time in bus clocks for time in ns
114 static int calc_clk (int time
, int bus_speed
)
118 clocks
= (time
*bus_speed
+999)/1000 -1;
130 * compute the values for the clock registers for PIO
131 * mode and pci_clk [MHz] speed
133 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
134 * for mode 3 and 4 drives 8 and 16-bit timings are the same
137 static void compute_clocks (u8 pio
, pio_clocks_t
*p_pclk
)
140 int bus_speed
= system_bus_clock(); /* get speed of PCI bus */
142 /* we don't check against CY82C693's min and max speed,
143 * so you can play with the idebus=xx parameter
146 /* let's calc the address setup time clocks */
147 p_pclk
->address_time
= (u8
)calc_clk(ide_pio_timings
[pio
].setup_time
, bus_speed
);
149 /* let's calc the active and recovery time clocks */
150 clk1
= calc_clk(ide_pio_timings
[pio
].active_time
, bus_speed
);
152 /* calc recovery timing */
153 clk2
= ide_pio_timings
[pio
].cycle_time
-
154 ide_pio_timings
[pio
].active_time
-
155 ide_pio_timings
[pio
].setup_time
;
157 clk2
= calc_clk(clk2
, bus_speed
);
159 clk1
= (clk1
<<4)|clk2
; /* combine active and recovery clocks */
161 /* note: we use the same values for 16bit IOR and IOW
162 * those are all the same, since I don't have other
163 * timings than those from ide-lib.c
166 p_pclk
->time_16r
= (u8
)clk1
;
167 p_pclk
->time_16w
= (u8
)clk1
;
169 /* what are good values for 8bit ?? */
170 p_pclk
->time_8
= (u8
)clk1
;
174 * set DMA mode a specific channel for CY82C693
177 static void cy82c693_set_dma_mode(ide_drive_t
*drive
, const u8 mode
)
179 ide_hwif_t
*hwif
= drive
->hwif
;
180 u8 single
= (mode
& 0x10) >> 4, index
= 0, data
= 0;
182 index
= hwif
->channel
? CY82_INDEX_CHANNEL1
: CY82_INDEX_CHANNEL0
;
184 #if CY82C693_DEBUG_LOGS
185 /* for debug let's show the previous values */
187 outb(index
, CY82_INDEX_PORT
);
188 data
= inb(CY82_DATA_PORT
);
190 printk (KERN_INFO
"%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
191 drive
->name
, HWIF(drive
)->channel
, drive
->select
.b
.unit
,
192 (data
&0x3), ((data
>>2)&1));
193 #endif /* CY82C693_DEBUG_LOGS */
195 data
= (mode
& 3) | (single
<< 2);
197 outb(index
, CY82_INDEX_PORT
);
198 outb(data
, CY82_DATA_PORT
);
200 #if CY82C693_DEBUG_INFO
201 printk(KERN_INFO
"%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
202 drive
->name
, HWIF(drive
)->channel
, drive
->select
.b
.unit
,
204 #endif /* CY82C693_DEBUG_INFO */
207 * note: below we set the value for Bus Master IDE TimeOut Register
208 * I'm not absolutly sure what this does, but it solved my problem
209 * with IDE DMA and sound, so I now can play sound and work with
210 * my IDE driver at the same time :-)
212 * If you know the correct (best) value for this register please
216 data
= BUSMASTER_TIMEOUT
;
217 outb(CY82_INDEX_TIMEOUT
, CY82_INDEX_PORT
);
218 outb(data
, CY82_DATA_PORT
);
220 #if CY82C693_DEBUG_INFO
221 printk (KERN_INFO
"%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
223 #endif /* CY82C693_DEBUG_INFO */
226 static void cy82c693_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
228 ide_hwif_t
*hwif
= HWIF(drive
);
229 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
231 unsigned int addrCtrl
;
233 /* select primary or secondary channel */
234 if (hwif
->index
> 0) { /* drive is on the secondary channel */
235 dev
= pci_get_slot(dev
->bus
, dev
->devfn
+1);
237 printk(KERN_ERR
"%s: tune_drive: "
238 "Cannot find secondary interface!\n",
244 #if CY82C693_DEBUG_LOGS
245 /* for debug let's show the register values */
247 if (drive
->select
.b
.unit
== 0) {
249 * get master drive registers
250 * address setup control register
253 pci_read_config_dword(dev
, CY82_IDE_ADDRSETUP
, &addrCtrl
);
256 /* now let's get the remaining registers */
257 pci_read_config_byte(dev
, CY82_IDE_MASTER_IOR
, &pclk
.time_16r
);
258 pci_read_config_byte(dev
, CY82_IDE_MASTER_IOW
, &pclk
.time_16w
);
259 pci_read_config_byte(dev
, CY82_IDE_MASTER_8BIT
, &pclk
.time_8
);
262 * set slave drive registers
263 * address setup control register
266 pci_read_config_dword(dev
, CY82_IDE_ADDRSETUP
, &addrCtrl
);
271 /* now let's get the remaining registers */
272 pci_read_config_byte(dev
, CY82_IDE_SLAVE_IOR
, &pclk
.time_16r
);
273 pci_read_config_byte(dev
, CY82_IDE_SLAVE_IOW
, &pclk
.time_16w
);
274 pci_read_config_byte(dev
, CY82_IDE_SLAVE_8BIT
, &pclk
.time_8
);
277 printk(KERN_INFO
"%s (ch=%d, dev=%d): PIO timing is "
278 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
279 drive
->name
, hwif
->channel
, drive
->select
.b
.unit
,
280 addrCtrl
, pclk
.time_16r
, pclk
.time_16w
, pclk
.time_8
);
281 #endif /* CY82C693_DEBUG_LOGS */
283 /* let's calc the values for this PIO mode */
284 compute_clocks(pio
, &pclk
);
286 /* now let's write the clocks registers */
287 if (drive
->select
.b
.unit
== 0) {
290 * address setup control register
293 pci_read_config_dword(dev
, CY82_IDE_ADDRSETUP
, &addrCtrl
);
296 addrCtrl
|= (unsigned int)pclk
.address_time
;
297 pci_write_config_dword(dev
, CY82_IDE_ADDRSETUP
, addrCtrl
);
299 /* now let's set the remaining registers */
300 pci_write_config_byte(dev
, CY82_IDE_MASTER_IOR
, pclk
.time_16r
);
301 pci_write_config_byte(dev
, CY82_IDE_MASTER_IOW
, pclk
.time_16w
);
302 pci_write_config_byte(dev
, CY82_IDE_MASTER_8BIT
, pclk
.time_8
);
308 * address setup control register
311 pci_read_config_dword(dev
, CY82_IDE_ADDRSETUP
, &addrCtrl
);
314 addrCtrl
|= ((unsigned int)pclk
.address_time
<<4);
315 pci_write_config_dword(dev
, CY82_IDE_ADDRSETUP
, addrCtrl
);
317 /* now let's set the remaining registers */
318 pci_write_config_byte(dev
, CY82_IDE_SLAVE_IOR
, pclk
.time_16r
);
319 pci_write_config_byte(dev
, CY82_IDE_SLAVE_IOW
, pclk
.time_16w
);
320 pci_write_config_byte(dev
, CY82_IDE_SLAVE_8BIT
, pclk
.time_8
);
326 #if CY82C693_DEBUG_INFO
327 printk(KERN_INFO
"%s (ch=%d, dev=%d): set PIO timing to "
328 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
329 drive
->name
, hwif
->channel
, drive
->select
.b
.unit
,
330 addrCtrl
, pclk
.time_16r
, pclk
.time_16w
, pclk
.time_8
);
331 #endif /* CY82C693_DEBUG_INFO */
335 * this function is called during init and is used to setup the cy82c693 chip
337 static unsigned int __devinit
init_chipset_cy82c693(struct pci_dev
*dev
, const char *name
)
339 if (PCI_FUNC(dev
->devfn
) != 1)
342 #ifdef CY82C693_SETDMA_CLOCK
344 #endif /* CY82C693_SETDMA_CLOCK */
346 /* write info about this verion of the driver */
347 printk(KERN_INFO CY82_VERSION
"\n");
349 #ifdef CY82C693_SETDMA_CLOCK
350 /* okay let's set the DMA clock speed */
352 outb(CY82_INDEX_CTRLREG1
, CY82_INDEX_PORT
);
353 data
= inb(CY82_DATA_PORT
);
355 #if CY82C693_DEBUG_INFO
356 printk(KERN_INFO
"%s: Peripheral Configuration Register: 0x%X\n",
358 #endif /* CY82C693_DEBUG_INFO */
361 * for some reason sometimes the DMA controller
362 * speed is set to ATCLK/2 ???? - we fix this here
364 * note: i don't know what causes this strange behaviour,
365 * but even changing the dma speed doesn't solve it :-(
366 * the ide performance is still only half the normal speed
368 * if anybody knows what goes wrong with my machine, please
374 outb(CY82_INDEX_CTRLREG1
, CY82_INDEX_PORT
);
375 outb(data
, CY82_DATA_PORT
);
377 #if CY82C693_DEBUG_INFO
378 printk (KERN_INFO
"%s: New Peripheral Configuration Register: 0x%X\n",
380 #endif /* CY82C693_DEBUG_INFO */
382 #endif /* CY82C693_SETDMA_CLOCK */
387 * the init function - called for each ide channel once
389 static void __devinit
init_hwif_cy82c693(ide_hwif_t
*hwif
)
391 hwif
->set_pio_mode
= &cy82c693_set_pio_mode
;
392 hwif
->set_dma_mode
= &cy82c693_set_dma_mode
;
395 static void __devinit
init_iops_cy82c693(ide_hwif_t
*hwif
)
397 static ide_hwif_t
*primary
;
398 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
400 if (PCI_FUNC(dev
->devfn
) == 1)
403 hwif
->mate
= primary
;
408 static const struct ide_port_info cy82c693_chipset __devinitdata
= {
410 .init_chipset
= init_chipset_cy82c693
,
411 .init_iops
= init_iops_cy82c693
,
412 .init_hwif
= init_hwif_cy82c693
,
413 .chipset
= ide_cy82c693
,
414 .host_flags
= IDE_HFLAG_SINGLE
| IDE_HFLAG_CY82C693
|
416 .pio_mask
= ATA_PIO4
,
417 .swdma_mask
= ATA_SWDMA2
,
418 .mwdma_mask
= ATA_MWDMA2
,
421 static int __devinit
cy82c693_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
423 struct pci_dev
*dev2
;
426 /* CY82C693 is more than only a IDE controller.
427 Function 1 is primary IDE channel, function 2 - secondary. */
428 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
&&
429 PCI_FUNC(dev
->devfn
) == 1) {
430 dev2
= pci_get_slot(dev
->bus
, dev
->devfn
+ 1);
431 ret
= ide_setup_pci_devices(dev
, dev2
, &cy82c693_chipset
);
432 /* We leak pci refs here but thats ok - we can't be unloaded */
437 static const struct pci_device_id cy82c693_pci_tbl
[] = {
438 { PCI_VDEVICE(CONTAQ
, PCI_DEVICE_ID_CONTAQ_82C693
), 0 },
441 MODULE_DEVICE_TABLE(pci
, cy82c693_pci_tbl
);
443 static struct pci_driver driver
= {
444 .name
= "Cypress_IDE",
445 .id_table
= cy82c693_pci_tbl
,
446 .probe
= cy82c693_init_one
,
449 static int __init
cy82c693_ide_init(void)
451 return ide_pci_register_driver(&driver
);
454 module_init(cy82c693_ide_init
);
456 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
457 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
458 MODULE_LICENSE("GPL");