2 * linux/drivers/ide/pci/cs5530.c Version 0.76 Aug 3 2007
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * May be copied or modified under the terms of the GNU General Public License
10 * Development of this chipset driver was funded
11 * by the nice folks at National Semiconductor.
14 * CS5530 documentation available from National Semiconductor.
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/blkdev.h>
25 #include <linux/hdreg.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/ide.h>
34 * Here are the standard PIO mode 0-4 timings for each "format".
35 * Format-0 uses fast data reg timings, with slower command reg timings.
36 * Format-1 uses fast timings for all registers, but won't work with all drives.
38 static unsigned int cs5530_pio_timings
[2][5] = {
39 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
40 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
44 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
46 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
47 #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
50 * cs5530_set_pio_mode - set host controller for PIO mode
52 * @pio: PIO mode number
54 * Handles setting of PIO mode for the chipset.
56 * The init_hwif_cs5530() routine guarantees that all drives
57 * will have valid default PIO timings set up before we get here.
60 static void cs5530_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
62 unsigned long basereg
= CS5530_BASEREG(drive
->hwif
);
63 unsigned int format
= (inl(basereg
+ 4) >> 31) & 1;
65 outl(cs5530_pio_timings
[format
][pio
], basereg
+ ((drive
->dn
& 1)<<3));
69 * cs5530_udma_filter - UDMA filter
72 * cs5530_udma_filter() does UDMA mask filtering for the given drive
73 * taking into the consideration capabilities of the mate device.
75 * The CS5530 specifies that two drives sharing a cable cannot mix
76 * UDMA/MDMA. It has to be one or the other, for the pair, though
77 * different timings can still be chosen for each drive. We could
78 * set the appropriate timing bits on the fly, but that might be
79 * a bit confusing. So, for now we statically handle this requirement
80 * by looking at our mate drive to see what it is capable of, before
81 * choosing a mode for our own drive.
83 * Note: This relies on the fact we never fail from UDMA to MWDMA2
84 * but instead drop to PIO.
87 static u8
cs5530_udma_filter(ide_drive_t
*drive
)
89 ide_hwif_t
*hwif
= drive
->hwif
;
90 ide_drive_t
*mate
= &hwif
->drives
[(drive
->dn
& 1) ^ 1];
91 struct hd_driveid
*mateid
= mate
->id
;
92 u8 mask
= hwif
->ultra_mask
;
94 if (mate
->present
== 0)
97 if ((mateid
->capability
& 1) && __ide_dma_bad_drive(mate
) == 0) {
98 if ((mateid
->field_valid
& 4) && (mateid
->dma_ultra
& 7))
100 if ((mateid
->field_valid
& 2) && (mateid
->dma_mword
& 7))
107 static void cs5530_set_dma_mode(ide_drive_t
*drive
, const u8 mode
)
109 unsigned long basereg
;
110 unsigned int reg
, timings
= 0;
113 case XFER_UDMA_0
: timings
= 0x00921250; break;
114 case XFER_UDMA_1
: timings
= 0x00911140; break;
115 case XFER_UDMA_2
: timings
= 0x00911030; break;
116 case XFER_MW_DMA_0
: timings
= 0x00077771; break;
117 case XFER_MW_DMA_1
: timings
= 0x00012121; break;
118 case XFER_MW_DMA_2
: timings
= 0x00002020; break;
123 basereg
= CS5530_BASEREG(drive
->hwif
);
124 reg
= inl(basereg
+ 4); /* get drive0 config register */
125 timings
|= reg
& 0x80000000; /* preserve PIO format bit */
126 if ((drive
-> dn
& 1) == 0) { /* are we configuring drive0? */
127 outl(timings
, basereg
+ 4); /* write drive0 config register */
129 if (timings
& 0x00100000)
130 reg
|= 0x00100000; /* enable UDMA timings for both drives */
132 reg
&= ~0x00100000; /* disable UDMA timings for both drives */
133 outl(reg
, basereg
+ 4); /* write drive0 config register */
134 outl(timings
, basereg
+ 12); /* write drive1 config register */
139 * init_chipset_5530 - set up 5530 bridge
143 * Initialize the cs5530 bridge for reliable IDE DMA operation.
146 static unsigned int __devinit
init_chipset_cs5530 (struct pci_dev
*dev
, const char *name
)
148 struct pci_dev
*master_0
= NULL
, *cs5530_0
= NULL
;
151 if (pci_resource_start(dev
, 4) == 0)
155 while ((dev
= pci_get_device(PCI_VENDOR_ID_CYRIX
, PCI_ANY_ID
, dev
)) != NULL
) {
156 switch (dev
->device
) {
157 case PCI_DEVICE_ID_CYRIX_PCI_MASTER
:
158 master_0
= pci_dev_get(dev
);
160 case PCI_DEVICE_ID_CYRIX_5530_LEGACY
:
161 cs5530_0
= pci_dev_get(dev
);
166 printk(KERN_ERR
"%s: unable to locate PCI MASTER function\n", name
);
170 printk(KERN_ERR
"%s: unable to locate CS5530 LEGACY function\n", name
);
174 spin_lock_irqsave(&ide_lock
, flags
);
175 /* all CPUs (there should only be one CPU with this chipset) */
178 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
179 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
182 pci_set_master(cs5530_0
);
183 pci_try_set_mwi(cs5530_0
);
186 * Set PCI CacheLineSize to 16-bytes:
187 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
190 pci_write_config_byte(cs5530_0
, PCI_CACHE_LINE_SIZE
, 0x04);
193 * Disable trapping of UDMA register accesses (Win98 hack):
194 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
197 pci_write_config_word(cs5530_0
, 0xd0, 0x5006);
200 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
201 * The other settings are what is necessary to get the register
202 * into a sane state for IDE DMA operation.
205 pci_write_config_byte(master_0
, 0x40, 0x1e);
208 * Set max PCI burst size (16-bytes seems to work best):
209 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
210 * all others: clear bit-1 at 0x41, and do:
211 * 128bytes: OR 0x00 at 0x41
212 * 256bytes: OR 0x04 at 0x41
213 * 512bytes: OR 0x08 at 0x41
214 * 1024bytes: OR 0x0c at 0x41
217 pci_write_config_byte(master_0
, 0x41, 0x14);
220 * These settings are necessary to get the chip
221 * into a sane state for IDE DMA operation.
224 pci_write_config_byte(master_0
, 0x42, 0x00);
225 pci_write_config_byte(master_0
, 0x43, 0xc1);
227 spin_unlock_irqrestore(&ide_lock
, flags
);
230 pci_dev_put(master_0
);
231 pci_dev_put(cs5530_0
);
236 * init_hwif_cs5530 - initialise an IDE channel
237 * @hwif: IDE to initialize
239 * This gets invoked by the IDE driver once for each channel. It
240 * performs channel-specific pre-initialization before drive probing.
243 static void __devinit
init_hwif_cs5530 (ide_hwif_t
*hwif
)
245 unsigned long basereg
;
250 hwif
->serialized
= hwif
->mate
->serialized
= 1;
252 hwif
->set_pio_mode
= &cs5530_set_pio_mode
;
253 hwif
->set_dma_mode
= &cs5530_set_dma_mode
;
255 basereg
= CS5530_BASEREG(hwif
);
256 d0_timings
= inl(basereg
+ 0);
257 if (CS5530_BAD_PIO(d0_timings
))
258 outl(cs5530_pio_timings
[(d0_timings
>> 31) & 1][0], basereg
+ 0);
259 if (CS5530_BAD_PIO(inl(basereg
+ 8)))
260 outl(cs5530_pio_timings
[(d0_timings
>> 31) & 1][0], basereg
+ 8);
262 hwif
->drives
[0].autotune
= 1;
263 hwif
->drives
[1].autotune
= 1;
265 if (hwif
->dma_base
== 0)
269 hwif
->ultra_mask
= 0x07;
270 hwif
->mwdma_mask
= 0x07;
272 hwif
->udma_filter
= cs5530_udma_filter
;
276 hwif
->drives
[0].autodma
= hwif
->autodma
;
277 hwif
->drives
[1].autodma
= hwif
->autodma
;
280 static ide_pci_device_t cs5530_chipset __devinitdata
= {
282 .init_chipset
= init_chipset_cs5530
,
283 .init_hwif
= init_hwif_cs5530
,
285 .bootable
= ON_BOARD
,
286 .pio_mask
= ATA_PIO4
,
287 .host_flags
= IDE_HFLAG_POST_SET_MODE
,
290 static int __devinit
cs5530_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
292 return ide_setup_pci_device(dev
, &cs5530_chipset
);
295 static const struct pci_device_id cs5530_pci_tbl
[] = {
296 { PCI_VDEVICE(CYRIX
, PCI_DEVICE_ID_CYRIX_5530_IDE
), 0 },
299 MODULE_DEVICE_TABLE(pci
, cs5530_pci_tbl
);
301 static struct pci_driver driver
= {
302 .name
= "CS5530 IDE",
303 .id_table
= cs5530_pci_tbl
,
304 .probe
= cs5530_init_one
,
307 static int __init
cs5530_ide_init(void)
309 return ide_pci_register_driver(&driver
);
312 module_init(cs5530_ide_init
);
314 MODULE_AUTHOR("Mark Lord");
315 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
316 MODULE_LICENSE("GPL");