drivers/ide/pci/cmd64x.c

   1 /*
   2  * linux/drivers/ide/pci/cmd64x.c               Version 1.53    Dec 24, 2007
   3  *
   4  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
   5  *           Due to massive hardware bugs, UltraDMA is only supported
   6  *           on the 646U2 and not on the 646U.
   7  *
   8  * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
   9  * Copyright (C) 1998           David S. Miller (davem@redhat.com)
  10  *
  11  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
  12  * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/pci.h>
  18 #include <linux/delay.h>
  19 #include <linux/hdreg.h>
  20 #include <linux/ide.h>
  21 #include <linux/init.h>
  22
  23 #include <asm/io.h>
  24
  25 #define CMD_DEBUG 0
  26
  27 #if CMD_DEBUG
  28 #define cmdprintk(x...) printk(x)
  29 #else
  30 #define cmdprintk(x...)
  31 #endif
  32
  33 /*
  34  * CMD64x specific registers definition.
  35  */
  36 #define CFR             0x50
  37 #define   CFR_INTR_CH0          0x04
  38
  39 #define CMDTIM          0x52
  40 #define ARTTIM0         0x53
  41 #define DRWTIM0         0x54
  42 #define ARTTIM1         0x55
  43 #define DRWTIM1         0x56
  44 #define ARTTIM23        0x57
  45 #define   ARTTIM23_DIS_RA2      0x04
  46 #define   ARTTIM23_DIS_RA3      0x08
  47 #define   ARTTIM23_INTR_CH1     0x10
  48 #define DRWTIM2         0x58
  49 #define BRST            0x59
  50 #define DRWTIM3         0x5b
  51
  52 #define BMIDECR0        0x70
  53 #define MRDMODE         0x71
  54 #define   MRDMODE_INTR_CH0      0x04
  55 #define   MRDMODE_INTR_CH1      0x08
  56 #define UDIDETCR0       0x73
  57 #define DTPR0           0x74
  58 #define BMIDECR1        0x78
  59 #define BMIDECSR        0x79
  60 #define UDIDETCR1       0x7B
  61 #define DTPR1           0x7C
  62
  63 static u8 quantize_timing(int timing, int quant)
  64 {
  65         return (timing + quant - 1) / quant;
  66 }
  67
  68 /*
  69  * This routine calculates active/recovery counts and then writes them into
  70  * the chipset registers.
  71  */
  72 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
  73 {
  74         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  75         int clock_time          = 1000 / system_bus_clock();
  76         u8  cycle_count, active_count, recovery_count, drwtim;
  77         static const u8 recovery_values[] =
  78                 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
  79         static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
  80
  81         cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
  82                   cycle_time, active_time);
  83
  84         cycle_count     = quantize_timing( cycle_time, clock_time);
  85         active_count    = quantize_timing(active_time, clock_time);
  86         recovery_count  = cycle_count - active_count;
  87
  88         /*
  89          * In case we've got too long recovery phase, try to lengthen
  90          * the active phase
  91          */
  92         if (recovery_count > 16) {
  93                 active_count += recovery_count - 16;
  94                 recovery_count = 16;
  95         }
  96         if (active_count > 16)          /* shouldn't actually happen... */
  97                 active_count = 16;
  98
  99         cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
 100                   cycle_count, active_count, recovery_count);
 101
 102         /*
 103          * Convert values to internal chipset representation
 104          */
 105         recovery_count = recovery_values[recovery_count];
 106         active_count  &= 0x0f;
 107
 108         /* Program the active/recovery counts into the DRWTIM register */
 109         drwtim = (active_count << 4) | recovery_count;
 110         (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
 111         cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
 112 }
 113
 114 /*
 115  * This routine writes into the chipset registers
 116  * PIO setup/active/recovery timings.
 117  */
 118 static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
 119 {
 120         ide_hwif_t *hwif        = HWIF(drive);
 121         struct pci_dev *dev     = hwif->pci_dev;
 122         unsigned int cycle_time;
 123         u8 setup_count, arttim = 0;
 124
 125         static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
 126         static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
 127
 128         cycle_time = ide_pio_cycle_time(drive, pio);
 129
 130         program_cycle_times(drive, cycle_time,
 131                             ide_pio_timings[pio].active_time);
 132
 133         setup_count = quantize_timing(ide_pio_timings[pio].setup_time,
 134                                       1000 / system_bus_clock());
 135
 136         /*
 137          * The primary channel has individual address setup timing registers
 138          * for each drive and the hardware selects the slowest timing itself.
 139          * The secondary channel has one common register and we have to select
 140          * the slowest address setup timing ourselves.
 141          */
 142         if (hwif->channel) {
 143                 ide_drive_t *drives = hwif->drives;
 144
 145                 drive->drive_data = setup_count;
 146                 setup_count = max(drives[0].drive_data, drives[1].drive_data);
 147         }
 148
 149         if (setup_count > 5)            /* shouldn't actually happen... */
 150                 setup_count = 5;
 151         cmdprintk("Final address setup count: %d\n", setup_count);
 152
 153         /*
 154          * Program the address setup clocks into the ARTTIM registers.
 155          * Avoid clearing the secondary channel's interrupt bit.
 156          */
 157         (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
 158         if (hwif->channel)
 159                 arttim &= ~ARTTIM23_INTR_CH1;
 160         arttim &= ~0xc0;
 161         arttim |= setup_values[setup_count];
 162         (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
 163         cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
 164 }
 165
 166 /*
 167  * Attempts to set drive's PIO mode.
 168  * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 169  */
 170
 171 static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
 172 {
 173         /*
 174          * Filter out the prefetch control values
 175          * to prevent PIO5 from being programmed
 176          */
 177         if (pio == 8 || pio == 9)
 178                 return;
 179
 180         cmd64x_tune_pio(drive, pio);
 181 }
 182
 183 static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
 184 {
 185         ide_hwif_t *hwif        = HWIF(drive);
 186         struct pci_dev *dev     = hwif->pci_dev;
 187         u8 unit                 = drive->dn & 0x01;
 188         u8 regU = 0, pciU       = hwif->channel ? UDIDETCR1 : UDIDETCR0;
 189
 190         if (speed >= XFER_SW_DMA_0) {
 191                 (void) pci_read_config_byte(dev, pciU, &regU);
 192                 regU &= ~(unit ? 0xCA : 0x35);
 193         }
 194
 195         switch(speed) {
 196         case XFER_UDMA_5:
 197                 regU |= unit ? 0x0A : 0x05;
 198                 break;
 199         case XFER_UDMA_4:
 200                 regU |= unit ? 0x4A : 0x15;
 201                 break;
 202         case XFER_UDMA_3:
 203                 regU |= unit ? 0x8A : 0x25;
 204                 break;
 205         case XFER_UDMA_2:
 206                 regU |= unit ? 0x42 : 0x11;
 207                 break;
 208         case XFER_UDMA_1:
 209                 regU |= unit ? 0x82 : 0x21;
 210                 break;
 211         case XFER_UDMA_0:
 212                 regU |= unit ? 0xC2 : 0x31;
 213                 break;
 214         case XFER_MW_DMA_2:
 215                 program_cycle_times(drive, 120, 70);
 216                 break;
 217         case XFER_MW_DMA_1:
 218                 program_cycle_times(drive, 150, 80);
 219                 break;
 220         case XFER_MW_DMA_0:
 221                 program_cycle_times(drive, 480, 215);
 222                 break;
 223         }
 224
 225         if (speed >= XFER_SW_DMA_0)
 226                 (void) pci_write_config_byte(dev, pciU, regU);
 227 }
 228
 229 static int cmd648_ide_dma_end (ide_drive_t *drive)
 230 {
 231         ide_hwif_t *hwif        = HWIF(drive);
 232         unsigned long base      = hwif->dma_base - (hwif->channel * 8);
 233         int err                 = __ide_dma_end(drive);
 234         u8  irq_mask            = hwif->channel ? MRDMODE_INTR_CH1 :
 235                                                   MRDMODE_INTR_CH0;
 236         u8  mrdmode             = inb(base + 1);
 237
 238         /* clear the interrupt bit */
 239         outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
 240              base + 1);
 241
 242         return err;
 243 }
 244
 245 static int cmd64x_ide_dma_end (ide_drive_t *drive)
 246 {
 247         ide_hwif_t *hwif        = HWIF(drive);
 248         struct pci_dev *dev     = hwif->pci_dev;
 249         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 250         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 251                                                   CFR_INTR_CH0;
 252         u8  irq_stat            = 0;
 253         int err                 = __ide_dma_end(drive);
 254
 255         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 256         /* clear the interrupt bit */
 257         (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
 258
 259         return err;
 260 }
 261
 262 static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
 263 {
 264         ide_hwif_t *hwif        = HWIF(drive);
 265         unsigned long base      = hwif->dma_base - (hwif->channel * 8);
 266         u8 irq_mask             = hwif->channel ? MRDMODE_INTR_CH1 :
 267                                                   MRDMODE_INTR_CH0;
 268         u8 dma_stat             = inb(hwif->dma_status);
 269         u8 mrdmode              = inb(base + 1);
 270
 271 #ifdef DEBUG
 272         printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
 273                drive->name, dma_stat, mrdmode, irq_mask);
 274 #endif
 275         if (!(mrdmode & irq_mask))
 276                 return 0;
 277
 278         /* return 1 if INTR asserted */
 279         if (dma_stat & 4)
 280                 return 1;
 281
 282         return 0;
 283 }
 284
 285 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
 286 {
 287         ide_hwif_t *hwif        = HWIF(drive);
 288         struct pci_dev *dev     = hwif->pci_dev;
 289         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 290         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 291                                                   CFR_INTR_CH0;
 292         u8  dma_stat            = inb(hwif->dma_status);
 293         u8  irq_stat            = 0;
 294
 295         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 296
 297 #ifdef DEBUG
 298         printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
 299                drive->name, dma_stat, irq_stat, irq_mask);
 300 #endif
 301         if (!(irq_stat & irq_mask))
 302                 return 0;
 303
 304         /* return 1 if INTR asserted */
 305         if (dma_stat & 4)
 306                 return 1;
 307
 308         return 0;
 309 }
 310
 311 /*
 312  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 313  * event order for DMA transfers.
 314  */
 315
 316 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
 317 {
 318         ide_hwif_t *hwif = HWIF(drive);
 319         u8 dma_stat = 0, dma_cmd = 0;
 320
 321         drive->waiting_for_dma = 0;
 322         /* get DMA status */
 323         dma_stat = inb(hwif->dma_status);
 324         /* read DMA command state */
 325         dma_cmd = inb(hwif->dma_command);
 326         /* stop DMA */
 327         outb(dma_cmd & ~1, hwif->dma_command);
 328         /* clear the INTR & ERROR bits */
 329         outb(dma_stat | 6, hwif->dma_status);
 330         /* and free any DMA resources */
 331         ide_destroy_dmatable(drive);
 332         /* verify good DMA status */
 333         return (dma_stat & 7) != 4;
 334 }
 335
 336 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
 337 {
 338         u8 mrdmode = 0;
 339
 340         if (dev->device == PCI_DEVICE_ID_CMD_646) {
 341
 342                 switch (dev->revision) {
 343                 case 0x07:
 344                 case 0x05:
 345                         printk("%s: UltraDMA capable\n", name);
 346                         break;
 347                 case 0x03:
 348                 default:
 349                         printk("%s: MultiWord DMA force limited\n", name);
 350                         break;
 351                 case 0x01:
 352                         printk("%s: MultiWord DMA limited, "
 353                                "IRQ workaround enabled\n", name);
 354                         break;
 355                 }
 356         }
 357
 358         /* Set a good latency timer and cache line size value. */
 359         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 360         /* FIXME: pci_set_master() to ensure a good latency timer value */
 361
 362         /*
 363          * Enable interrupts, select MEMORY READ LINE for reads.
 364          *
 365          * NOTE: although not mentioned in the PCI0646U specs,
 366          * bits 0-1 are write only and won't be read back as
 367          * set or not -- PCI0646U2 specs clarify this point.
 368          */
 369         (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
 370         mrdmode &= ~0x30;
 371         (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
 372
 373         return 0;
 374 }
 375
 376 static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
 377 {
 378         struct pci_dev  *dev    = hwif->pci_dev;
 379         u8 bmidecsr = 0, mask   = hwif->channel ? 0x02 : 0x01;
 380
 381         switch (dev->device) {
 382         case PCI_DEVICE_ID_CMD_648:
 383         case PCI_DEVICE_ID_CMD_649:
 384                 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
 385                 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 386         default:
 387                 return ATA_CBL_PATA40;
 388         }
 389 }
 390
 391 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
 392 {
 393         struct pci_dev *dev     = hwif->pci_dev;
 394
 395         hwif->set_pio_mode = &cmd64x_set_pio_mode;
 396         hwif->set_dma_mode = &cmd64x_set_dma_mode;
 397
 398         if (!hwif->dma_base)
 399                 return;
 400
 401         /*
 402          * UltraDMA only supported on PCI646U and PCI646U2, which
 403          * correspond to revisions 0x03, 0x05 and 0x07 respectively.
 404          * Actually, although the CMD tech support people won't
 405          * tell me the details, the 0x03 revision cannot support
 406          * UDMA correctly without hardware modifications, and even
 407          * then it only works with Quantum disks due to some
 408          * hold time assumptions in the 646U part which are fixed
 409          * in the 646U2.
 410          *
 411          * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
 412          */
 413         if (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 5)
 414                 hwif->ultra_mask = 0x00;
 415
 416         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 417                 hwif->cbl = ata66_cmd64x(hwif);
 418
 419         switch (dev->device) {
 420         case PCI_DEVICE_ID_CMD_648:
 421         case PCI_DEVICE_ID_CMD_649:
 422         alt_irq_bits:
 423                 hwif->ide_dma_end       = &cmd648_ide_dma_end;
 424                 hwif->ide_dma_test_irq  = &cmd648_ide_dma_test_irq;
 425                 break;
 426         case PCI_DEVICE_ID_CMD_646:
 427                 if (dev->revision == 0x01) {
 428                         hwif->ide_dma_end = &cmd646_1_ide_dma_end;
 429                         break;
 430                 } else if (dev->revision >= 0x03)
 431                         goto alt_irq_bits;
 432                 /* fall thru */
 433         default:
 434                 hwif->ide_dma_end       = &cmd64x_ide_dma_end;
 435                 hwif->ide_dma_test_irq  = &cmd64x_ide_dma_test_irq;
 436                 break;
 437         }
 438 }
 439
 440 static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
 441         {       /* 0 */
 442                 .name           = "CMD643",
 443                 .init_chipset   = init_chipset_cmd64x,
 444                 .init_hwif      = init_hwif_cmd64x,
 445                 .enablebits     = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
 446                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 447                 .pio_mask       = ATA_PIO5,
 448                 .mwdma_mask     = ATA_MWDMA2,
 449                 .udma_mask      = 0x00, /* no udma */
 450         },{     /* 1 */
 451                 .name           = "CMD646",
 452                 .init_chipset   = init_chipset_cmd64x,
 453                 .init_hwif      = init_hwif_cmd64x,
 454                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 455                 .chipset        = ide_cmd646,
 456                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 457                 .pio_mask       = ATA_PIO5,
 458                 .mwdma_mask     = ATA_MWDMA2,
 459                 .udma_mask      = ATA_UDMA2,
 460         },{     /* 2 */
 461                 .name           = "CMD648",
 462                 .init_chipset   = init_chipset_cmd64x,
 463                 .init_hwif      = init_hwif_cmd64x,
 464                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 465                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 466                 .pio_mask       = ATA_PIO5,
 467                 .mwdma_mask     = ATA_MWDMA2,
 468                 .udma_mask      = ATA_UDMA4,
 469         },{     /* 3 */
 470                 .name           = "CMD649",
 471                 .init_chipset   = init_chipset_cmd64x,
 472                 .init_hwif      = init_hwif_cmd64x,
 473                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 474                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 475                 .pio_mask       = ATA_PIO5,
 476                 .mwdma_mask     = ATA_MWDMA2,
 477                 .udma_mask      = ATA_UDMA5,
 478         }
 479 };
 480
 481 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 482 {
 483         struct ide_port_info d;
 484         u8 idx = id->driver_data;
 485
 486         d = cmd64x_chipsets[idx];
 487
 488         /*
 489          * The original PCI0646 didn't have the primary channel enable bit,
 490          * it appeared starting with PCI0646U (i.e. revision ID 3).
 491          */
 492         if (idx == 1 && dev->revision < 3)
 493                 d.enablebits[0].reg = 0;
 494
 495         return ide_setup_pci_device(dev, &d);
 496 }
 497
 498 static const struct pci_device_id cmd64x_pci_tbl[] = {
 499         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
 500         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
 501         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
 502         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
 503         { 0, },
 504 };
 505 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
 506
 507 static struct pci_driver driver = {
 508         .name           = "CMD64x_IDE",
 509         .id_table       = cmd64x_pci_tbl,
 510         .probe          = cmd64x_init_one,
 511 };
 512
 513 static int __init cmd64x_ide_init(void)
 514 {
 515         return ide_pci_register_driver(&driver);
 516 }
 517
 518 module_init(cmd64x_ide_init);
 519
 520 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
 521 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
 522 MODULE_LICENSE("GPL");