drivers/ide/pci/cmd64x.c

   1 /*
   2  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
   3  *           Due to massive hardware bugs, UltraDMA is only supported
   4  *           on the 646U2 and not on the 646U.
   5  *
   6  * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
   7  * Copyright (C) 1998           David S. Miller (davem@redhat.com)
   8  *
   9  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
  10  * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/hdreg.h>
  18 #include <linux/ide.h>
  19 #include <linux/init.h>
  20
  21 #include <asm/io.h>
  22
  23 #define CMD_DEBUG 0
  24
  25 #if CMD_DEBUG
  26 #define cmdprintk(x...) printk(x)
  27 #else
  28 #define cmdprintk(x...)
  29 #endif
  30
  31 /*
  32  * CMD64x specific registers definition.
  33  */
  34 #define CFR             0x50
  35 #define   CFR_INTR_CH0          0x04
  36
  37 #define CMDTIM          0x52
  38 #define ARTTIM0         0x53
  39 #define DRWTIM0         0x54
  40 #define ARTTIM1         0x55
  41 #define DRWTIM1         0x56
  42 #define ARTTIM23        0x57
  43 #define   ARTTIM23_DIS_RA2      0x04
  44 #define   ARTTIM23_DIS_RA3      0x08
  45 #define   ARTTIM23_INTR_CH1     0x10
  46 #define DRWTIM2         0x58
  47 #define BRST            0x59
  48 #define DRWTIM3         0x5b
  49
  50 #define BMIDECR0        0x70
  51 #define MRDMODE         0x71
  52 #define   MRDMODE_INTR_CH0      0x04
  53 #define   MRDMODE_INTR_CH1      0x08
  54 #define UDIDETCR0       0x73
  55 #define DTPR0           0x74
  56 #define BMIDECR1        0x78
  57 #define BMIDECSR        0x79
  58 #define UDIDETCR1       0x7B
  59 #define DTPR1           0x7C
  60
  61 static u8 quantize_timing(int timing, int quant)
  62 {
  63         return (timing + quant - 1) / quant;
  64 }
  65
  66 /*
  67  * This routine calculates active/recovery counts and then writes them into
  68  * the chipset registers.
  69  */
  70 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
  71 {
  72         struct pci_dev *dev     = to_pci_dev(drive->hwif->dev);
  73         int clock_time          = 1000 / system_bus_clock();
  74         u8  cycle_count, active_count, recovery_count, drwtim;
  75         static const u8 recovery_values[] =
  76                 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
  77         static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
  78
  79         cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
  80                   cycle_time, active_time);
  81
  82         cycle_count     = quantize_timing( cycle_time, clock_time);
  83         active_count    = quantize_timing(active_time, clock_time);
  84         recovery_count  = cycle_count - active_count;
  85
  86         /*
  87          * In case we've got too long recovery phase, try to lengthen
  88          * the active phase
  89          */
  90         if (recovery_count > 16) {
  91                 active_count += recovery_count - 16;
  92                 recovery_count = 16;
  93         }
  94         if (active_count > 16)          /* shouldn't actually happen... */
  95                 active_count = 16;
  96
  97         cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
  98                   cycle_count, active_count, recovery_count);
  99
 100         /*
 101          * Convert values to internal chipset representation
 102          */
 103         recovery_count = recovery_values[recovery_count];
 104         active_count  &= 0x0f;
 105
 106         /* Program the active/recovery counts into the DRWTIM register */
 107         drwtim = (active_count << 4) | recovery_count;
 108         (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
 109         cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
 110 }
 111
 112 /*
 113  * This routine writes into the chipset registers
 114  * PIO setup/active/recovery timings.
 115  */
 116 static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
 117 {
 118         ide_hwif_t *hwif        = HWIF(drive);
 119         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 120         unsigned int cycle_time;
 121         u8 setup_count, arttim = 0;
 122
 123         static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
 124         static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
 125
 126         cycle_time = ide_pio_cycle_time(drive, pio);
 127
 128         program_cycle_times(drive, cycle_time,
 129                             ide_pio_timings[pio].active_time);
 130
 131         setup_count = quantize_timing(ide_pio_timings[pio].setup_time,
 132                                       1000 / system_bus_clock());
 133
 134         /*
 135          * The primary channel has individual address setup timing registers
 136          * for each drive and the hardware selects the slowest timing itself.
 137          * The secondary channel has one common register and we have to select
 138          * the slowest address setup timing ourselves.
 139          */
 140         if (hwif->channel) {
 141                 ide_drive_t *drives = hwif->drives;
 142
 143                 drive->drive_data = setup_count;
 144                 setup_count = max(drives[0].drive_data, drives[1].drive_data);
 145         }
 146
 147         if (setup_count > 5)            /* shouldn't actually happen... */
 148                 setup_count = 5;
 149         cmdprintk("Final address setup count: %d\n", setup_count);
 150
 151         /*
 152          * Program the address setup clocks into the ARTTIM registers.
 153          * Avoid clearing the secondary channel's interrupt bit.
 154          */
 155         (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
 156         if (hwif->channel)
 157                 arttim &= ~ARTTIM23_INTR_CH1;
 158         arttim &= ~0xc0;
 159         arttim |= setup_values[setup_count];
 160         (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
 161         cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
 162 }
 163
 164 /*
 165  * Attempts to set drive's PIO mode.
 166  * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 167  */
 168
 169 static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
 170 {
 171         /*
 172          * Filter out the prefetch control values
 173          * to prevent PIO5 from being programmed
 174          */
 175         if (pio == 8 || pio == 9)
 176                 return;
 177
 178         cmd64x_tune_pio(drive, pio);
 179 }
 180
 181 static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
 182 {
 183         ide_hwif_t *hwif        = HWIF(drive);
 184         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 185         u8 unit                 = drive->dn & 0x01;
 186         u8 regU = 0, pciU       = hwif->channel ? UDIDETCR1 : UDIDETCR0;
 187
 188         if (speed >= XFER_SW_DMA_0) {
 189                 (void) pci_read_config_byte(dev, pciU, &regU);
 190                 regU &= ~(unit ? 0xCA : 0x35);
 191         }
 192
 193         switch(speed) {
 194         case XFER_UDMA_5:
 195                 regU |= unit ? 0x0A : 0x05;
 196                 break;
 197         case XFER_UDMA_4:
 198                 regU |= unit ? 0x4A : 0x15;
 199                 break;
 200         case XFER_UDMA_3:
 201                 regU |= unit ? 0x8A : 0x25;
 202                 break;
 203         case XFER_UDMA_2:
 204                 regU |= unit ? 0x42 : 0x11;
 205                 break;
 206         case XFER_UDMA_1:
 207                 regU |= unit ? 0x82 : 0x21;
 208                 break;
 209         case XFER_UDMA_0:
 210                 regU |= unit ? 0xC2 : 0x31;
 211                 break;
 212         case XFER_MW_DMA_2:
 213                 program_cycle_times(drive, 120, 70);
 214                 break;
 215         case XFER_MW_DMA_1:
 216                 program_cycle_times(drive, 150, 80);
 217                 break;
 218         case XFER_MW_DMA_0:
 219                 program_cycle_times(drive, 480, 215);
 220                 break;
 221         }
 222
 223         if (speed >= XFER_SW_DMA_0)
 224                 (void) pci_write_config_byte(dev, pciU, regU);
 225 }
 226
 227 static int cmd648_ide_dma_end (ide_drive_t *drive)
 228 {
 229         ide_hwif_t *hwif        = HWIF(drive);
 230         unsigned long base      = hwif->dma_base - (hwif->channel * 8);
 231         int err                 = __ide_dma_end(drive);
 232         u8  irq_mask            = hwif->channel ? MRDMODE_INTR_CH1 :
 233                                                   MRDMODE_INTR_CH0;
 234         u8  mrdmode             = inb(base + 1);
 235
 236         /* clear the interrupt bit */
 237         outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
 238              base + 1);
 239
 240         return err;
 241 }
 242
 243 static int cmd64x_ide_dma_end (ide_drive_t *drive)
 244 {
 245         ide_hwif_t *hwif        = HWIF(drive);
 246         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 247         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 248         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 249                                                   CFR_INTR_CH0;
 250         u8  irq_stat            = 0;
 251         int err                 = __ide_dma_end(drive);
 252
 253         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 254         /* clear the interrupt bit */
 255         (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
 256
 257         return err;
 258 }
 259
 260 static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
 261 {
 262         ide_hwif_t *hwif        = HWIF(drive);
 263         unsigned long base      = hwif->dma_base - (hwif->channel * 8);
 264         u8 irq_mask             = hwif->channel ? MRDMODE_INTR_CH1 :
 265                                                   MRDMODE_INTR_CH0;
 266         u8 dma_stat             = inb(hwif->dma_status);
 267         u8 mrdmode              = inb(base + 1);
 268
 269 #ifdef DEBUG
 270         printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
 271                drive->name, dma_stat, mrdmode, irq_mask);
 272 #endif
 273         if (!(mrdmode & irq_mask))
 274                 return 0;
 275
 276         /* return 1 if INTR asserted */
 277         if (dma_stat & 4)
 278                 return 1;
 279
 280         return 0;
 281 }
 282
 283 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
 284 {
 285         ide_hwif_t *hwif        = HWIF(drive);
 286         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 287         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 288         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 289                                                   CFR_INTR_CH0;
 290         u8  dma_stat            = inb(hwif->dma_status);
 291         u8  irq_stat            = 0;
 292
 293         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 294
 295 #ifdef DEBUG
 296         printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
 297                drive->name, dma_stat, irq_stat, irq_mask);
 298 #endif
 299         if (!(irq_stat & irq_mask))
 300                 return 0;
 301
 302         /* return 1 if INTR asserted */
 303         if (dma_stat & 4)
 304                 return 1;
 305
 306         return 0;
 307 }
 308
 309 /*
 310  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 311  * event order for DMA transfers.
 312  */
 313
 314 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
 315 {
 316         ide_hwif_t *hwif = HWIF(drive);
 317         u8 dma_stat = 0, dma_cmd = 0;
 318
 319         drive->waiting_for_dma = 0;
 320         /* get DMA status */
 321         dma_stat = inb(hwif->dma_status);
 322         /* read DMA command state */
 323         dma_cmd = inb(hwif->dma_command);
 324         /* stop DMA */
 325         outb(dma_cmd & ~1, hwif->dma_command);
 326         /* clear the INTR & ERROR bits */
 327         outb(dma_stat | 6, hwif->dma_status);
 328         /* and free any DMA resources */
 329         ide_destroy_dmatable(drive);
 330         /* verify good DMA status */
 331         return (dma_stat & 7) != 4;
 332 }
 333
 334 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
 335 {
 336         u8 mrdmode = 0;
 337
 338         if (dev->device == PCI_DEVICE_ID_CMD_646) {
 339
 340                 switch (dev->revision) {
 341                 case 0x07:
 342                 case 0x05:
 343                         printk("%s: UltraDMA capable\n", name);
 344                         break;
 345                 case 0x03:
 346                 default:
 347                         printk("%s: MultiWord DMA force limited\n", name);
 348                         break;
 349                 case 0x01:
 350                         printk("%s: MultiWord DMA limited, "
 351                                "IRQ workaround enabled\n", name);
 352                         break;
 353                 }
 354         }
 355
 356         /* Set a good latency timer and cache line size value. */
 357         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 358         /* FIXME: pci_set_master() to ensure a good latency timer value */
 359
 360         /*
 361          * Enable interrupts, select MEMORY READ LINE for reads.
 362          *
 363          * NOTE: although not mentioned in the PCI0646U specs,
 364          * bits 0-1 are write only and won't be read back as
 365          * set or not -- PCI0646U2 specs clarify this point.
 366          */
 367         (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
 368         mrdmode &= ~0x30;
 369         (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
 370
 371         return 0;
 372 }
 373
 374 static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
 375 {
 376         struct pci_dev  *dev    = to_pci_dev(hwif->dev);
 377         u8 bmidecsr = 0, mask   = hwif->channel ? 0x02 : 0x01;
 378
 379         switch (dev->device) {
 380         case PCI_DEVICE_ID_CMD_648:
 381         case PCI_DEVICE_ID_CMD_649:
 382                 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
 383                 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 384         default:
 385                 return ATA_CBL_PATA40;
 386         }
 387 }
 388
 389 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
 390 {
 391         struct pci_dev *dev = to_pci_dev(hwif->dev);
 392
 393         hwif->set_pio_mode = &cmd64x_set_pio_mode;
 394         hwif->set_dma_mode = &cmd64x_set_dma_mode;
 395
 396         if (!hwif->dma_base)
 397                 return;
 398
 399         /*
 400          * UltraDMA only supported on PCI646U and PCI646U2, which
 401          * correspond to revisions 0x03, 0x05 and 0x07 respectively.
 402          * Actually, although the CMD tech support people won't
 403          * tell me the details, the 0x03 revision cannot support
 404          * UDMA correctly without hardware modifications, and even
 405          * then it only works with Quantum disks due to some
 406          * hold time assumptions in the 646U part which are fixed
 407          * in the 646U2.
 408          *
 409          * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
 410          */
 411         if (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 5)
 412                 hwif->ultra_mask = 0x00;
 413
 414         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 415                 hwif->cbl = ata66_cmd64x(hwif);
 416
 417         switch (dev->device) {
 418         case PCI_DEVICE_ID_CMD_648:
 419         case PCI_DEVICE_ID_CMD_649:
 420         alt_irq_bits:
 421                 hwif->ide_dma_end       = &cmd648_ide_dma_end;
 422                 hwif->ide_dma_test_irq  = &cmd648_ide_dma_test_irq;
 423                 break;
 424         case PCI_DEVICE_ID_CMD_646:
 425                 if (dev->revision == 0x01) {
 426                         hwif->ide_dma_end = &cmd646_1_ide_dma_end;
 427                         break;
 428                 } else if (dev->revision >= 0x03)
 429                         goto alt_irq_bits;
 430                 /* fall thru */
 431         default:
 432                 hwif->ide_dma_end       = &cmd64x_ide_dma_end;
 433                 hwif->ide_dma_test_irq  = &cmd64x_ide_dma_test_irq;
 434                 break;
 435         }
 436 }
 437
 438 static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
 439         {       /* 0 */
 440                 .name           = "CMD643",
 441                 .init_chipset   = init_chipset_cmd64x,
 442                 .init_hwif      = init_hwif_cmd64x,
 443                 .enablebits     = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
 444                 .host_flags     = IDE_HFLAG_CLEAR_SIMPLEX |
 445                                   IDE_HFLAG_ABUSE_PREFETCH |
 446                                   IDE_HFLAG_BOOTABLE,
 447                 .pio_mask       = ATA_PIO5,
 448                 .mwdma_mask     = ATA_MWDMA2,
 449                 .udma_mask      = 0x00, /* no udma */
 450         },{     /* 1 */
 451                 .name           = "CMD646",
 452                 .init_chipset   = init_chipset_cmd64x,
 453                 .init_hwif      = init_hwif_cmd64x,
 454                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 455                 .chipset        = ide_cmd646,
 456                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 457                 .pio_mask       = ATA_PIO5,
 458                 .mwdma_mask     = ATA_MWDMA2,
 459                 .udma_mask      = ATA_UDMA2,
 460         },{     /* 2 */
 461                 .name           = "CMD648",
 462                 .init_chipset   = init_chipset_cmd64x,
 463                 .init_hwif      = init_hwif_cmd64x,
 464                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 465                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 466                 .pio_mask       = ATA_PIO5,
 467                 .mwdma_mask     = ATA_MWDMA2,
 468                 .udma_mask      = ATA_UDMA4,
 469         },{     /* 3 */
 470                 .name           = "CMD649",
 471                 .init_chipset   = init_chipset_cmd64x,
 472                 .init_hwif      = init_hwif_cmd64x,
 473                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 474                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 475                 .pio_mask       = ATA_PIO5,
 476                 .mwdma_mask     = ATA_MWDMA2,
 477                 .udma_mask      = ATA_UDMA5,
 478         }
 479 };
 480
 481 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 482 {
 483         struct ide_port_info d;
 484         u8 idx = id->driver_data;
 485
 486         d = cmd64x_chipsets[idx];
 487
 488         /*
 489          * The original PCI0646 didn't have the primary channel enable bit,
 490          * it appeared starting with PCI0646U (i.e. revision ID 3).
 491          */
 492         if (idx == 1 && dev->revision < 3)
 493                 d.enablebits[0].reg = 0;
 494
 495         return ide_setup_pci_device(dev, &d);
 496 }
 497
 498 static const struct pci_device_id cmd64x_pci_tbl[] = {
 499         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
 500         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
 501         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
 502         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
 503         { 0, },
 504 };
 505 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
 506
 507 static struct pci_driver driver = {
 508         .name           = "CMD64x_IDE",
 509         .id_table       = cmd64x_pci_tbl,
 510         .probe          = cmd64x_init_one,
 511 };
 512
 513 static int __init cmd64x_ide_init(void)
 514 {
 515         return ide_pci_register_driver(&driver);
 516 }
 517
 518 module_init(cmd64x_ide_init);
 519
 520 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
 521 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
 522 MODULE_LICENSE("GPL");