2 * linux/drivers/ide/pci/alim15x3.c Version 0.29 Sep 16 2007
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
13 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
15 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
17 **********************************************************************
18 * 9/7/99 --Parts from the above author are included and need to be
19 * converted into standard interface, once I finish the thought.
22 * Don't use LBA48 mode on ALi <= 0xC4
23 * Don't poke 0x79 with a non ALi northbridge
24 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
25 * Allow UDMA6 on revisions > 0xC4
28 * Chipset documentation available under NDA only
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/delay.h>
37 #include <linux/hdreg.h>
38 #include <linux/ide.h>
39 #include <linux/init.h>
40 #include <linux/dmi.h>
44 #define DISPLAY_ALI_TIMINGS
47 * ALi devices are not plug in. Otherwise these static values would
48 * need to go. They ought to go away anyway
51 static u8 m5229_revision
;
52 static u8 chip_is_1543c_e
;
53 static struct pci_dev
*isa_dev
;
55 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
56 #include <linux/stat.h>
57 #include <linux/proc_fs.h>
59 static u8 ali_proc
= 0;
61 static struct pci_dev
*bmide_dev
;
63 static char *fifo
[4] = {
69 static char *udmaT
[8] = {
80 static char *channel_status
[8] = {
92 * ali_get_info - generate proc file for ALi IDE
93 * @buffer: buffer to fill
94 * @addr: address of user start in buffer
95 * @offset: offset into 'file'
96 * @count: buffer count
98 * Walks the Ali devices and outputs summary data on the tuning and
99 * anything else that will help with debugging
102 static int ali_get_info (char *buffer
, char **addr
, off_t offset
, int count
)
105 u8 reg53h
, reg5xh
, reg5yh
, reg5xh1
, reg5yh1
, c0
, c1
, rev
, tmp
;
106 char *q
, *p
= buffer
;
109 pci_read_config_byte(bmide_dev
, 0x08, &rev
);
110 if (rev
>= 0xc1) /* M1543C or newer */
115 /* first fetch bibma: */
117 bibma
= pci_resource_start(bmide_dev
, 4);
120 * at that point bibma+0x2 et bibma+0xa are byte
121 * registers to investigate:
123 c0
= inb(bibma
+ 0x02);
124 c1
= inb(bibma
+ 0x0a);
127 "\n Ali M15x3 Chipset.\n");
129 " ------------------\n");
130 pci_read_config_byte(bmide_dev
, 0x78, ®53h
);
131 p
+= sprintf(p
, "PCI Clock: %d.\n", reg53h
);
133 pci_read_config_byte(bmide_dev
, 0x53, ®53h
);
135 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
136 (reg53h
& 0x02) ? "Yes" : "No ",
137 (reg53h
& 0x01) ? "Yes" : "No " );
138 pci_read_config_byte(bmide_dev
, 0x74, ®53h
);
140 "FIFO Status: contains %d Words, runs%s%s\n\n",
142 (reg53h
& 0x40) ? " OVERWR" : "",
143 (reg53h
& 0x80) ? " OVERRD." : "." );
146 "-------------------primary channel"
147 "-------------------secondary channel"
150 pci_read_config_byte(bmide_dev
, 0x09, ®53h
);
154 (reg53h
& 0x20) ? "On " : "Off",
155 (reg53h
& 0x10) ? "On " : "Off" );
158 "both channels togth: %s"
160 (c0
&0x80) ? "No " : "Yes",
161 (c1
&0x80) ? "No " : "Yes" );
163 pci_read_config_byte(bmide_dev
, 0x76, ®53h
);
165 "Channel state: %s %s\n",
166 channel_status
[reg53h
& 0x07],
167 channel_status
[(reg53h
& 0x70) >> 4] );
169 pci_read_config_byte(bmide_dev
, 0x58, ®5xh
);
170 pci_read_config_byte(bmide_dev
, 0x5c, ®5yh
);
172 "Add. Setup Timing: %dT"
174 (reg5xh
& 0x07) ? (reg5xh
& 0x07) : 8,
175 (reg5yh
& 0x07) ? (reg5yh
& 0x07) : 8 );
177 pci_read_config_byte(bmide_dev
, 0x59, ®5xh
);
178 pci_read_config_byte(bmide_dev
, 0x5d, ®5yh
);
180 "Command Act. Count: %dT"
182 "Command Rec. Count: %dT"
184 (reg5xh
& 0x70) ? ((reg5xh
& 0x70) >> 4) : 8,
185 (reg5yh
& 0x70) ? ((reg5yh
& 0x70) >> 4) : 8,
186 (reg5xh
& 0x0f) ? (reg5xh
& 0x0f) : 16,
187 (reg5yh
& 0x0f) ? (reg5yh
& 0x0f) : 16 );
190 "----------------drive0-----------drive1"
191 "------------drive0-----------drive1------\n\n");
195 (c0
&0x20) ? "Yes" : "No ",
196 (c0
&0x40) ? "Yes" : "No ",
197 (c1
&0x20) ? "Yes" : "No ",
198 (c1
&0x40) ? "Yes" : "No " );
200 pci_read_config_byte(bmide_dev
, 0x54, ®5xh
);
201 pci_read_config_byte(bmide_dev
, 0x55, ®5yh
);
202 q
= "FIFO threshold: %2d Words %2d Words"
203 " %2d Words %2d Words\n";
206 (pci_read_config_byte(bmide_dev
, 0x4f, &tmp
), (tmp
&= 0x20))) {
207 p
+= sprintf(p
, q
, 8, 8, 8, 8);
210 (reg5xh
& 0x03) + 12,
211 ((reg5xh
& 0x30)>>4) + 12,
212 (reg5yh
& 0x03) + 12,
213 ((reg5yh
& 0x30)>>4) + 12 );
216 int t1
= (tmp
= (reg5xh
& 0x03)) ? (tmp
<< 3) : 4;
217 int t2
= (tmp
= ((reg5xh
& 0x30)>>4)) ? (tmp
<< 3) : 4;
218 int t3
= (tmp
= (reg5yh
& 0x03)) ? (tmp
<< 3) : 4;
219 int t4
= (tmp
= ((reg5yh
& 0x30)>>4)) ? (tmp
<< 3) : 4;
220 p
+= sprintf(p
, q
, t1
, t2
, t3
, t4
);
225 "FIFO threshold: %2d Words %2d Words"
226 " %2d Words %2d Words\n",
227 (reg5xh
& 0x03) + 12,
228 ((reg5xh
& 0x30)>>4) + 12,
229 (reg5yh
& 0x03) + 12,
230 ((reg5yh
& 0x30)>>4) + 12 );
234 "FIFO mode: %s %s %s %s\n",
235 fifo
[((reg5xh
& 0x0c) >> 2)],
236 fifo
[((reg5xh
& 0xc0) >> 6)],
237 fifo
[((reg5yh
& 0x0c) >> 2)],
238 fifo
[((reg5yh
& 0xc0) >> 6)] );
240 pci_read_config_byte(bmide_dev
, 0x5a, ®5xh
);
241 pci_read_config_byte(bmide_dev
, 0x5b, ®5xh1
);
242 pci_read_config_byte(bmide_dev
, 0x5e, ®5yh
);
243 pci_read_config_byte(bmide_dev
, 0x5f, ®5yh1
);
246 "------------------drive0-----------drive1"
247 "------------drive0-----------drive1------\n")*/
248 "Dt RW act. Cnt %2dT %2dT"
250 "Dt RW rec. Cnt %2dT %2dT"
252 (reg5xh
& 0x70) ? ((reg5xh
& 0x70) >> 4) : 8,
253 (reg5xh1
& 0x70) ? ((reg5xh1
& 0x70) >> 4) : 8,
254 (reg5yh
& 0x70) ? ((reg5yh
& 0x70) >> 4) : 8,
255 (reg5yh1
& 0x70) ? ((reg5yh1
& 0x70) >> 4) : 8,
256 (reg5xh
& 0x0f) ? (reg5xh
& 0x0f) : 16,
257 (reg5xh1
& 0x0f) ? (reg5xh1
& 0x0f) : 16,
258 (reg5yh
& 0x0f) ? (reg5yh
& 0x0f) : 16,
259 (reg5yh1
& 0x0f) ? (reg5yh1
& 0x0f) : 16 );
262 "-----------------------------------UDMA Timings"
263 "--------------------------------\n\n");
265 pci_read_config_byte(bmide_dev
, 0x56, ®5xh
);
266 pci_read_config_byte(bmide_dev
, 0x57, ®5yh
);
270 "UDMA timings: %s %s"
272 (reg5xh
& 0x08) ? "OK" : "No",
273 (reg5xh
& 0x80) ? "OK" : "No",
274 (reg5yh
& 0x08) ? "OK" : "No",
275 (reg5yh
& 0x80) ? "OK" : "No",
276 udmaT
[(reg5xh
& 0x07)],
277 udmaT
[(reg5xh
& 0x70) >> 4],
278 udmaT
[reg5yh
& 0x07],
279 udmaT
[(reg5yh
& 0x70) >> 4] );
281 return p
-buffer
; /* => must be less than 4k! */
283 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
286 * ali_set_pio_mode - set host controller for PIO mode
288 * @pio: PIO mode number
290 * Program the controller for the given PIO mode.
293 static void ali_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
295 ide_hwif_t
*hwif
= HWIF(drive
);
296 struct pci_dev
*dev
= hwif
->pci_dev
;
297 int s_time
, a_time
, c_time
;
298 u8 s_clc
, a_clc
, r_clc
;
300 int bus_speed
= system_bus_clock();
301 int port
= hwif
->channel
? 0x5c : 0x58;
302 int portFIFO
= hwif
->channel
? 0x55 : 0x54;
304 int unit
= drive
->select
.b
.unit
& 1;
306 s_time
= ide_pio_timings
[pio
].setup_time
;
307 a_time
= ide_pio_timings
[pio
].active_time
;
308 if ((s_clc
= (s_time
* bus_speed
+ 999) / 1000) >= 8)
310 if ((a_clc
= (a_time
* bus_speed
+ 999) / 1000) >= 8)
312 c_time
= ide_pio_timings
[pio
].cycle_time
;
315 if ((r_clc
= ((c_time
- s_time
- a_time
) * bus_speed
+ 999) / 1000) >= 16)
319 if (!(r_clc
= (c_time
* bus_speed
+ 999) / 1000 - a_clc
- s_clc
)) {
325 local_irq_save(flags
);
328 * PIO mode => ATA FIFO on, ATAPI FIFO off
330 pci_read_config_byte(dev
, portFIFO
, &cd_dma_fifo
);
331 if (drive
->media
==ide_disk
) {
333 pci_write_config_byte(dev
, portFIFO
, (cd_dma_fifo
& 0x0F) | 0x50);
335 pci_write_config_byte(dev
, portFIFO
, (cd_dma_fifo
& 0xF0) | 0x05);
339 pci_write_config_byte(dev
, portFIFO
, cd_dma_fifo
& 0x0F);
341 pci_write_config_byte(dev
, portFIFO
, cd_dma_fifo
& 0xF0);
345 pci_write_config_byte(dev
, port
, s_clc
);
346 pci_write_config_byte(dev
, port
+drive
->select
.b
.unit
+2, (a_clc
<< 4) | r_clc
);
347 local_irq_restore(flags
);
351 * { 70, 165, 365 }, PIO Mode 0
352 * { 50, 125, 208 }, PIO Mode 1
353 * { 30, 100, 110 }, PIO Mode 2
354 * { 30, 80, 70 }, PIO Mode 3 with IORDY
355 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
356 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
361 * ali_udma_filter - compute UDMA mask
364 * Return available UDMA modes.
366 * The actual rules for the ALi are:
367 * No UDMA on revisions <= 0x20
368 * Disk only for revisions < 0xC2
369 * Not WDC drives for revisions < 0xC2
371 * FIXME: WDC ifdef needs to die
374 static u8
ali_udma_filter(ide_drive_t
*drive
)
376 if (m5229_revision
> 0x20 && m5229_revision
< 0xC2) {
377 if (drive
->media
!= ide_disk
)
379 #ifndef CONFIG_WDC_ALI15X3
380 if (chip_is_1543c_e
&& strstr(drive
->id
->model
, "WDC "))
385 return drive
->hwif
->ultra_mask
;
389 * ali_set_dma_mode - set host controller for DMA mode
393 * Configure the hardware for the desired IDE transfer mode.
396 static void ali_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
398 ide_hwif_t
*hwif
= HWIF(drive
);
399 struct pci_dev
*dev
= hwif
->pci_dev
;
401 u8 unit
= (drive
->select
.b
.unit
& 0x01);
403 int m5229_udma
= (hwif
->channel
) ? 0x57 : 0x56;
405 if (speed
< XFER_PIO_0
)
408 if (speed
== XFER_UDMA_6
)
411 if (speed
< XFER_UDMA_0
) {
412 u8 ultra_enable
= (unit
) ? 0x7f : 0xf7;
414 * clear "ultra enable" bit
416 pci_read_config_byte(dev
, m5229_udma
, &tmpbyte
);
417 tmpbyte
&= ultra_enable
;
418 pci_write_config_byte(dev
, m5229_udma
, tmpbyte
);
421 * FIXME: Oh, my... DMA timings are never set.
424 pci_read_config_byte(dev
, m5229_udma
, &tmpbyte
);
425 tmpbyte
&= (0x0f << ((1-unit
) << 2));
427 * enable ultra dma and set timing
429 tmpbyte
|= ((0x08 | ((4-speed1
)&0x07)) << (unit
<< 2));
430 pci_write_config_byte(dev
, m5229_udma
, tmpbyte
);
431 if (speed
>= XFER_UDMA_3
) {
432 pci_read_config_byte(dev
, 0x4b, &tmpbyte
);
434 pci_write_config_byte(dev
, 0x4b, tmpbyte
);
440 * ali15x3_dma_setup - begin a DMA phase
441 * @drive: target device
443 * Returns 1 if the DMA cannot be performed, zero on success.
446 static int ali15x3_dma_setup(ide_drive_t
*drive
)
448 if (m5229_revision
< 0xC2 && drive
->media
!= ide_disk
) {
449 if (rq_data_dir(drive
->hwif
->hwgroup
->rq
))
450 return 1; /* try PIO instead of DMA */
452 return ide_dma_setup(drive
);
456 * init_chipset_ali15x3 - Initialise an ALi IDE controller
458 * @name: Name of the controller
460 * This function initializes the ALI IDE controller and where
461 * appropriate also sets up the 1533 southbridge.
464 static unsigned int __devinit
init_chipset_ali15x3 (struct pci_dev
*dev
, const char *name
)
468 struct pci_dev
*north
= pci_get_slot(dev
->bus
, PCI_DEVFN(0,0));
470 m5229_revision
= dev
->revision
;
472 isa_dev
= pci_get_device(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, NULL
);
474 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
478 ide_pci_create_host_proc("ali", ali_get_info
);
480 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
482 local_irq_save(flags
);
484 if (m5229_revision
< 0xC2) {
486 * revision 0x20 (1543-E, 1543-F)
487 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
488 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
490 pci_read_config_byte(dev
, 0x4b, &tmpbyte
);
494 pci_write_config_byte(dev
, 0x4b, tmpbyte
& 0x7F);
496 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
498 if (m5229_revision
>= 0x20 && isa_dev
) {
499 pci_read_config_byte(isa_dev
, 0x5e, &tmpbyte
);
500 chip_is_1543c_e
= ((tmpbyte
& 0x1e) == 0x12) ? 1: 0;
506 * 1543C-B?, 1535, 1535D, 1553
507 * Note 1: not all "motherboard" support this detection
508 * Note 2: if no udma 66 device, the detection may "error".
509 * but in this case, we will not set the device to
510 * ultra 66, the detection result is not important
514 * enable "Cable Detection", m5229, 0x4b, bit3
516 pci_read_config_byte(dev
, 0x4b, &tmpbyte
);
517 pci_write_config_byte(dev
, 0x4b, tmpbyte
| 0x08);
520 * We should only tune the 1533 enable if we are using an ALi
521 * North bridge. We might have no north found on some zany
522 * box without a device at 0:0.0. The ALi bridge will be at
523 * 0:0.0 so if we didn't find one we know what is cooking.
525 if (north
&& north
->vendor
!= PCI_VENDOR_ID_AL
)
528 if (m5229_revision
< 0xC5 && isa_dev
)
531 * set south-bridge's enable bit, m1533, 0x79
534 pci_read_config_byte(isa_dev
, 0x79, &tmpbyte
);
535 if (m5229_revision
== 0xC2) {
537 * 1543C-B0 (m1533, 0x79, bit 2)
539 pci_write_config_byte(isa_dev
, 0x79, tmpbyte
| 0x04);
540 } else if (m5229_revision
>= 0xC3) {
542 * 1553/1535 (m1533, 0x79, bit 1)
544 pci_write_config_byte(isa_dev
, 0x79, tmpbyte
| 0x02);
550 * CD_ROM DMA on (m5229, 0x53, bit0)
551 * Enable this bit even if we want to use PIO.
552 * PIO FIFO off (m5229, 0x53, bit1)
553 * The hardware will use 0x54h and 0x55h to control PIO FIFO.
554 * (Not on later devices it seems)
556 * 0x53 changes meaning on later revs - we must no touch
557 * bit 1 on them. Need to check if 0x20 is the right break.
559 if (m5229_revision
>= 0x20) {
560 pci_read_config_byte(dev
, 0x53, &tmpbyte
);
562 if (m5229_revision
<= 0x20)
563 tmpbyte
= (tmpbyte
& (~0x02)) | 0x01;
564 else if (m5229_revision
== 0xc7 || m5229_revision
== 0xc8)
569 pci_write_config_byte(dev
, 0x53, tmpbyte
);
572 pci_dev_put(isa_dev
);
573 local_irq_restore(flags
);
578 * Cable special cases
581 static const struct dmi_system_id cable_dmi_table
[] = {
583 .ident
= "HP Pavilion N5430",
585 DMI_MATCH(DMI_BOARD_VENDOR
, "Hewlett-Packard"),
586 DMI_MATCH(DMI_BOARD_VERSION
, "OmniBook N32N-736"),
590 .ident
= "Toshiba Satellite S1800-814",
592 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
593 DMI_MATCH(DMI_PRODUCT_NAME
, "S1800-814"),
599 static int ali_cable_override(struct pci_dev
*pdev
)
602 if (pdev
->subsystem_vendor
== 0x10CF &&
603 pdev
->subsystem_device
== 0x10AF)
606 /* Mitac 8317 (Winbook-A) and relatives */
607 if (pdev
->subsystem_vendor
== 0x1071 &&
608 pdev
->subsystem_device
== 0x8317)
612 if (dmi_check_system(cable_dmi_table
))
619 * ata66_ali15x3 - check for UDMA 66 support
620 * @hwif: IDE interface
622 * This checks if the controller and the cable are capable
623 * of UDMA66 transfers. It doesn't check the drives.
624 * But see note 2 below!
626 * FIXME: frobs bits that are not defined on newer ALi devicea
629 static u8 __devinit
ata66_ali15x3(ide_hwif_t
*hwif
)
631 struct pci_dev
*dev
= hwif
->pci_dev
;
633 u8 cbl
= ATA_CBL_PATA40
, tmpbyte
;
635 local_irq_save(flags
);
637 if (m5229_revision
>= 0xC2) {
639 * m5229 80-pin cable detection (from Host View)
641 * 0x4a bit0 is 0 => primary channel has 80-pin
642 * 0x4a bit1 is 0 => secondary channel has 80-pin
644 * Certain laptops use short but suitable cables
645 * and don't implement the detect logic.
647 if (ali_cable_override(dev
))
648 cbl
= ATA_CBL_PATA40_SHORT
;
650 pci_read_config_byte(dev
, 0x4a, &tmpbyte
);
651 if ((tmpbyte
& (1 << hwif
->channel
)) == 0)
652 cbl
= ATA_CBL_PATA80
;
656 local_irq_restore(flags
);
662 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
663 * @hwif: IDE interface
665 * Initialize the IDE structure side of the ALi 15x3 driver.
668 static void __devinit
init_hwif_common_ali15x3 (ide_hwif_t
*hwif
)
670 hwif
->set_pio_mode
= &ali_set_pio_mode
;
671 hwif
->set_dma_mode
= &ali_set_dma_mode
;
672 hwif
->udma_filter
= &ali_udma_filter
;
674 if (hwif
->dma_base
== 0)
677 hwif
->dma_setup
= &ali15x3_dma_setup
;
679 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
680 hwif
->cbl
= ata66_ali15x3(hwif
);
684 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
685 * @hwif: interface to configure
687 * Obtain the IRQ tables for an ALi based IDE solution on the PC
688 * class platforms. This part of the code isn't applicable to the
692 static void __devinit
init_hwif_ali15x3 (ide_hwif_t
*hwif
)
695 s8 irq_routing_table
[] = { -1, 9, 3, 10, 4, 5, 7, 6,
696 1, 11, 0, 12, 0, 14, 0, 15 };
699 if (hwif
->pci_dev
->device
== PCI_DEVICE_ID_AL_M5229
)
700 hwif
->irq
= hwif
->channel
? 15 : 14;
704 * read IDE interface control
706 pci_read_config_byte(isa_dev
, 0x58, &ideic
);
709 ideic
= ideic
& 0x03;
711 /* get IRQ for IDE Controller */
712 if ((hwif
->channel
&& ideic
== 0x03) ||
713 (!hwif
->channel
&& !ideic
)) {
715 * get SIRQ1 routing table
717 pci_read_config_byte(isa_dev
, 0x44, &inmir
);
718 inmir
= inmir
& 0x0f;
719 irq
= irq_routing_table
[inmir
];
720 } else if (hwif
->channel
&& !(ideic
& 0x01)) {
722 * get SIRQ2 routing table
724 pci_read_config_byte(isa_dev
, 0x75, &inmir
);
725 inmir
= inmir
& 0x0f;
726 irq
= irq_routing_table
[inmir
];
732 init_hwif_common_ali15x3(hwif
);
736 * init_dma_ali15x3 - set up DMA on ALi15x3
737 * @hwif: IDE interface
738 * @dmabase: DMA interface base PCI address
740 * Set up the DMA functionality on the ALi 15x3. For the ALi
741 * controllers this is generic so we can let the generic code do
745 static void __devinit
init_dma_ali15x3 (ide_hwif_t
*hwif
, unsigned long dmabase
)
747 if (m5229_revision
< 0x20)
750 outb(inb(dmabase
+ 2) & 0x60, dmabase
+ 2);
751 ide_setup_dma(hwif
, dmabase
, 8);
754 static const struct ide_port_info ali15x3_chipset __devinitdata
= {
756 .init_chipset
= init_chipset_ali15x3
,
757 .init_hwif
= init_hwif_ali15x3
,
758 .init_dma
= init_dma_ali15x3
,
759 .host_flags
= IDE_HFLAG_BOOTABLE
,
760 .pio_mask
= ATA_PIO5
,
761 .swdma_mask
= ATA_SWDMA2
,
762 .mwdma_mask
= ATA_MWDMA2
,
766 * alim15x3_init_one - set up an ALi15x3 IDE controller
767 * @dev: PCI device to set up
769 * Perform the actual set up for an ALi15x3 that has been found by the
773 static int __devinit
alim15x3_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
775 static struct pci_device_id ati_rs100
[] = {
776 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
) },
780 struct ide_port_info d
= ali15x3_chipset
;
781 u8 rev
= dev
->revision
;
783 if (pci_dev_present(ati_rs100
))
784 printk(KERN_WARNING
"alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
786 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
788 d
.host_flags
|= IDE_HFLAG_NO_LBA48_DMA
;
792 d
.host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
795 d
.udma_mask
= ATA_UDMA2
;
796 else if (rev
== 0xC2 || rev
== 0xC3)
797 d
.udma_mask
= ATA_UDMA4
;
798 else if (rev
== 0xC4)
799 d
.udma_mask
= ATA_UDMA5
;
801 d
.udma_mask
= ATA_UDMA6
;
804 #if defined(CONFIG_SPARC64)
805 d
.init_hwif
= init_hwif_common_ali15x3
;
806 #endif /* CONFIG_SPARC64 */
807 return ide_setup_pci_device(dev
, &d
);
811 static const struct pci_device_id alim15x3_pci_tbl
[] = {
812 { PCI_VDEVICE(AL
, PCI_DEVICE_ID_AL_M5229
), 0 },
813 { PCI_VDEVICE(AL
, PCI_DEVICE_ID_AL_M5228
), 0 },
816 MODULE_DEVICE_TABLE(pci
, alim15x3_pci_tbl
);
818 static struct pci_driver driver
= {
819 .name
= "ALI15x3_IDE",
820 .id_table
= alim15x3_pci_tbl
,
821 .probe
= alim15x3_init_one
,
824 static int __init
ali15x3_ide_init(void)
826 return ide_pci_register_driver(&driver
);
829 module_init(ali15x3_ide_init
);
831 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
832 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
833 MODULE_LICENSE("GPL");