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ide: remove write-only ->sata_misc[] from ide_hwif_t
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / alim15x3.c
1 /*
2 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
4 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
5 *
6 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
7 * May be copied or modified under the terms of the GNU General Public License
8 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 *
19 * Recent changes
20 * Don't use LBA48 mode on ALi <= 0xC4
21 * Don't poke 0x79 with a non ALi northbridge
22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
23 * Allow UDMA6 on revisions > 0xC4
24 *
25 * Documentation
26 * Chipset documentation available under NDA only
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/kernel.h>
33 #include <linux/pci.h>
34 #include <linux/hdreg.h>
35 #include <linux/ide.h>
36 #include <linux/init.h>
37 #include <linux/dmi.h>
38
39 #include <asm/io.h>
40
41 #define DISPLAY_ALI_TIMINGS
42
43 /*
44 * ALi devices are not plug in. Otherwise these static values would
45 * need to go. They ought to go away anyway
46 */
47
48 static u8 m5229_revision;
49 static u8 chip_is_1543c_e;
50 static struct pci_dev *isa_dev;
51
52 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
53 #include <linux/stat.h>
54 #include <linux/proc_fs.h>
55
56 static u8 ali_proc = 0;
57
58 static struct pci_dev *bmide_dev;
59
60 static char *fifo[4] = {
61 "FIFO Off",
62 "FIFO On ",
63 "DMA mode",
64 "PIO mode" };
65
66 static char *udmaT[8] = {
67 "1.5T",
68 " 2T",
69 "2.5T",
70 " 3T",
71 "3.5T",
72 " 4T",
73 " 6T",
74 " 8T"
75 };
76
77 static char *channel_status[8] = {
78 "OK ",
79 "busy ",
80 "DRQ ",
81 "DRQ busy ",
82 "error ",
83 "error busy ",
84 "error DRQ ",
85 "error DRQ busy"
86 };
87
88 /**
89 * ali_get_info - generate proc file for ALi IDE
90 * @buffer: buffer to fill
91 * @addr: address of user start in buffer
92 * @offset: offset into 'file'
93 * @count: buffer count
94 *
95 * Walks the Ali devices and outputs summary data on the tuning and
96 * anything else that will help with debugging
97 */
98
99 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
100 {
101 unsigned long bibma;
102 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
103 char *q, *p = buffer;
104
105 /* fetch rev. */
106 pci_read_config_byte(bmide_dev, 0x08, &rev);
107 if (rev >= 0xc1) /* M1543C or newer */
108 udmaT[7] = " ???";
109 else
110 fifo[3] = " ??? ";
111
112 /* first fetch bibma: */
113
114 bibma = pci_resource_start(bmide_dev, 4);
115
116 /*
117 * at that point bibma+0x2 et bibma+0xa are byte
118 * registers to investigate:
119 */
120 c0 = inb(bibma + 0x02);
121 c1 = inb(bibma + 0x0a);
122
123 p += sprintf(p,
124 "\n Ali M15x3 Chipset.\n");
125 p += sprintf(p,
126 " ------------------\n");
127 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
128 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
129
130 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
131 p += sprintf(p,
132 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
133 (reg53h & 0x02) ? "Yes" : "No ",
134 (reg53h & 0x01) ? "Yes" : "No " );
135 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
136 p += sprintf(p,
137 "FIFO Status: contains %d Words, runs%s%s\n\n",
138 (reg53h & 0x3f),
139 (reg53h & 0x40) ? " OVERWR" : "",
140 (reg53h & 0x80) ? " OVERRD." : "." );
141
142 p += sprintf(p,
143 "-------------------primary channel"
144 "-------------------secondary channel"
145 "---------\n\n");
146
147 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
148 p += sprintf(p,
149 "channel status: %s"
150 " %s\n",
151 (reg53h & 0x20) ? "On " : "Off",
152 (reg53h & 0x10) ? "On " : "Off" );
153
154 p += sprintf(p,
155 "both channels togth: %s"
156 " %s\n",
157 (c0&0x80) ? "No " : "Yes",
158 (c1&0x80) ? "No " : "Yes" );
159
160 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
161 p += sprintf(p,
162 "Channel state: %s %s\n",
163 channel_status[reg53h & 0x07],
164 channel_status[(reg53h & 0x70) >> 4] );
165
166 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
167 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
168 p += sprintf(p,
169 "Add. Setup Timing: %dT"
170 " %dT\n",
171 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
172 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
173
174 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
175 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
176 p += sprintf(p,
177 "Command Act. Count: %dT"
178 " %dT\n"
179 "Command Rec. Count: %dT"
180 " %dT\n\n",
181 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
182 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
183 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
184 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
185
186 p += sprintf(p,
187 "----------------drive0-----------drive1"
188 "------------drive0-----------drive1------\n\n");
189 p += sprintf(p,
190 "DMA enabled: %s %s"
191 " %s %s\n",
192 (c0&0x20) ? "Yes" : "No ",
193 (c0&0x40) ? "Yes" : "No ",
194 (c1&0x20) ? "Yes" : "No ",
195 (c1&0x40) ? "Yes" : "No " );
196
197 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
198 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
199 q = "FIFO threshold: %2d Words %2d Words"
200 " %2d Words %2d Words\n";
201 if (rev < 0xc1) {
202 if ((rev == 0x20) &&
203 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
204 p += sprintf(p, q, 8, 8, 8, 8);
205 } else {
206 p += sprintf(p, q,
207 (reg5xh & 0x03) + 12,
208 ((reg5xh & 0x30)>>4) + 12,
209 (reg5yh & 0x03) + 12,
210 ((reg5yh & 0x30)>>4) + 12 );
211 }
212 } else {
213 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
214 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
215 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
216 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
217 p += sprintf(p, q, t1, t2, t3, t4);
218 }
219
220 #if 0
221 p += sprintf(p,
222 "FIFO threshold: %2d Words %2d Words"
223 " %2d Words %2d Words\n",
224 (reg5xh & 0x03) + 12,
225 ((reg5xh & 0x30)>>4) + 12,
226 (reg5yh & 0x03) + 12,
227 ((reg5yh & 0x30)>>4) + 12 );
228 #endif
229
230 p += sprintf(p,
231 "FIFO mode: %s %s %s %s\n",
232 fifo[((reg5xh & 0x0c) >> 2)],
233 fifo[((reg5xh & 0xc0) >> 6)],
234 fifo[((reg5yh & 0x0c) >> 2)],
235 fifo[((reg5yh & 0xc0) >> 6)] );
236
237 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
238 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
239 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
240 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
241
242 p += sprintf(p,/*
243 "------------------drive0-----------drive1"
244 "------------drive0-----------drive1------\n")*/
245 "Dt RW act. Cnt %2dT %2dT"
246 " %2dT %2dT\n"
247 "Dt RW rec. Cnt %2dT %2dT"
248 " %2dT %2dT\n\n",
249 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
250 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
251 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
252 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
253 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
254 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
255 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
256 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
257
258 p += sprintf(p,
259 "-----------------------------------UDMA Timings"
260 "--------------------------------\n\n");
261
262 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
263 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
264 p += sprintf(p,
265 "UDMA: %s %s"
266 " %s %s\n"
267 "UDMA timings: %s %s"
268 " %s %s\n\n",
269 (reg5xh & 0x08) ? "OK" : "No",
270 (reg5xh & 0x80) ? "OK" : "No",
271 (reg5yh & 0x08) ? "OK" : "No",
272 (reg5yh & 0x80) ? "OK" : "No",
273 udmaT[(reg5xh & 0x07)],
274 udmaT[(reg5xh & 0x70) >> 4],
275 udmaT[reg5yh & 0x07],
276 udmaT[(reg5yh & 0x70) >> 4] );
277
278 return p-buffer; /* => must be less than 4k! */
279 }
280 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
281
282 /**
283 * ali_set_pio_mode - set host controller for PIO mode
284 * @drive: drive
285 * @pio: PIO mode number
286 *
287 * Program the controller for the given PIO mode.
288 */
289
290 static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
291 {
292 ide_hwif_t *hwif = HWIF(drive);
293 struct pci_dev *dev = to_pci_dev(hwif->dev);
294 int s_time, a_time, c_time;
295 u8 s_clc, a_clc, r_clc;
296 unsigned long flags;
297 int bus_speed = system_bus_clock();
298 int port = hwif->channel ? 0x5c : 0x58;
299 int portFIFO = hwif->channel ? 0x55 : 0x54;
300 u8 cd_dma_fifo = 0;
301 int unit = drive->select.b.unit & 1;
302
303 s_time = ide_pio_timings[pio].setup_time;
304 a_time = ide_pio_timings[pio].active_time;
305 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
306 s_clc = 0;
307 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
308 a_clc = 0;
309 c_time = ide_pio_timings[pio].cycle_time;
310
311 #if 0
312 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
313 r_clc = 0;
314 #endif
315
316 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
317 r_clc = 1;
318 } else {
319 if (r_clc >= 16)
320 r_clc = 0;
321 }
322 local_irq_save(flags);
323
324 /*
325 * PIO mode => ATA FIFO on, ATAPI FIFO off
326 */
327 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
328 if (drive->media==ide_disk) {
329 if (unit) {
330 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
331 } else {
332 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
333 }
334 } else {
335 if (unit) {
336 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
337 } else {
338 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
339 }
340 }
341
342 pci_write_config_byte(dev, port, s_clc);
343 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
344 local_irq_restore(flags);
345
346 /*
347 * setup active rec
348 * { 70, 165, 365 }, PIO Mode 0
349 * { 50, 125, 208 }, PIO Mode 1
350 * { 30, 100, 110 }, PIO Mode 2
351 * { 30, 80, 70 }, PIO Mode 3 with IORDY
352 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
353 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
354 */
355 }
356
357 /**
358 * ali_udma_filter - compute UDMA mask
359 * @drive: IDE device
360 *
361 * Return available UDMA modes.
362 *
363 * The actual rules for the ALi are:
364 * No UDMA on revisions <= 0x20
365 * Disk only for revisions < 0xC2
366 * Not WDC drives for revisions < 0xC2
367 *
368 * FIXME: WDC ifdef needs to die
369 */
370
371 static u8 ali_udma_filter(ide_drive_t *drive)
372 {
373 if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
374 if (drive->media != ide_disk)
375 return 0;
376 #ifndef CONFIG_WDC_ALI15X3
377 if (chip_is_1543c_e && strstr(drive->id->model, "WDC "))
378 return 0;
379 #endif
380 }
381
382 return drive->hwif->ultra_mask;
383 }
384
385 /**
386 * ali_set_dma_mode - set host controller for DMA mode
387 * @drive: drive
388 * @speed: DMA mode
389 *
390 * Configure the hardware for the desired IDE transfer mode.
391 */
392
393 static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
394 {
395 ide_hwif_t *hwif = HWIF(drive);
396 struct pci_dev *dev = to_pci_dev(hwif->dev);
397 u8 speed1 = speed;
398 u8 unit = (drive->select.b.unit & 0x01);
399 u8 tmpbyte = 0x00;
400 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
401
402 if (speed == XFER_UDMA_6)
403 speed1 = 0x47;
404
405 if (speed < XFER_UDMA_0) {
406 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
407 /*
408 * clear "ultra enable" bit
409 */
410 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
411 tmpbyte &= ultra_enable;
412 pci_write_config_byte(dev, m5229_udma, tmpbyte);
413
414 /*
415 * FIXME: Oh, my... DMA timings are never set.
416 */
417 } else {
418 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
419 tmpbyte &= (0x0f << ((1-unit) << 2));
420 /*
421 * enable ultra dma and set timing
422 */
423 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
424 pci_write_config_byte(dev, m5229_udma, tmpbyte);
425 if (speed >= XFER_UDMA_3) {
426 pci_read_config_byte(dev, 0x4b, &tmpbyte);
427 tmpbyte |= 1;
428 pci_write_config_byte(dev, 0x4b, tmpbyte);
429 }
430 }
431 }
432
433 /**
434 * ali15x3_dma_setup - begin a DMA phase
435 * @drive: target device
436 *
437 * Returns 1 if the DMA cannot be performed, zero on success.
438 */
439
440 static int ali15x3_dma_setup(ide_drive_t *drive)
441 {
442 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
443 if (rq_data_dir(drive->hwif->hwgroup->rq))
444 return 1; /* try PIO instead of DMA */
445 }
446 return ide_dma_setup(drive);
447 }
448
449 /**
450 * init_chipset_ali15x3 - Initialise an ALi IDE controller
451 * @dev: PCI device
452 * @name: Name of the controller
453 *
454 * This function initializes the ALI IDE controller and where
455 * appropriate also sets up the 1533 southbridge.
456 */
457
458 static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
459 {
460 unsigned long flags;
461 u8 tmpbyte;
462 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
463
464 m5229_revision = dev->revision;
465
466 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
467
468 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
469 if (!ali_proc) {
470 ali_proc = 1;
471 bmide_dev = dev;
472 ide_pci_create_host_proc("ali", ali_get_info);
473 }
474 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
475
476 local_irq_save(flags);
477
478 if (m5229_revision < 0xC2) {
479 /*
480 * revision 0x20 (1543-E, 1543-F)
481 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
482 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
483 */
484 pci_read_config_byte(dev, 0x4b, &tmpbyte);
485 /*
486 * clear bit 7
487 */
488 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
489 /*
490 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
491 */
492 if (m5229_revision >= 0x20 && isa_dev) {
493 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
494 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
495 }
496 goto out;
497 }
498
499 /*
500 * 1543C-B?, 1535, 1535D, 1553
501 * Note 1: not all "motherboard" support this detection
502 * Note 2: if no udma 66 device, the detection may "error".
503 * but in this case, we will not set the device to
504 * ultra 66, the detection result is not important
505 */
506
507 /*
508 * enable "Cable Detection", m5229, 0x4b, bit3
509 */
510 pci_read_config_byte(dev, 0x4b, &tmpbyte);
511 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
512
513 /*
514 * We should only tune the 1533 enable if we are using an ALi
515 * North bridge. We might have no north found on some zany
516 * box without a device at 0:0.0. The ALi bridge will be at
517 * 0:0.0 so if we didn't find one we know what is cooking.
518 */
519 if (north && north->vendor != PCI_VENDOR_ID_AL)
520 goto out;
521
522 if (m5229_revision < 0xC5 && isa_dev)
523 {
524 /*
525 * set south-bridge's enable bit, m1533, 0x79
526 */
527
528 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
529 if (m5229_revision == 0xC2) {
530 /*
531 * 1543C-B0 (m1533, 0x79, bit 2)
532 */
533 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
534 } else if (m5229_revision >= 0xC3) {
535 /*
536 * 1553/1535 (m1533, 0x79, bit 1)
537 */
538 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
539 }
540 }
541
542 out:
543 /*
544 * CD_ROM DMA on (m5229, 0x53, bit0)
545 * Enable this bit even if we want to use PIO.
546 * PIO FIFO off (m5229, 0x53, bit1)
547 * The hardware will use 0x54h and 0x55h to control PIO FIFO.
548 * (Not on later devices it seems)
549 *
550 * 0x53 changes meaning on later revs - we must no touch
551 * bit 1 on them. Need to check if 0x20 is the right break.
552 */
553 if (m5229_revision >= 0x20) {
554 pci_read_config_byte(dev, 0x53, &tmpbyte);
555
556 if (m5229_revision <= 0x20)
557 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
558 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
559 tmpbyte |= 0x03;
560 else
561 tmpbyte |= 0x01;
562
563 pci_write_config_byte(dev, 0x53, tmpbyte);
564 }
565 pci_dev_put(north);
566 pci_dev_put(isa_dev);
567 local_irq_restore(flags);
568 return 0;
569 }
570
571 /*
572 * Cable special cases
573 */
574
575 static const struct dmi_system_id cable_dmi_table[] = {
576 {
577 .ident = "HP Pavilion N5430",
578 .matches = {
579 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
580 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
581 },
582 },
583 {
584 .ident = "Toshiba Satellite S1800-814",
585 .matches = {
586 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
587 DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
588 },
589 },
590 { }
591 };
592
593 static int ali_cable_override(struct pci_dev *pdev)
594 {
595 /* Fujitsu P2000 */
596 if (pdev->subsystem_vendor == 0x10CF &&
597 pdev->subsystem_device == 0x10AF)
598 return 1;
599
600 /* Mitac 8317 (Winbook-A) and relatives */
601 if (pdev->subsystem_vendor == 0x1071 &&
602 pdev->subsystem_device == 0x8317)
603 return 1;
604
605 /* Systems by DMI */
606 if (dmi_check_system(cable_dmi_table))
607 return 1;
608
609 return 0;
610 }
611
612 /**
613 * ata66_ali15x3 - check for UDMA 66 support
614 * @hwif: IDE interface
615 *
616 * This checks if the controller and the cable are capable
617 * of UDMA66 transfers. It doesn't check the drives.
618 * But see note 2 below!
619 *
620 * FIXME: frobs bits that are not defined on newer ALi devicea
621 */
622
623 static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif)
624 {
625 struct pci_dev *dev = to_pci_dev(hwif->dev);
626 unsigned long flags;
627 u8 cbl = ATA_CBL_PATA40, tmpbyte;
628
629 local_irq_save(flags);
630
631 if (m5229_revision >= 0xC2) {
632 /*
633 * m5229 80-pin cable detection (from Host View)
634 *
635 * 0x4a bit0 is 0 => primary channel has 80-pin
636 * 0x4a bit1 is 0 => secondary channel has 80-pin
637 *
638 * Certain laptops use short but suitable cables
639 * and don't implement the detect logic.
640 */
641 if (ali_cable_override(dev))
642 cbl = ATA_CBL_PATA40_SHORT;
643 else {
644 pci_read_config_byte(dev, 0x4a, &tmpbyte);
645 if ((tmpbyte & (1 << hwif->channel)) == 0)
646 cbl = ATA_CBL_PATA80;
647 }
648 }
649
650 local_irq_restore(flags);
651
652 return cbl;
653 }
654
655 /**
656 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
657 * @hwif: IDE interface
658 *
659 * Initialize the IDE structure side of the ALi 15x3 driver.
660 */
661
662 static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
663 {
664 hwif->set_pio_mode = &ali_set_pio_mode;
665 hwif->set_dma_mode = &ali_set_dma_mode;
666 hwif->udma_filter = &ali_udma_filter;
667
668 hwif->cable_detect = ata66_ali15x3;
669
670 if (hwif->dma_base == 0)
671 return;
672
673 hwif->dma_setup = &ali15x3_dma_setup;
674 }
675
676 /**
677 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
678 * @hwif: interface to configure
679 *
680 * Obtain the IRQ tables for an ALi based IDE solution on the PC
681 * class platforms. This part of the code isn't applicable to the
682 * Sparc systems
683 */
684
685 static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
686 {
687 struct pci_dev *dev = to_pci_dev(hwif->dev);
688 u8 ideic, inmir;
689 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
690 1, 11, 0, 12, 0, 14, 0, 15 };
691 int irq = -1;
692
693 if (dev->device == PCI_DEVICE_ID_AL_M5229)
694 hwif->irq = hwif->channel ? 15 : 14;
695
696 if (isa_dev) {
697 /*
698 * read IDE interface control
699 */
700 pci_read_config_byte(isa_dev, 0x58, &ideic);
701
702 /* bit0, bit1 */
703 ideic = ideic & 0x03;
704
705 /* get IRQ for IDE Controller */
706 if ((hwif->channel && ideic == 0x03) ||
707 (!hwif->channel && !ideic)) {
708 /*
709 * get SIRQ1 routing table
710 */
711 pci_read_config_byte(isa_dev, 0x44, &inmir);
712 inmir = inmir & 0x0f;
713 irq = irq_routing_table[inmir];
714 } else if (hwif->channel && !(ideic & 0x01)) {
715 /*
716 * get SIRQ2 routing table
717 */
718 pci_read_config_byte(isa_dev, 0x75, &inmir);
719 inmir = inmir & 0x0f;
720 irq = irq_routing_table[inmir];
721 }
722 if(irq >= 0)
723 hwif->irq = irq;
724 }
725
726 init_hwif_common_ali15x3(hwif);
727 }
728
729 /**
730 * init_dma_ali15x3 - set up DMA on ALi15x3
731 * @hwif: IDE interface
732 * @dmabase: DMA interface base PCI address
733 *
734 * Set up the DMA functionality on the ALi 15x3. For the ALi
735 * controllers this is generic so we can let the generic code do
736 * the actual work.
737 */
738
739 static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
740 {
741 if (m5229_revision < 0x20)
742 return;
743 if (!hwif->channel)
744 outb(inb(dmabase + 2) & 0x60, dmabase + 2);
745 ide_setup_dma(hwif, dmabase);
746 }
747
748 static const struct ide_port_info ali15x3_chipset __devinitdata = {
749 .name = "ALI15X3",
750 .init_chipset = init_chipset_ali15x3,
751 .init_hwif = init_hwif_ali15x3,
752 .init_dma = init_dma_ali15x3,
753 .host_flags = IDE_HFLAG_BOOTABLE,
754 .pio_mask = ATA_PIO5,
755 .swdma_mask = ATA_SWDMA2,
756 .mwdma_mask = ATA_MWDMA2,
757 };
758
759 /**
760 * alim15x3_init_one - set up an ALi15x3 IDE controller
761 * @dev: PCI device to set up
762 *
763 * Perform the actual set up for an ALi15x3 that has been found by the
764 * hot plug layer.
765 */
766
767 static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
768 {
769 static struct pci_device_id ati_rs100[] = {
770 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) },
771 { },
772 };
773
774 struct ide_port_info d = ali15x3_chipset;
775 u8 rev = dev->revision, idx = id->driver_data;
776
777 if (pci_dev_present(ati_rs100))
778 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
779
780 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
781 if (rev <= 0xC4)
782 d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
783
784 if (rev >= 0x20) {
785 if (rev == 0x20)
786 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
787
788 if (rev < 0xC2)
789 d.udma_mask = ATA_UDMA2;
790 else if (rev == 0xC2 || rev == 0xC3)
791 d.udma_mask = ATA_UDMA4;
792 else if (rev == 0xC4)
793 d.udma_mask = ATA_UDMA5;
794 else
795 d.udma_mask = ATA_UDMA6;
796 }
797
798 if (idx == 0)
799 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
800
801 #if defined(CONFIG_SPARC64)
802 d.init_hwif = init_hwif_common_ali15x3;
803 #endif /* CONFIG_SPARC64 */
804 return ide_setup_pci_device(dev, &d);
805 }
806
807
808 static const struct pci_device_id alim15x3_pci_tbl[] = {
809 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
810 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
811 { 0, },
812 };
813 MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
814
815 static struct pci_driver driver = {
816 .name = "ALI15x3_IDE",
817 .id_table = alim15x3_pci_tbl,
818 .probe = alim15x3_init_one,
819 };
820
821 static int __init ali15x3_ide_init(void)
822 {
823 return ide_pci_register_driver(&driver);
824 }
825
826 module_init(ali15x3_ide_init);
827
828 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
829 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
830 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)