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Merge git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / cris / ide-cris.c
1 /* $Id: cris-ide-driver.patch,v 1.1 2005/06/29 21:39:07 akpm Exp $
2 *
3 * Etrax specific IDE functions, like init and PIO-mode setting etc.
4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
5 * Copyright (c) 2000-2005 Axis Communications AB
6 *
7 * Authors: Bjorn Wesen (initial version)
8 * Mikael Starvik (crisv32 port)
9 */
10
11 /* Regarding DMA:
12 *
13 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
14 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
15 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
16 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
17 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
18 */
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/blkdev.h>
27 #include <linux/hdreg.h>
28 #include <linux/ide.h>
29 #include <linux/init.h>
30
31 #include <asm/io.h>
32 #include <asm/dma.h>
33
34 /* number of DMA descriptors */
35 #define MAX_DMA_DESCRS 64
36
37 /* number of times to retry busy-flags when reading/writing IDE-registers
38 * this can't be too high because a hung harddisk might cause the watchdog
39 * to trigger (sometimes INB and OUTB are called with irq's disabled)
40 */
41
42 #define IDE_REGISTER_TIMEOUT 300
43
44 #define LOWDB(x)
45 #define D(x)
46
47 enum /* Transfer types */
48 {
49 TYPE_PIO,
50 TYPE_DMA,
51 TYPE_UDMA
52 };
53
54 /* CRISv32 specifics */
55 #ifdef CONFIG_ETRAX_ARCH_V32
56 #include <asm/arch/hwregs/ata_defs.h>
57 #include <asm/arch/hwregs/dma_defs.h>
58 #include <asm/arch/hwregs/dma.h>
59 #include <asm/arch/pinmux.h>
60
61 #define ATA_UDMA2_CYC 2
62 #define ATA_UDMA2_DVS 3
63 #define ATA_UDMA1_CYC 2
64 #define ATA_UDMA1_DVS 4
65 #define ATA_UDMA0_CYC 4
66 #define ATA_UDMA0_DVS 6
67 #define ATA_DMA2_STROBE 7
68 #define ATA_DMA2_HOLD 1
69 #define ATA_DMA1_STROBE 8
70 #define ATA_DMA1_HOLD 3
71 #define ATA_DMA0_STROBE 25
72 #define ATA_DMA0_HOLD 19
73 #define ATA_PIO4_SETUP 3
74 #define ATA_PIO4_STROBE 7
75 #define ATA_PIO4_HOLD 1
76 #define ATA_PIO3_SETUP 3
77 #define ATA_PIO3_STROBE 9
78 #define ATA_PIO3_HOLD 3
79 #define ATA_PIO2_SETUP 3
80 #define ATA_PIO2_STROBE 13
81 #define ATA_PIO2_HOLD 5
82 #define ATA_PIO1_SETUP 5
83 #define ATA_PIO1_STROBE 23
84 #define ATA_PIO1_HOLD 9
85 #define ATA_PIO0_SETUP 9
86 #define ATA_PIO0_STROBE 39
87 #define ATA_PIO0_HOLD 9
88
89 int
90 cris_ide_ack_intr(ide_hwif_t* hwif)
91 {
92 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
93 int, hwif->io_ports[0]);
94 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
95 return 1;
96 }
97
98 static inline int
99 cris_ide_busy(void)
100 {
101 reg_ata_rs_stat_data stat_data;
102 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
103 return stat_data.busy;
104 }
105
106 static inline int
107 cris_ide_ready(void)
108 {
109 return !cris_ide_busy();
110 }
111
112 static inline int
113 cris_ide_data_available(unsigned short* data)
114 {
115 reg_ata_rs_stat_data stat_data;
116 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
117 *data = stat_data.data;
118 return stat_data.dav;
119 }
120
121 static void
122 cris_ide_write_command(unsigned long command)
123 {
124 REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
125 }
126
127 static void
128 cris_ide_set_speed(int type, int setup, int strobe, int hold)
129 {
130 reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
131 reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
132
133 if (type == TYPE_PIO) {
134 ctrl0.pio_setup = setup;
135 ctrl0.pio_strb = strobe;
136 ctrl0.pio_hold = hold;
137 } else if (type == TYPE_DMA) {
138 ctrl0.dma_strb = strobe;
139 ctrl0.dma_hold = hold;
140 } else if (type == TYPE_UDMA) {
141 ctrl1.udma_tcyc = setup;
142 ctrl1.udma_tdvs = strobe;
143 }
144 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
145 REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
146 }
147
148 static unsigned long
149 cris_ide_base_address(int bus)
150 {
151 reg_ata_rw_ctrl2 ctrl2 = {0};
152 ctrl2.sel = bus;
153 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
154 }
155
156 static unsigned long
157 cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
158 {
159 reg_ata_rw_ctrl2 ctrl2 = {0};
160 ctrl2.addr = addr;
161 ctrl2.cs1 = cs1;
162 ctrl2.cs0 = cs0;
163 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
164 }
165
166 static __init void
167 cris_ide_reset(unsigned val)
168 {
169 reg_ata_rw_ctrl0 ctrl0 = {0};
170 ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
171 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
172 }
173
174 static __init void
175 cris_ide_init(void)
176 {
177 reg_ata_rw_ctrl0 ctrl0 = {0};
178 reg_ata_rw_intr_mask intr_mask = {0};
179
180 ctrl0.en = regk_ata_yes;
181 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
182
183 intr_mask.bus0 = regk_ata_yes;
184 intr_mask.bus1 = regk_ata_yes;
185 intr_mask.bus2 = regk_ata_yes;
186 intr_mask.bus3 = regk_ata_yes;
187
188 REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
189
190 crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
191 crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
192
193 crisv32_pinmux_alloc_fixed(pinmux_ata);
194 crisv32_pinmux_alloc_fixed(pinmux_ata0);
195 crisv32_pinmux_alloc_fixed(pinmux_ata1);
196 crisv32_pinmux_alloc_fixed(pinmux_ata2);
197 crisv32_pinmux_alloc_fixed(pinmux_ata3);
198
199 DMA_RESET(regi_dma2);
200 DMA_ENABLE(regi_dma2);
201 DMA_RESET(regi_dma3);
202 DMA_ENABLE(regi_dma3);
203
204 DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
205 DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
206 }
207
208 static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
209
210 #define cris_dma_descr_type dma_descr_data
211 #define cris_pio_read regk_ata_rd
212 #define cris_ultra_mask 0x7
213 #define MAX_DESCR_SIZE 0xffffffffUL
214
215 static unsigned long
216 cris_ide_get_reg(unsigned long reg)
217 {
218 return (reg & 0x0e000000) >> 25;
219 }
220
221 static void
222 cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
223 {
224 d->buf = (char*)virt_to_phys(buf);
225 d->after = d->buf + len;
226 d->eol = last;
227 }
228
229 static void
230 cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
231 {
232 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
233 reg_ata_rw_trf_cnt trf_cnt = {0};
234
235 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
236 mycontext.saved_data_buf = d->buf;
237 /* start the dma channel */
238 DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
239
240 /* initiate a multi word dma read using PIO handshaking */
241 trf_cnt.cnt = len >> 1;
242 /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
243 if (type == TYPE_UDMA)
244 trf_cnt.cnt++;
245 REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
246
247 ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
248 ctrl2.trf_mode = regk_ata_dma;
249 ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
250 type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
251 ctrl2.multi = regk_ata_yes;
252 ctrl2.dma_size = regk_ata_word;
253 REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
254 }
255
256 static void
257 cris_ide_wait_dma(int dir)
258 {
259 reg_dma_rw_stat status;
260 do
261 {
262 status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
263 } while(status.list_state != regk_dma_data_at_eol);
264 }
265
266 static int cris_dma_test_irq(ide_drive_t *drive)
267 {
268 int intr = REG_RD_INT(ata, regi_ata, r_intr);
269 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
270 return intr & (1 << ctrl2.sel) ? 1 : 0;
271 }
272
273 static void cris_ide_initialize_dma(int dir)
274 {
275 }
276
277 #else
278 /* CRISv10 specifics */
279 #include <asm/arch/svinto.h>
280 #include <asm/arch/io_interface_mux.h>
281
282 /* PIO timing (in R_ATA_CONFIG)
283 *
284 * _____________________________
285 * ADDRESS : ________/
286 *
287 * _______________
288 * DIOR : ____________/ \__________
289 *
290 * _______________
291 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
292 *
293 *
294 * DIOR is unbuffered while address and data is buffered.
295 * This creates two problems:
296 * 1. The DIOR pulse is to early (because it is unbuffered)
297 * 2. The rise time of DIOR is long
298 *
299 * There are at least three different plausible solutions
300 * 1. Use a pad capable of larger currents in Etrax
301 * 2. Use an external buffer
302 * 3. Make the strobe pulse longer
303 *
304 * Some of the strobe timings below are modified to compensate
305 * for this. This implies a slight performance decrease.
306 *
307 * THIS SHOULD NEVER BE CHANGED!
308 *
309 * TODO: Is this true for the latest LX boards still ?
310 */
311
312 #define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */
313 #define ATA_UDMA2_DVS 0
314 #define ATA_UDMA1_CYC 0
315 #define ATA_UDMA1_DVS 0
316 #define ATA_UDMA0_CYC 0
317 #define ATA_UDMA0_DVS 0
318 #define ATA_DMA2_STROBE 4
319 #define ATA_DMA2_HOLD 0
320 #define ATA_DMA1_STROBE 4
321 #define ATA_DMA1_HOLD 1
322 #define ATA_DMA0_STROBE 12
323 #define ATA_DMA0_HOLD 9
324 #define ATA_PIO4_SETUP 1
325 #define ATA_PIO4_STROBE 5
326 #define ATA_PIO4_HOLD 0
327 #define ATA_PIO3_SETUP 1
328 #define ATA_PIO3_STROBE 5
329 #define ATA_PIO3_HOLD 1
330 #define ATA_PIO2_SETUP 1
331 #define ATA_PIO2_STROBE 6
332 #define ATA_PIO2_HOLD 2
333 #define ATA_PIO1_SETUP 2
334 #define ATA_PIO1_STROBE 11
335 #define ATA_PIO1_HOLD 4
336 #define ATA_PIO0_SETUP 4
337 #define ATA_PIO0_STROBE 19
338 #define ATA_PIO0_HOLD 4
339
340 int
341 cris_ide_ack_intr(ide_hwif_t* hwif)
342 {
343 return 1;
344 }
345
346 static inline int
347 cris_ide_busy(void)
348 {
349 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
350 }
351
352 static inline int
353 cris_ide_ready(void)
354 {
355 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
356 }
357
358 static inline int
359 cris_ide_data_available(unsigned short* data)
360 {
361 unsigned long status = *R_ATA_STATUS_DATA;
362 *data = (unsigned short)status;
363 return status & IO_MASK(R_ATA_STATUS_DATA, dav);
364 }
365
366 static void
367 cris_ide_write_command(unsigned long command)
368 {
369 *R_ATA_CTRL_DATA = command;
370 }
371
372 static void
373 cris_ide_set_speed(int type, int setup, int strobe, int hold)
374 {
375 static int pio_setup = ATA_PIO4_SETUP;
376 static int pio_strobe = ATA_PIO4_STROBE;
377 static int pio_hold = ATA_PIO4_HOLD;
378 static int dma_strobe = ATA_DMA2_STROBE;
379 static int dma_hold = ATA_DMA2_HOLD;
380
381 if (type == TYPE_PIO) {
382 pio_setup = setup;
383 pio_strobe = strobe;
384 pio_hold = hold;
385 } else if (type == TYPE_DMA) {
386 dma_strobe = strobe;
387 dma_hold = hold;
388 }
389 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
390 IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
391 IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) |
392 IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) |
393 IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
394 IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) );
395 }
396
397 static unsigned long
398 cris_ide_base_address(int bus)
399 {
400 return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
401 }
402
403 static unsigned long
404 cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
405 {
406 return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
407 IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
408 IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
409 }
410
411 static __init void
412 cris_ide_reset(unsigned val)
413 {
414 #ifdef CONFIG_ETRAX_IDE_G27_RESET
415 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
416 #endif
417 #ifdef CONFIG_ETRAX_IDE_PB7_RESET
418 port_pb_dir_shadow = port_pb_dir_shadow |
419 IO_STATE(R_PORT_PB_DIR, dir7, output);
420 *R_PORT_PB_DIR = port_pb_dir_shadow;
421 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
422 #endif
423 }
424
425 static __init void
426 cris_ide_init(void)
427 {
428 volatile unsigned int dummy;
429
430 *R_ATA_CTRL_DATA = 0;
431 *R_ATA_TRANSFER_CNT = 0;
432 *R_ATA_CONFIG = 0;
433
434 if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
435 printk(KERN_CRIT "ide: Failed to get IO interface\n");
436 return;
437 } else if (cris_request_dma(ATA_TX_DMA_NBR,
438 "ETRAX100LX IDE TX",
439 DMA_VERBOSE_ON_ERROR,
440 dma_ata)) {
441 cris_free_io_interface(if_ata);
442 printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
443 return;
444 } else if (cris_request_dma(ATA_RX_DMA_NBR,
445 "ETRAX100LX IDE RX",
446 DMA_VERBOSE_ON_ERROR,
447 dma_ata)) {
448 cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
449 cris_free_io_interface(if_ata);
450 printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
451 return;
452 }
453
454 /* make a dummy read to set the ata controller in a proper state */
455 dummy = *R_ATA_STATUS_DATA;
456
457 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
458 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
459 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
460
461 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
462
463 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
464 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
465 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
466 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
467
468 /* reset the dma channels we will use */
469
470 RESET_DMA(ATA_TX_DMA_NBR);
471 RESET_DMA(ATA_RX_DMA_NBR);
472 WAIT_DMA(ATA_TX_DMA_NBR);
473 WAIT_DMA(ATA_RX_DMA_NBR);
474 }
475
476 #define cris_dma_descr_type etrax_dma_descr
477 #define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
478 #define cris_ultra_mask 0x0
479 #define MAX_DESCR_SIZE 0x10000UL
480
481 static unsigned long
482 cris_ide_get_reg(unsigned long reg)
483 {
484 return (reg & 0x0e000000) >> 25;
485 }
486
487 static void
488 cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
489 {
490 d->buf = virt_to_phys(buf);
491 d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
492 if (last)
493 d->ctrl |= d_eol;
494 }
495
496 static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
497 {
498 unsigned long cmd;
499
500 if (dir) {
501 /* need to do this before RX DMA due to a chip bug
502 * it is enough to just flush the part of the cache that
503 * corresponds to the buffers we start, but since HD transfers
504 * usually are more than 8 kB, it is easier to optimize for the
505 * normal case and just flush the entire cache. its the only
506 * way to be sure! (OB movie quote)
507 */
508 flush_etrax_cache();
509 *R_DMA_CH3_FIRST = virt_to_phys(d);
510 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
511
512 } else {
513 *R_DMA_CH2_FIRST = virt_to_phys(d);
514 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
515 }
516
517 /* initiate a multi word dma read using DMA handshaking */
518
519 *R_ATA_TRANSFER_CNT =
520 IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
521
522 cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
523 cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
524 IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
525 *R_ATA_CTRL_DATA =
526 cmd |
527 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
528 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
529 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
530 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
531 }
532
533 static void
534 cris_ide_wait_dma(int dir)
535 {
536 if (dir)
537 WAIT_DMA(ATA_RX_DMA_NBR);
538 else
539 WAIT_DMA(ATA_TX_DMA_NBR);
540 }
541
542 static int cris_dma_test_irq(ide_drive_t *drive)
543 {
544 int intr = *R_IRQ_MASK0_RD;
545 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG);
546 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
547 }
548
549
550 static void cris_ide_initialize_dma(int dir)
551 {
552 if (dir)
553 {
554 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
555 WAIT_DMA(ATA_RX_DMA_NBR);
556 }
557 else
558 {
559 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
560 WAIT_DMA(ATA_TX_DMA_NBR);
561 }
562 }
563
564 #endif
565
566 void
567 cris_ide_outw(unsigned short data, unsigned long reg) {
568 int timeleft;
569
570 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
571
572 /* note the lack of handling any timeouts. we stop waiting, but we don't
573 * really notify anybody.
574 */
575
576 timeleft = IDE_REGISTER_TIMEOUT;
577 /* wait for busy flag */
578 do {
579 timeleft--;
580 } while(timeleft && cris_ide_busy());
581
582 /*
583 * Fall through at a timeout, so the ongoing command will be
584 * aborted by the write below, which is expected to be a dummy
585 * command to the command register. This happens when a faulty
586 * drive times out on a command. See comment on timeout in
587 * INB.
588 */
589 if(!timeleft)
590 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
591
592 cris_ide_write_command(reg|data); /* write data to the drive's register */
593
594 timeleft = IDE_REGISTER_TIMEOUT;
595 /* wait for transmitter ready */
596 do {
597 timeleft--;
598 } while(timeleft && !cris_ide_ready());
599 }
600
601 void
602 cris_ide_outb(unsigned char data, unsigned long reg)
603 {
604 cris_ide_outw(data, reg);
605 }
606
607 void
608 cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
609 {
610 cris_ide_outw(addr, port);
611 }
612
613 unsigned short
614 cris_ide_inw(unsigned long reg) {
615 int timeleft;
616 unsigned short val;
617
618 timeleft = IDE_REGISTER_TIMEOUT;
619 /* wait for busy flag */
620 do {
621 timeleft--;
622 } while(timeleft && cris_ide_busy());
623
624 if(!timeleft) {
625 /*
626 * If we're asked to read the status register, like for
627 * example when a command does not complete for an
628 * extended time, but the ATA interface is stuck in a
629 * busy state at the *ETRAX* ATA interface level (as has
630 * happened repeatedly with at least one bad disk), then
631 * the best thing to do is to pretend that we read
632 * "busy" in the status register, so the IDE driver will
633 * time-out, abort the ongoing command and perform a
634 * reset sequence. Note that the subsequent OUT_BYTE
635 * call will also timeout on busy, but as long as the
636 * write is still performed, everything will be fine.
637 */
638 if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
639 return BUSY_STAT;
640 else
641 /* For other rare cases we assume 0 is good enough. */
642 return 0;
643 }
644
645 cris_ide_write_command(reg | cris_pio_read);
646
647 timeleft = IDE_REGISTER_TIMEOUT;
648 /* wait for available */
649 do {
650 timeleft--;
651 } while(timeleft && !cris_ide_data_available(&val));
652
653 if(!timeleft)
654 return 0;
655
656 LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
657
658 return val;
659 }
660
661 unsigned char
662 cris_ide_inb(unsigned long reg)
663 {
664 return (unsigned char)cris_ide_inw(reg);
665 }
666
667 static int cris_dma_check (ide_drive_t *drive);
668 static int cris_dma_end (ide_drive_t *drive);
669 static int cris_dma_setup (ide_drive_t *drive);
670 static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command);
671 static int cris_dma_test_irq(ide_drive_t *drive);
672 static void cris_dma_start(ide_drive_t *drive);
673 static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
674 static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
675 static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
676 static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
677 static int cris_dma_on (ide_drive_t *drive);
678
679 static void cris_dma_off(ide_drive_t *drive)
680 {
681 }
682
683 static void cris_set_pio_mode(ide_drive_t *drive, const u8 pio)
684 {
685 int setup, strobe, hold;
686
687 switch(pio)
688 {
689 case 0:
690 setup = ATA_PIO0_SETUP;
691 strobe = ATA_PIO0_STROBE;
692 hold = ATA_PIO0_HOLD;
693 break;
694 case 1:
695 setup = ATA_PIO1_SETUP;
696 strobe = ATA_PIO1_STROBE;
697 hold = ATA_PIO1_HOLD;
698 break;
699 case 2:
700 setup = ATA_PIO2_SETUP;
701 strobe = ATA_PIO2_STROBE;
702 hold = ATA_PIO2_HOLD;
703 break;
704 case 3:
705 setup = ATA_PIO3_SETUP;
706 strobe = ATA_PIO3_STROBE;
707 hold = ATA_PIO3_HOLD;
708 break;
709 case 4:
710 setup = ATA_PIO4_SETUP;
711 strobe = ATA_PIO4_STROBE;
712 hold = ATA_PIO4_HOLD;
713 break;
714 default:
715 return;
716 }
717
718 cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
719
720 (void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
721 }
722
723 static int speed_cris_ide(ide_drive_t *drive, const u8 speed)
724 {
725 int cyc = 0, dvs = 0, strobe = 0, hold = 0;
726
727 switch(speed)
728 {
729 case XFER_UDMA_0:
730 cyc = ATA_UDMA0_CYC;
731 dvs = ATA_UDMA0_DVS;
732 break;
733 case XFER_UDMA_1:
734 cyc = ATA_UDMA1_CYC;
735 dvs = ATA_UDMA1_DVS;
736 break;
737 case XFER_UDMA_2:
738 cyc = ATA_UDMA2_CYC;
739 dvs = ATA_UDMA2_DVS;
740 break;
741 case XFER_MW_DMA_0:
742 strobe = ATA_DMA0_STROBE;
743 hold = ATA_DMA0_HOLD;
744 break;
745 case XFER_MW_DMA_1:
746 strobe = ATA_DMA1_STROBE;
747 hold = ATA_DMA1_HOLD;
748 break;
749 case XFER_MW_DMA_2:
750 strobe = ATA_DMA2_STROBE;
751 hold = ATA_DMA2_HOLD;
752 break;
753 default:
754 BUG();
755 break;
756 }
757
758 if (speed >= XFER_UDMA_0)
759 cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
760 else
761 cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
762
763 return ide_config_drive_speed(drive, speed);
764 }
765
766 void __init
767 init_e100_ide (void)
768 {
769 hw_regs_t hw;
770 int ide_offsets[IDE_NR_PORTS];
771 int h;
772 int i;
773
774 printk("ide: ETRAX FS built-in ATA DMA controller\n");
775
776 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
777 ide_offsets[i] = cris_ide_reg_addr(i, 0, 1);
778
779 /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
780 ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0);
781
782 /* first fill in some stuff in the ide_hwifs fields */
783
784 for(h = 0; h < MAX_HWIFS; h++) {
785 ide_hwif_t *hwif = &ide_hwifs[h];
786 ide_setup_ports(&hw, cris_ide_base_address(h),
787 ide_offsets,
788 0, 0, cris_ide_ack_intr,
789 ide_default_irq(0));
790 ide_register_hw(&hw, 1, &hwif);
791 hwif->mmio = 1;
792 hwif->chipset = ide_etrax100;
793 hwif->set_pio_mode = &cris_set_pio_mode;
794 hwif->speedproc = &speed_cris_ide;
795 hwif->ata_input_data = &cris_ide_input_data;
796 hwif->ata_output_data = &cris_ide_output_data;
797 hwif->atapi_input_bytes = &cris_atapi_input_bytes;
798 hwif->atapi_output_bytes = &cris_atapi_output_bytes;
799 hwif->ide_dma_check = &cris_dma_check;
800 hwif->ide_dma_end = &cris_dma_end;
801 hwif->dma_setup = &cris_dma_setup;
802 hwif->dma_exec_cmd = &cris_dma_exec_cmd;
803 hwif->ide_dma_test_irq = &cris_dma_test_irq;
804 hwif->dma_start = &cris_dma_start;
805 hwif->OUTB = &cris_ide_outb;
806 hwif->OUTW = &cris_ide_outw;
807 hwif->OUTBSYNC = &cris_ide_outbsync;
808 hwif->INB = &cris_ide_inb;
809 hwif->INW = &cris_ide_inw;
810 hwif->dma_host_off = &cris_dma_off;
811 hwif->dma_host_on = &cris_dma_on;
812 hwif->dma_off_quietly = &cris_dma_off;
813 hwif->cbl = ATA_CBL_PATA40;
814 hwif->pio_mask = ATA_PIO4,
815 hwif->ultra_mask = cris_ultra_mask;
816 hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */
817 hwif->autodma = 1;
818 hwif->drives[0].autodma = 1;
819 hwif->drives[1].autodma = 1;
820 }
821
822 /* Reset pulse */
823 cris_ide_reset(0);
824 udelay(25);
825 cris_ide_reset(1);
826
827 cris_ide_init();
828
829 cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
830 cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
831 cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
832 }
833
834 static int cris_dma_on (ide_drive_t *drive)
835 {
836 return 0;
837 }
838
839
840 static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
841
842 /*
843 * The following routines are mainly used by the ATAPI drivers.
844 *
845 * These routines will round up any request for an odd number of bytes,
846 * so if an odd bytecount is specified, be sure that there's at least one
847 * extra byte allocated for the buffer.
848 */
849 static void
850 cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
851 {
852 D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
853 buffer, bytecount));
854
855 if(bytecount & 1) {
856 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
857 bytecount++; /* to round off */
858 }
859
860 /* setup DMA and start transfer */
861
862 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
863 cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
864
865 /* wait for completion */
866 LED_DISK_READ(1);
867 cris_ide_wait_dma(1);
868 LED_DISK_READ(0);
869 }
870
871 static void
872 cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
873 {
874 D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
875 buffer, bytecount));
876
877 if(bytecount & 1) {
878 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
879 bytecount++;
880 }
881
882 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
883 cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
884
885 /* wait for completion */
886
887 LED_DISK_WRITE(1);
888 LED_DISK_READ(1);
889 cris_ide_wait_dma(0);
890 LED_DISK_WRITE(0);
891 }
892
893 /*
894 * This is used for most PIO data transfers *from* the IDE interface
895 */
896 static void
897 cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
898 {
899 cris_atapi_input_bytes(drive, buffer, wcount << 2);
900 }
901
902 /*
903 * This is used for most PIO data transfers *to* the IDE interface
904 */
905 static void
906 cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
907 {
908 cris_atapi_output_bytes(drive, buffer, wcount << 2);
909 }
910
911 /* we only have one DMA channel on the chip for ATA, so we can keep these statically */
912 static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
913 static unsigned int ata_tot_size;
914
915 /*
916 * cris_ide_build_dmatable() prepares a dma request.
917 * Returns 0 if all went okay, returns 1 otherwise.
918 */
919 static int cris_ide_build_dmatable (ide_drive_t *drive)
920 {
921 ide_hwif_t *hwif = drive->hwif;
922 struct scatterlist* sg;
923 struct request *rq = drive->hwif->hwgroup->rq;
924 unsigned long size, addr;
925 unsigned int count = 0;
926 int i = 0;
927
928 sg = hwif->sg_table;
929
930 ata_tot_size = 0;
931
932 ide_map_sg(drive, rq);
933 i = hwif->sg_nents;
934
935 while(i) {
936 /*
937 * Determine addr and size of next buffer area. We assume that
938 * individual virtual buffers are always composed linearly in
939 * physical memory. For example, we assume that any 8kB buffer
940 * is always composed of two adjacent physical 4kB pages rather
941 * than two possibly non-adjacent physical 4kB pages.
942 */
943 /* group sequential buffers into one large buffer */
944 addr = page_to_phys(sg->page) + sg->offset;
945 size = sg_dma_len(sg);
946 while (sg++, --i) {
947 if ((addr + size) != page_to_phys(sg->page) + sg->offset)
948 break;
949 size += sg_dma_len(sg);
950 }
951
952 /* did we run out of descriptors? */
953
954 if(count >= MAX_DMA_DESCRS) {
955 printk("%s: too few DMA descriptors\n", drive->name);
956 return 1;
957 }
958
959 /* however, this case is more difficult - rw_trf_cnt cannot be more
960 than 65536 words per transfer, so in that case we need to either
961 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
962 the descriptors, or
963 2) simply do the request here, and get dma_intr to only ide_end_request on
964 those blocks that were actually set-up for transfer.
965 */
966
967 if(ata_tot_size + size > 131072) {
968 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
969 return 1;
970 }
971
972 /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
973 don't handle size > 131072 only one split is necessary */
974
975 if(size > MAX_DESCR_SIZE) {
976 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
977 count++;
978 ata_tot_size += MAX_DESCR_SIZE;
979 size -= MAX_DESCR_SIZE;
980 addr += MAX_DESCR_SIZE;
981 }
982
983 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
984 count++;
985 ata_tot_size += size;
986 }
987
988 if (count) {
989 /* return and say all is ok */
990 return 0;
991 }
992
993 printk("%s: empty DMA table?\n", drive->name);
994 return 1; /* let the PIO routines handle this weirdness */
995 }
996
997 /*
998 * cris_dma_intr() is the handler for disk read/write DMA interrupts
999 */
1000 static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
1001 {
1002 LED_DISK_READ(0);
1003 LED_DISK_WRITE(0);
1004
1005 return ide_dma_intr(drive);
1006 }
1007
1008 /*
1009 * Functions below initiates/aborts DMA read/write operations on a drive.
1010 *
1011 * The caller is assumed to have selected the drive and programmed the drive's
1012 * sector address using CHS or LBA. All that remains is to prepare for DMA
1013 * and then issue the actual read/write DMA/PIO command to the drive.
1014 *
1015 * For ATAPI devices, we just prepare for DMA and return. The caller should
1016 * then issue the packet command to the drive and call us again with
1017 * cris_dma_start afterwards.
1018 *
1019 * Returns 0 if all went well.
1020 * Returns 1 if DMA read/write could not be started, in which case
1021 * the caller should revert to PIO for the current request.
1022 */
1023
1024 static int cris_dma_check(ide_drive_t *drive)
1025 {
1026 if (ide_tune_dma(drive))
1027 return 0;
1028
1029 return -1;
1030 }
1031
1032 static int cris_dma_end(ide_drive_t *drive)
1033 {
1034 drive->waiting_for_dma = 0;
1035 return 0;
1036 }
1037
1038 static int cris_dma_setup(ide_drive_t *drive)
1039 {
1040 struct request *rq = drive->hwif->hwgroup->rq;
1041
1042 cris_ide_initialize_dma(!rq_data_dir(rq));
1043 if (cris_ide_build_dmatable (drive)) {
1044 ide_map_sg(drive, rq);
1045 return 1;
1046 }
1047
1048 drive->waiting_for_dma = 1;
1049 return 0;
1050 }
1051
1052 static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
1053 {
1054 /* set the irq handler which will finish the request when DMA is done */
1055 ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL);
1056
1057 /* issue cmd to drive */
1058 cris_ide_outb(command, IDE_COMMAND_REG);
1059 }
1060
1061 static void cris_dma_start(ide_drive_t *drive)
1062 {
1063 struct request *rq = drive->hwif->hwgroup->rq;
1064 int writing = rq_data_dir(rq);
1065 int type = TYPE_DMA;
1066
1067 if (drive->current_speed >= XFER_UDMA_0)
1068 type = TYPE_UDMA;
1069
1070 cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
1071
1072 if (writing) {
1073 LED_DISK_WRITE(1);
1074 } else {
1075 LED_DISK_READ(1);
1076 }
1077 }
kernel source for telekom puls (alcatel/mediatek)