drivers/i2c/busses/i2c-sh_mobile.c

   1 /*
   2  * SuperH Mobile I2C Controller
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  *
   6  * Portions of the code based on out-of-tree driver i2c-sh7343.c
   7  * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/i2c.h>
  30 #include <linux/err.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/clk.h>
  33 #include <linux/io.h>
  34
  35 /* Transmit operation:                                                      */
  36 /*                                                                          */
  37 /* 0 byte transmit                                                          */
  38 /* BUS:     S     A8     ACK   P                                            */
  39 /* IRQ:       DTE   WAIT                                                    */
  40 /* ICIC:                                                                    */
  41 /* ICCR: 0x94 0x90                                                          */
  42 /* ICDR:      A8                                                            */
  43 /*                                                                          */
  44 /* 1 byte transmit                                                          */
  45 /* BUS:     S     A8     ACK   D8(1)   ACK   P                              */
  46 /* IRQ:       DTE   WAIT         WAIT                                       */
  47 /* ICIC:      -DTE                                                          */
  48 /* ICCR: 0x94       0x90                                                    */
  49 /* ICDR:      A8    D8(1)                                                   */
  50 /*                                                                          */
  51 /* 2 byte transmit                                                          */
  52 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P                */
  53 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  54 /* ICIC:      -DTE                                                          */
  55 /* ICCR: 0x94                    0x90                                       */
  56 /* ICDR:      A8    D8(1)        D8(2)                                      */
  57 /*                                                                          */
  58 /* 3 bytes or more, +---------+ gets repeated                               */
  59 /*                                                                          */
  60 /*                                                                          */
  61 /* Receive operation:                                                       */
  62 /*                                                                          */
  63 /* 0 byte receive - not supported since slave may hold SDA low              */
  64 /*                                                                          */
  65 /* 1 byte receive       [TX] | [RX]                                         */
  66 /* BUS:     S     A8     ACK | D8(1)   ACK   P                              */
  67 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  68 /* ICIC:      -DTE           |   +DTE                                       */
  69 /* ICCR: 0x94       0x81     |   0xc0                                       */
  70 /* ICDR:      A8             |            D8(1)                             */
  71 /*                                                                          */
  72 /* 2 byte receive        [TX]| [RX]                                         */
  73 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P                */
  74 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  75 /* ICIC:      -DTE           |                 +DTE                         */
  76 /* ICCR: 0x94       0x81     |                 0xc0                         */
  77 /* ICDR:      A8             |                 D8(1)    D8(2)               */
  78 /*                                                                          */
  79 /* 3 byte receive       [TX] | [RX]                                         */
  80 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  81 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  82 /* ICIC:      -DTE           |                              +DTE            */
  83 /* ICCR: 0x94       0x81     |                              0xc0            */
  84 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  85 /*                                                                          */
  86 /* 4 bytes or more, this part is repeated    +---------+                    */
  87 /*                                                                          */
  88 /*                                                                          */
  89 /* Interrupt order and BUSY flag                                            */
  90 /*     ___                                                 _                */
  91 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  92 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  93 /*                                                                          */
  94 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P                 */
  95 /*                                           ___                            */
  96 /* WAIT IRQ ________________________________/   \___________                */
  97 /* TACK IRQ ____________________________________/   \_______                */
  98 /* DTE  IRQ __________________________________________/   \_                */
  99 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
 100 /*         _______________________________________________                  */
 101 /* BUSY __/                                               \_                */
 102 /*                                                                          */
 103
 104 enum sh_mobile_i2c_op {
 105         OP_START = 0,
 106         OP_TX_FIRST,
 107         OP_TX,
 108         OP_TX_STOP,
 109         OP_TX_TO_RX,
 110         OP_RX,
 111         OP_RX_STOP,
 112         OP_RX_STOP_DATA,
 113 };
 114
 115 struct sh_mobile_i2c_data {
 116         struct device *dev;
 117         void __iomem *reg;
 118         struct i2c_adapter adap;
 119
 120         struct clk *clk;
 121         u_int8_t iccl;
 122         u_int8_t icch;
 123
 124         spinlock_t lock;
 125         wait_queue_head_t wait;
 126         struct i2c_msg *msg;
 127         int pos;
 128         int sr;
 129 };
 130
 131 #define NORMAL_SPEED            100000 /* FAST_SPEED 400000 */
 132
 133 /* Register offsets */
 134 #define ICDR(pd)                (pd->reg + 0x00)
 135 #define ICCR(pd)                (pd->reg + 0x04)
 136 #define ICSR(pd)                (pd->reg + 0x08)
 137 #define ICIC(pd)                (pd->reg + 0x0c)
 138 #define ICCL(pd)                (pd->reg + 0x10)
 139 #define ICCH(pd)                (pd->reg + 0x14)
 140
 141 /* Register bits */
 142 #define ICCR_ICE                0x80
 143 #define ICCR_RACK               0x40
 144 #define ICCR_TRS                0x10
 145 #define ICCR_BBSY               0x04
 146 #define ICCR_SCP                0x01
 147
 148 #define ICSR_SCLM               0x80
 149 #define ICSR_SDAM               0x40
 150 #define SW_DONE                 0x20
 151 #define ICSR_BUSY               0x10
 152 #define ICSR_AL                 0x08
 153 #define ICSR_TACK               0x04
 154 #define ICSR_WAIT               0x02
 155 #define ICSR_DTE                0x01
 156
 157 #define ICIC_ALE                0x08
 158 #define ICIC_TACKE              0x04
 159 #define ICIC_WAITE              0x02
 160 #define ICIC_DTEE               0x01
 161
 162 static void activate_ch(struct sh_mobile_i2c_data *pd)
 163 {
 164         unsigned long i2c_clk;
 165         u_int32_t num;
 166         u_int32_t denom;
 167         u_int32_t tmp;
 168
 169         /* Wake up device and enable clock */
 170         pm_runtime_get_sync(pd->dev);
 171         clk_enable(pd->clk);
 172
 173         /* Get clock rate after clock is enabled */
 174         i2c_clk = clk_get_rate(pd->clk);
 175
 176         /* Calculate the value for iccl. From the data sheet:
 177          * iccl = (p clock / transfer rate) * (L / (L + H))
 178          * where L and H are the SCL low/high ratio (5/4 in this case).
 179          * We also round off the result.
 180          */
 181         num = i2c_clk * 5;
 182         denom = NORMAL_SPEED * 9;
 183         tmp = num * 10 / denom;
 184         if (tmp % 10 >= 5)
 185                 pd->iccl = (u_int8_t)((num/denom) + 1);
 186         else
 187                 pd->iccl = (u_int8_t)(num/denom);
 188
 189         /* Calculate the value for icch. From the data sheet:
 190            icch = (p clock / transfer rate) * (H / (L + H)) */
 191         num = i2c_clk * 4;
 192         tmp = num * 10 / denom;
 193         if (tmp % 10 >= 5)
 194                 pd->icch = (u_int8_t)((num/denom) + 1);
 195         else
 196                 pd->icch = (u_int8_t)(num/denom);
 197
 198         /* Enable channel and configure rx ack */
 199         iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
 200
 201         /* Mask all interrupts */
 202         iowrite8(0, ICIC(pd));
 203
 204         /* Set the clock */
 205         iowrite8(pd->iccl, ICCL(pd));
 206         iowrite8(pd->icch, ICCH(pd));
 207 }
 208
 209 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 210 {
 211         /* Clear/disable interrupts */
 212         iowrite8(0, ICSR(pd));
 213         iowrite8(0, ICIC(pd));
 214
 215         /* Disable channel */
 216         iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
 217
 218         /* Disable clock and mark device as idle */
 219         clk_disable(pd->clk);
 220         pm_runtime_put_sync(pd->dev);
 221 }
 222
 223 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 224                             enum sh_mobile_i2c_op op, unsigned char data)
 225 {
 226         unsigned char ret = 0;
 227         unsigned long flags;
 228
 229         dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
 230
 231         spin_lock_irqsave(&pd->lock, flags);
 232
 233         switch (op) {
 234         case OP_START: /* issue start and trigger DTE interrupt */
 235                 iowrite8(0x94, ICCR(pd));
 236                 break;
 237         case OP_TX_FIRST: /* disable DTE interrupt and write data */
 238                 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
 239                 iowrite8(data, ICDR(pd));
 240                 break;
 241         case OP_TX: /* write data */
 242                 iowrite8(data, ICDR(pd));
 243                 break;
 244         case OP_TX_STOP: /* write data and issue a stop afterwards */
 245                 iowrite8(data, ICDR(pd));
 246                 iowrite8(0x90, ICCR(pd));
 247                 break;
 248         case OP_TX_TO_RX: /* select read mode */
 249                 iowrite8(0x81, ICCR(pd));
 250                 break;
 251         case OP_RX: /* just read data */
 252                 ret = ioread8(ICDR(pd));
 253                 break;
 254         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 255                 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
 256                          ICIC(pd));
 257                 iowrite8(0xc0, ICCR(pd));
 258                 break;
 259         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 260                 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
 261                          ICIC(pd));
 262                 ret = ioread8(ICDR(pd));
 263                 iowrite8(0xc0, ICCR(pd));
 264                 break;
 265         }
 266
 267         spin_unlock_irqrestore(&pd->lock, flags);
 268
 269         dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 270         return ret;
 271 }
 272
 273 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
 274 {
 275         if (pd->pos == -1)
 276                 return 1;
 277
 278         return 0;
 279 }
 280
 281 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
 282 {
 283         if (pd->pos == (pd->msg->len - 1))
 284                 return 1;
 285
 286         return 0;
 287 }
 288
 289 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
 290                                    unsigned char *buf)
 291 {
 292         switch (pd->pos) {
 293         case -1:
 294                 *buf = (pd->msg->addr & 0x7f) << 1;
 295                 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
 296                 break;
 297         default:
 298                 *buf = pd->msg->buf[pd->pos];
 299         }
 300 }
 301
 302 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 303 {
 304         unsigned char data;
 305
 306         if (pd->pos == pd->msg->len)
 307                 return 1;
 308
 309         sh_mobile_i2c_get_data(pd, &data);
 310
 311         if (sh_mobile_i2c_is_last_byte(pd))
 312                 i2c_op(pd, OP_TX_STOP, data);
 313         else if (sh_mobile_i2c_is_first_byte(pd))
 314                 i2c_op(pd, OP_TX_FIRST, data);
 315         else
 316                 i2c_op(pd, OP_TX, data);
 317
 318         pd->pos++;
 319         return 0;
 320 }
 321
 322 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 323 {
 324         unsigned char data;
 325         int real_pos;
 326
 327         do {
 328                 if (pd->pos <= -1) {
 329                         sh_mobile_i2c_get_data(pd, &data);
 330
 331                         if (sh_mobile_i2c_is_first_byte(pd))
 332                                 i2c_op(pd, OP_TX_FIRST, data);
 333                         else
 334                                 i2c_op(pd, OP_TX, data);
 335                         break;
 336                 }
 337
 338                 if (pd->pos == 0) {
 339                         i2c_op(pd, OP_TX_TO_RX, 0);
 340                         break;
 341                 }
 342
 343                 real_pos = pd->pos - 2;
 344
 345                 if (pd->pos == pd->msg->len) {
 346                         if (real_pos < 0) {
 347                                 i2c_op(pd, OP_RX_STOP, 0);
 348                                 break;
 349                         }
 350                         data = i2c_op(pd, OP_RX_STOP_DATA, 0);
 351                 } else
 352                         data = i2c_op(pd, OP_RX, 0);
 353
 354                 if (real_pos >= 0)
 355                         pd->msg->buf[real_pos] = data;
 356         } while (0);
 357
 358         pd->pos++;
 359         return pd->pos == (pd->msg->len + 2);
 360 }
 361
 362 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 363 {
 364         struct platform_device *dev = dev_id;
 365         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 366         unsigned char sr;
 367         int wakeup;
 368
 369         sr = ioread8(ICSR(pd));
 370         pd->sr |= sr; /* remember state */
 371
 372         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 373                (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 374                pd->pos, pd->msg->len);
 375
 376         if (sr & (ICSR_AL | ICSR_TACK)) {
 377                 /* don't interrupt transaction - continue to issue stop */
 378                 iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
 379                 wakeup = 0;
 380         } else if (pd->msg->flags & I2C_M_RD)
 381                 wakeup = sh_mobile_i2c_isr_rx(pd);
 382         else
 383                 wakeup = sh_mobile_i2c_isr_tx(pd);
 384
 385         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 386                 iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
 387
 388         if (wakeup) {
 389                 pd->sr |= SW_DONE;
 390                 wake_up(&pd->wait);
 391         }
 392
 393         return IRQ_HANDLED;
 394 }
 395
 396 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
 397 {
 398         if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
 399                 dev_err(pd->dev, "Unsupported zero length i2c read\n");
 400                 return -EIO;
 401         }
 402
 403         /* Initialize channel registers */
 404         iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
 405
 406         /* Enable channel and configure rx ack */
 407         iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
 408
 409         /* Set the clock */
 410         iowrite8(pd->iccl, ICCL(pd));
 411         iowrite8(pd->icch, ICCH(pd));
 412
 413         pd->msg = usr_msg;
 414         pd->pos = -1;
 415         pd->sr = 0;
 416
 417         /* Enable all interrupts to begin with */
 418         iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
 419         return 0;
 420 }
 421
 422 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 423                               struct i2c_msg *msgs,
 424                               int num)
 425 {
 426         struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 427         struct i2c_msg  *msg;
 428         int err = 0;
 429         u_int8_t val;
 430         int i, k, retry_count;
 431
 432         activate_ch(pd);
 433
 434         /* Process all messages */
 435         for (i = 0; i < num; i++) {
 436                 msg = &msgs[i];
 437
 438                 err = start_ch(pd, msg);
 439                 if (err)
 440                         break;
 441
 442                 i2c_op(pd, OP_START, 0);
 443
 444                 /* The interrupt handler takes care of the rest... */
 445                 k = wait_event_timeout(pd->wait,
 446                                        pd->sr & (ICSR_TACK | SW_DONE),
 447                                        5 * HZ);
 448                 if (!k)
 449                         dev_err(pd->dev, "Transfer request timed out\n");
 450
 451                 retry_count = 1000;
 452 again:
 453                 val = ioread8(ICSR(pd));
 454
 455                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 456
 457                 /* the interrupt handler may wake us up before the
 458                  * transfer is finished, so poll the hardware
 459                  * until we're done.
 460                  */
 461                 if (val & ICSR_BUSY) {
 462                         udelay(10);
 463                         if (retry_count--)
 464                                 goto again;
 465
 466                         err = -EIO;
 467                         dev_err(pd->dev, "Polling timed out\n");
 468                         break;
 469                 }
 470
 471                 /* handle missing acknowledge and arbitration lost */
 472                 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
 473                         err = -EIO;
 474                         break;
 475                 }
 476         }
 477
 478         deactivate_ch(pd);
 479
 480         if (!err)
 481                 err = num;
 482         return err;
 483 }
 484
 485 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 486 {
 487         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 488 }
 489
 490 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
 491         .functionality  = sh_mobile_i2c_func,
 492         .master_xfer    = sh_mobile_i2c_xfer,
 493 };
 494
 495 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
 496 {
 497         struct resource *res;
 498         int ret = -ENXIO;
 499         int q, m;
 500         int k = 0;
 501         int n = 0;
 502
 503         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 504                 for (n = res->start; hook && n <= res->end; n++) {
 505                         if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
 506                                         dev_name(&dev->dev), dev))
 507                                 goto rollback;
 508                 }
 509                 k++;
 510         }
 511
 512         if (hook)
 513                 return k > 0 ? 0 : -ENOENT;
 514
 515         k--;
 516         ret = 0;
 517
 518  rollback:
 519         for (q = k; k >= 0; k--) {
 520                 for (m = n; m >= res->start; m--)
 521                         free_irq(m, dev);
 522
 523                 res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1);
 524                 m = res->end;
 525         }
 526
 527         return ret;
 528 }
 529
 530 static int sh_mobile_i2c_probe(struct platform_device *dev)
 531 {
 532         struct sh_mobile_i2c_data *pd;
 533         struct i2c_adapter *adap;
 534         struct resource *res;
 535         char clk_name[8];
 536         int size;
 537         int ret;
 538
 539         pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 540         if (pd == NULL) {
 541                 dev_err(&dev->dev, "cannot allocate private data\n");
 542                 return -ENOMEM;
 543         }
 544
 545         snprintf(clk_name, sizeof(clk_name), "i2c%d", dev->id);
 546         pd->clk = clk_get(&dev->dev, clk_name);
 547         if (IS_ERR(pd->clk)) {
 548                 dev_err(&dev->dev, "cannot get clock \"%s\"\n", clk_name);
 549                 ret = PTR_ERR(pd->clk);
 550                 goto err;
 551         }
 552
 553         ret = sh_mobile_i2c_hook_irqs(dev, 1);
 554         if (ret) {
 555                 dev_err(&dev->dev, "cannot request IRQ\n");
 556                 goto err_clk;
 557         }
 558
 559         pd->dev = &dev->dev;
 560         platform_set_drvdata(dev, pd);
 561
 562         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 563         if (res == NULL) {
 564                 dev_err(&dev->dev, "cannot find IO resource\n");
 565                 ret = -ENOENT;
 566                 goto err_irq;
 567         }
 568
 569         size = resource_size(res);
 570
 571         pd->reg = ioremap(res->start, size);
 572         if (pd->reg == NULL) {
 573                 dev_err(&dev->dev, "cannot map IO\n");
 574                 ret = -ENXIO;
 575                 goto err_irq;
 576         }
 577
 578         /* Enable Runtime PM for this device.
 579          *
 580          * Also tell the Runtime PM core to ignore children
 581          * for this device since it is valid for us to suspend
 582          * this I2C master driver even though the slave devices
 583          * on the I2C bus may not be suspended.
 584          *
 585          * The state of the I2C hardware bus is unaffected by
 586          * the Runtime PM state.
 587          */
 588         pm_suspend_ignore_children(&dev->dev, true);
 589         pm_runtime_enable(&dev->dev);
 590
 591         /* setup the private data */
 592         adap = &pd->adap;
 593         i2c_set_adapdata(adap, pd);
 594
 595         adap->owner = THIS_MODULE;
 596         adap->algo = &sh_mobile_i2c_algorithm;
 597         adap->dev.parent = &dev->dev;
 598         adap->retries = 5;
 599         adap->nr = dev->id;
 600
 601         strlcpy(adap->name, dev->name, sizeof(adap->name));
 602
 603         spin_lock_init(&pd->lock);
 604         init_waitqueue_head(&pd->wait);
 605
 606         ret = i2c_add_numbered_adapter(adap);
 607         if (ret < 0) {
 608                 dev_err(&dev->dev, "cannot add numbered adapter\n");
 609                 goto err_all;
 610         }
 611
 612         return 0;
 613
 614  err_all:
 615         iounmap(pd->reg);
 616  err_irq:
 617         sh_mobile_i2c_hook_irqs(dev, 0);
 618  err_clk:
 619         clk_put(pd->clk);
 620  err:
 621         kfree(pd);
 622         return ret;
 623 }
 624
 625 static int sh_mobile_i2c_remove(struct platform_device *dev)
 626 {
 627         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 628
 629         i2c_del_adapter(&pd->adap);
 630         iounmap(pd->reg);
 631         sh_mobile_i2c_hook_irqs(dev, 0);
 632         clk_put(pd->clk);
 633         pm_runtime_disable(&dev->dev);
 634         kfree(pd);
 635         return 0;
 636 }
 637
 638 static int sh_mobile_i2c_runtime_nop(struct device *dev)
 639 {
 640         /* Runtime PM callback shared between ->runtime_suspend()
 641          * and ->runtime_resume(). Simply returns success.
 642          *
 643          * This driver re-initializes all registers after
 644          * pm_runtime_get_sync() anyway so there is no need
 645          * to save and restore registers here.
 646          */
 647         return 0;
 648 }
 649
 650 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
 651         .runtime_suspend = sh_mobile_i2c_runtime_nop,
 652         .runtime_resume = sh_mobile_i2c_runtime_nop,
 653 };
 654
 655 static struct platform_driver sh_mobile_i2c_driver = {
 656         .driver         = {
 657                 .name           = "i2c-sh_mobile",
 658                 .owner          = THIS_MODULE,
 659                 .pm             = &sh_mobile_i2c_dev_pm_ops,
 660         },
 661         .probe          = sh_mobile_i2c_probe,
 662         .remove         = sh_mobile_i2c_remove,
 663 };
 664
 665 static int __init sh_mobile_i2c_adap_init(void)
 666 {
 667         return platform_driver_register(&sh_mobile_i2c_driver);
 668 }
 669
 670 static void __exit sh_mobile_i2c_adap_exit(void)
 671 {
 672         platform_driver_unregister(&sh_mobile_i2c_driver);
 673 }
 674
 675 subsys_initcall(sh_mobile_i2c_adap_init);
 676 module_exit(sh_mobile_i2c_adap_exit);
 677
 678 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
 679 MODULE_AUTHOR("Magnus Damm");
 680 MODULE_LICENSE("GPL v2");