2 * This file is provided under a dual BSD/GPLv2 license. When using or
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54 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
55 * S12xx Product Family.
57 * Features supported by this driver:
60 * Block process call transaction no
64 #include <linux/module.h>
65 #include <linux/init.h>
66 #include <linux/pci.h>
67 #include <linux/kernel.h>
68 #include <linux/stddef.h>
69 #include <linux/completion.h>
70 #include <linux/dma-mapping.h>
71 #include <linux/i2c.h>
72 #include <linux/acpi.h>
73 #include <linux/interrupt.h>
75 #include <asm-generic/io-64-nonatomic-lo-hi.h>
77 /* PCI Address Constants */
80 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
81 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
82 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
83 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
85 #define ISMT_DESC_ENTRIES 32 /* number of descriptor entries */
86 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
88 /* Hardware Descriptor Constants - Control Field */
89 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
90 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
91 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
92 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
93 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
94 #define ISMT_DESC_INT 0x40 /* Interrupt */
95 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
97 /* Hardware Descriptor Constants - Status Field */
98 #define ISMT_DESC_SCS 0x01 /* Success */
99 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
100 #define ISMT_DESC_NAK 0x08 /* NAK Received */
101 #define ISMT_DESC_CRC 0x10 /* CRC Error */
102 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
103 #define ISMT_DESC_COL 0x40 /* Collisions */
104 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
107 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
109 /* iSMT General Register address offsets (SMBBAR + <addr>) */
110 #define ISMT_GR_GCTRL 0x000 /* General Control */
111 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
112 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
113 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
114 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
115 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
117 /* iSMT Master Registers */
118 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
119 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
120 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
121 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
122 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
124 /* iSMT Miscellaneous Registers */
125 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
127 /* General Control Register (GCTRL) bit definitions */
128 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
129 #define ISMT_GCTRL_KILL 0x08 /* Kill */
130 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
132 /* Master Control Register (MCTRL) bit definitions */
133 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
134 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
135 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
137 /* Master Status Register (MSTS) bit definitions */
138 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
139 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
140 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
141 #define ISMT_MSTS_IP 0x01 /* In Progress */
143 /* Master Descriptor Size (MDS) bit definitions */
144 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
146 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
147 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
148 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
149 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
150 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
151 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
154 /* MSI Control Register (MSICTL) bit definitions */
155 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
157 /* iSMT Hardware Descriptor */
159 u8 tgtaddr_rw
; /* target address & r/w bit */
160 u8 wr_len_cmd
; /* write length in bytes or a command */
161 u8 rd_len
; /* read length */
162 u8 control
; /* control bits */
163 u8 status
; /* status bits */
164 u8 retry
; /* collision retry and retry count */
165 u8 rxbytes
; /* received bytes */
166 u8 txbytes
; /* transmitted bytes */
167 u32 dptr_low
; /* lower 32 bit of the data pointer */
168 u32 dptr_high
; /* upper 32 bit of the data pointer */
172 struct i2c_adapter adapter
;
173 void *smba
; /* PCI BAR */
174 struct pci_dev
*pci_dev
;
175 struct ismt_desc
*hw
; /* descriptor virt base addr */
176 dma_addr_t io_rng_dma
; /* descriptor HW base addr */
177 u8 head
; /* ring buffer head pointer */
178 struct completion cmp
; /* interrupt completion */
179 u8 dma_buffer
[I2C_SMBUS_BLOCK_MAX
+ 1]; /* temp R/W data buffer */
180 bool using_msi
; /* type of interrupt flag */
184 * ismt_ids - PCI device IDs supported by this driver
186 static const DEFINE_PCI_DEVICE_TABLE(ismt_ids
) = {
187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_S1200_SMT0
) },
188 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_S1200_SMT1
) },
189 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_AVOTON_SMT
) },
193 MODULE_DEVICE_TABLE(pci
, ismt_ids
);
195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
196 static unsigned int bus_speed
;
197 module_param(bus_speed
, uint
, S_IRUGO
);
198 MODULE_PARM_DESC(bus_speed
, "Bus Speed in kHz (0 = BIOS default)");
201 * __ismt_desc_dump() - dump the contents of a specific descriptor
203 static void __ismt_desc_dump(struct device
*dev
, const struct ismt_desc
*desc
)
206 dev_dbg(dev
, "Descriptor struct: %p\n", desc
);
207 dev_dbg(dev
, "\ttgtaddr_rw=0x%02X\n", desc
->tgtaddr_rw
);
208 dev_dbg(dev
, "\twr_len_cmd=0x%02X\n", desc
->wr_len_cmd
);
209 dev_dbg(dev
, "\trd_len= 0x%02X\n", desc
->rd_len
);
210 dev_dbg(dev
, "\tcontrol= 0x%02X\n", desc
->control
);
211 dev_dbg(dev
, "\tstatus= 0x%02X\n", desc
->status
);
212 dev_dbg(dev
, "\tretry= 0x%02X\n", desc
->retry
);
213 dev_dbg(dev
, "\trxbytes= 0x%02X\n", desc
->rxbytes
);
214 dev_dbg(dev
, "\ttxbytes= 0x%02X\n", desc
->txbytes
);
215 dev_dbg(dev
, "\tdptr_low= 0x%08X\n", desc
->dptr_low
);
216 dev_dbg(dev
, "\tdptr_high= 0x%08X\n", desc
->dptr_high
);
219 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
220 * @priv: iSMT private data
222 static void ismt_desc_dump(struct ismt_priv
*priv
)
224 struct device
*dev
= &priv
->pci_dev
->dev
;
225 struct ismt_desc
*desc
= &priv
->hw
[priv
->head
];
227 dev_dbg(dev
, "Dump of the descriptor struct: 0x%X\n", priv
->head
);
228 __ismt_desc_dump(dev
, desc
);
232 * ismt_gen_reg_dump() - dump the iSMT General Registers
233 * @priv: iSMT private data
235 static void ismt_gen_reg_dump(struct ismt_priv
*priv
)
237 struct device
*dev
= &priv
->pci_dev
->dev
;
239 dev_dbg(dev
, "Dump of the iSMT General Registers\n");
240 dev_dbg(dev
, " GCTRL.... : (0x%p)=0x%X\n",
241 priv
->smba
+ ISMT_GR_GCTRL
,
242 readl(priv
->smba
+ ISMT_GR_GCTRL
));
243 dev_dbg(dev
, " SMTICL... : (0x%p)=0x%016llX\n",
244 priv
->smba
+ ISMT_GR_SMTICL
,
245 (long long unsigned int)readq(priv
->smba
+ ISMT_GR_SMTICL
));
246 dev_dbg(dev
, " ERRINTMSK : (0x%p)=0x%X\n",
247 priv
->smba
+ ISMT_GR_ERRINTMSK
,
248 readl(priv
->smba
+ ISMT_GR_ERRINTMSK
));
249 dev_dbg(dev
, " ERRAERMSK : (0x%p)=0x%X\n",
250 priv
->smba
+ ISMT_GR_ERRAERMSK
,
251 readl(priv
->smba
+ ISMT_GR_ERRAERMSK
));
252 dev_dbg(dev
, " ERRSTS... : (0x%p)=0x%X\n",
253 priv
->smba
+ ISMT_GR_ERRSTS
,
254 readl(priv
->smba
+ ISMT_GR_ERRSTS
));
255 dev_dbg(dev
, " ERRINFO.. : (0x%p)=0x%X\n",
256 priv
->smba
+ ISMT_GR_ERRINFO
,
257 readl(priv
->smba
+ ISMT_GR_ERRINFO
));
261 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
262 * @priv: iSMT private data
264 static void ismt_mstr_reg_dump(struct ismt_priv
*priv
)
266 struct device
*dev
= &priv
->pci_dev
->dev
;
268 dev_dbg(dev
, "Dump of the iSMT Master Registers\n");
269 dev_dbg(dev
, " MDBA..... : (0x%p)=0x%016llX\n",
270 priv
->smba
+ ISMT_MSTR_MDBA
,
271 (long long unsigned int)readq(priv
->smba
+ ISMT_MSTR_MDBA
));
272 dev_dbg(dev
, " MCTRL.... : (0x%p)=0x%X\n",
273 priv
->smba
+ ISMT_MSTR_MCTRL
,
274 readl(priv
->smba
+ ISMT_MSTR_MCTRL
));
275 dev_dbg(dev
, " MSTS..... : (0x%p)=0x%X\n",
276 priv
->smba
+ ISMT_MSTR_MSTS
,
277 readl(priv
->smba
+ ISMT_MSTR_MSTS
));
278 dev_dbg(dev
, " MDS...... : (0x%p)=0x%X\n",
279 priv
->smba
+ ISMT_MSTR_MDS
,
280 readl(priv
->smba
+ ISMT_MSTR_MDS
));
281 dev_dbg(dev
, " RPOLICY.. : (0x%p)=0x%X\n",
282 priv
->smba
+ ISMT_MSTR_RPOLICY
,
283 readl(priv
->smba
+ ISMT_MSTR_RPOLICY
));
284 dev_dbg(dev
, " SPGT..... : (0x%p)=0x%X\n",
285 priv
->smba
+ ISMT_SPGT
,
286 readl(priv
->smba
+ ISMT_SPGT
));
290 * ismt_submit_desc() - add a descriptor to the ring
291 * @priv: iSMT private data
293 static void ismt_submit_desc(struct ismt_priv
*priv
)
298 ismt_desc_dump(priv
);
299 ismt_gen_reg_dump(priv
);
300 ismt_mstr_reg_dump(priv
);
302 /* Set the FMHP (Firmware Master Head Pointer)*/
303 fmhp
= ((priv
->head
+ 1) % ISMT_DESC_ENTRIES
) << 16;
304 val
= readl(priv
->smba
+ ISMT_MSTR_MCTRL
);
305 writel((val
& ~ISMT_MCTRL_FMHP
) | fmhp
,
306 priv
->smba
+ ISMT_MSTR_MCTRL
);
308 /* Set the start bit */
309 val
= readl(priv
->smba
+ ISMT_MSTR_MCTRL
);
310 writel(val
| ISMT_MCTRL_SS
,
311 priv
->smba
+ ISMT_MSTR_MCTRL
);
315 * ismt_process_desc() - handle the completion of the descriptor
316 * @desc: the iSMT hardware descriptor
317 * @data: data buffer from the upper layer
318 * @priv: ismt_priv struct holding our dma buffer
319 * @size: SMBus transaction type
320 * @read_write: flag to indicate if this is a read or write
322 static int ismt_process_desc(const struct ismt_desc
*desc
,
323 union i2c_smbus_data
*data
,
324 struct ismt_priv
*priv
, int size
,
327 u8
*dma_buffer
= priv
->dma_buffer
;
329 dev_dbg(&priv
->pci_dev
->dev
, "Processing completed descriptor\n");
330 __ismt_desc_dump(&priv
->pci_dev
->dev
, desc
);
332 if (desc
->status
& ISMT_DESC_SCS
) {
333 if (read_write
== I2C_SMBUS_WRITE
&&
334 size
!= I2C_SMBUS_PROC_CALL
)
339 case I2C_SMBUS_BYTE_DATA
:
340 data
->byte
= dma_buffer
[0];
342 case I2C_SMBUS_WORD_DATA
:
343 case I2C_SMBUS_PROC_CALL
:
344 data
->word
= dma_buffer
[0] | (dma_buffer
[1] << 8);
346 case I2C_SMBUS_BLOCK_DATA
:
347 memcpy(&data
->block
[1], dma_buffer
, desc
->rxbytes
);
348 data
->block
[0] = desc
->rxbytes
;
354 if (likely(desc
->status
& ISMT_DESC_NAK
))
357 if (desc
->status
& ISMT_DESC_CRC
)
360 if (desc
->status
& ISMT_DESC_COL
)
363 if (desc
->status
& ISMT_DESC_LPR
)
366 if (desc
->status
& (ISMT_DESC_DLTO
| ISMT_DESC_CLTO
))
373 * ismt_access() - process an SMBus command
374 * @adap: the i2c host adapter
375 * @addr: address of the i2c/SMBus target
376 * @flags: command options
377 * @read_write: read from or write to device
378 * @command: the i2c/SMBus command to issue
379 * @size: SMBus transaction type
380 * @data: read/write data buffer
382 static int ismt_access(struct i2c_adapter
*adap
, u16 addr
,
383 unsigned short flags
, char read_write
, u8 command
,
384 int size
, union i2c_smbus_data
*data
)
387 dma_addr_t dma_addr
= 0; /* address of the data buffer */
389 enum dma_data_direction dma_direction
= 0;
390 struct ismt_desc
*desc
;
391 struct ismt_priv
*priv
= i2c_get_adapdata(adap
);
392 struct device
*dev
= &priv
->pci_dev
->dev
;
394 desc
= &priv
->hw
[priv
->head
];
396 /* Initialize the descriptor */
397 memset(desc
, 0, sizeof(struct ismt_desc
));
398 desc
->tgtaddr_rw
= ISMT_DESC_ADDR_RW(addr
, read_write
);
400 /* Initialize common control bits */
401 if (likely(priv
->using_msi
))
402 desc
->control
= ISMT_DESC_INT
| ISMT_DESC_FAIR
;
404 desc
->control
= ISMT_DESC_FAIR
;
406 if ((flags
& I2C_CLIENT_PEC
) && (size
!= I2C_SMBUS_QUICK
)
407 && (size
!= I2C_SMBUS_I2C_BLOCK_DATA
))
408 desc
->control
|= ISMT_DESC_PEC
;
411 case I2C_SMBUS_QUICK
:
412 dev_dbg(dev
, "I2C_SMBUS_QUICK\n");
416 if (read_write
== I2C_SMBUS_WRITE
) {
419 * The command field contains the write data
421 dev_dbg(dev
, "I2C_SMBUS_BYTE: WRITE\n");
422 desc
->control
|= ISMT_DESC_CWRL
;
423 desc
->wr_len_cmd
= command
;
426 dev_dbg(dev
, "I2C_SMBUS_BYTE: READ\n");
428 dma_direction
= DMA_FROM_DEVICE
;
433 case I2C_SMBUS_BYTE_DATA
:
434 if (read_write
== I2C_SMBUS_WRITE
) {
437 * Command plus 1 data byte
439 dev_dbg(dev
, "I2C_SMBUS_BYTE_DATA: WRITE\n");
440 desc
->wr_len_cmd
= 2;
442 dma_direction
= DMA_TO_DEVICE
;
443 priv
->dma_buffer
[0] = command
;
444 priv
->dma_buffer
[1] = data
->byte
;
447 dev_dbg(dev
, "I2C_SMBUS_BYTE_DATA: READ\n");
448 desc
->control
|= ISMT_DESC_CWRL
;
449 desc
->wr_len_cmd
= command
;
452 dma_direction
= DMA_FROM_DEVICE
;
456 case I2C_SMBUS_WORD_DATA
:
457 if (read_write
== I2C_SMBUS_WRITE
) {
459 dev_dbg(dev
, "I2C_SMBUS_WORD_DATA: WRITE\n");
460 desc
->wr_len_cmd
= 3;
462 dma_direction
= DMA_TO_DEVICE
;
463 priv
->dma_buffer
[0] = command
;
464 priv
->dma_buffer
[1] = data
->word
& 0xff;
465 priv
->dma_buffer
[2] = data
->word
>> 8;
468 dev_dbg(dev
, "I2C_SMBUS_WORD_DATA: READ\n");
469 desc
->wr_len_cmd
= command
;
470 desc
->control
|= ISMT_DESC_CWRL
;
473 dma_direction
= DMA_FROM_DEVICE
;
477 case I2C_SMBUS_PROC_CALL
:
478 dev_dbg(dev
, "I2C_SMBUS_PROC_CALL\n");
479 desc
->wr_len_cmd
= 3;
482 dma_direction
= DMA_BIDIRECTIONAL
;
483 priv
->dma_buffer
[0] = command
;
484 priv
->dma_buffer
[1] = data
->word
& 0xff;
485 priv
->dma_buffer
[2] = data
->word
>> 8;
488 case I2C_SMBUS_BLOCK_DATA
:
489 if (read_write
== I2C_SMBUS_WRITE
) {
491 dev_dbg(dev
, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
492 dma_size
= data
->block
[0] + 1;
493 dma_direction
= DMA_TO_DEVICE
;
494 desc
->wr_len_cmd
= dma_size
;
495 desc
->control
|= ISMT_DESC_BLK
;
496 priv
->dma_buffer
[0] = command
;
497 memcpy(&priv
->dma_buffer
[1], &data
->block
[1], dma_size
);
500 dev_dbg(dev
, "I2C_SMBUS_BLOCK_DATA: READ\n");
501 dma_size
= I2C_SMBUS_BLOCK_MAX
;
502 dma_direction
= DMA_FROM_DEVICE
;
503 desc
->rd_len
= dma_size
;
504 desc
->wr_len_cmd
= command
;
505 desc
->control
|= (ISMT_DESC_BLK
| ISMT_DESC_CWRL
);
510 dev_err(dev
, "Unsupported transaction %d\n",
515 /* map the data buffer */
517 dev_dbg(dev
, " dev=%p\n", dev
);
518 dev_dbg(dev
, " data=%p\n", data
);
519 dev_dbg(dev
, " dma_buffer=%p\n", priv
->dma_buffer
);
520 dev_dbg(dev
, " dma_size=%d\n", dma_size
);
521 dev_dbg(dev
, " dma_direction=%d\n", dma_direction
);
523 dma_addr
= dma_map_single(dev
,
528 if (dma_mapping_error(dev
, dma_addr
)) {
529 dev_err(dev
, "Error in mapping dma buffer %p\n",
534 dev_dbg(dev
, " dma_addr = 0x%016llX\n",
535 (unsigned long long)dma_addr
);
537 desc
->dptr_low
= lower_32_bits(dma_addr
);
538 desc
->dptr_high
= upper_32_bits(dma_addr
);
541 INIT_COMPLETION(priv
->cmp
);
543 /* Add the descriptor */
544 ismt_submit_desc(priv
);
546 /* Now we wait for interrupt completion, 1s */
547 ret
= wait_for_completion_timeout(&priv
->cmp
, HZ
*1);
549 /* unmap the data buffer */
551 dma_unmap_single(&adap
->dev
, dma_addr
, dma_size
, dma_direction
);
553 if (unlikely(!ret
)) {
554 dev_err(dev
, "completion wait timed out\n");
559 /* do any post processing of the descriptor here */
560 ret
= ismt_process_desc(desc
, data
, priv
, size
, read_write
);
563 /* Update the ring pointer */
565 priv
->head
%= ISMT_DESC_ENTRIES
;
571 * ismt_func() - report which i2c commands are supported by this adapter
572 * @adap: the i2c host adapter
574 static u32
ismt_func(struct i2c_adapter
*adap
)
576 return I2C_FUNC_SMBUS_QUICK
|
577 I2C_FUNC_SMBUS_BYTE
|
578 I2C_FUNC_SMBUS_BYTE_DATA
|
579 I2C_FUNC_SMBUS_WORD_DATA
|
580 I2C_FUNC_SMBUS_PROC_CALL
|
581 I2C_FUNC_SMBUS_BLOCK_DATA
|
586 * smbus_algorithm - the adapter algorithm and supported functionality
587 * @smbus_xfer: the adapter algorithm
588 * @functionality: functionality supported by the adapter
590 static const struct i2c_algorithm smbus_algorithm
= {
591 .smbus_xfer
= ismt_access
,
592 .functionality
= ismt_func
,
596 * ismt_handle_isr() - interrupt handler bottom half
597 * @priv: iSMT private data
599 static irqreturn_t
ismt_handle_isr(struct ismt_priv
*priv
)
601 complete(&priv
->cmp
);
608 * ismt_do_interrupt() - IRQ interrupt handler
609 * @vec: interrupt vector
610 * @data: iSMT private data
612 static irqreturn_t
ismt_do_interrupt(int vec
, void *data
)
615 struct ismt_priv
*priv
= data
;
618 * check to see it's our interrupt, return IRQ_NONE if not ours
619 * since we are sharing interrupt
621 val
= readl(priv
->smba
+ ISMT_MSTR_MSTS
);
623 if (!(val
& (ISMT_MSTS_MIS
| ISMT_MSTS_MEIS
)))
626 writel(val
| ISMT_MSTS_MIS
| ISMT_MSTS_MEIS
,
627 priv
->smba
+ ISMT_MSTR_MSTS
);
629 return ismt_handle_isr(priv
);
633 * ismt_do_msi_interrupt() - MSI interrupt handler
634 * @vec: interrupt vector
635 * @data: iSMT private data
637 static irqreturn_t
ismt_do_msi_interrupt(int vec
, void *data
)
639 return ismt_handle_isr(data
);
643 * ismt_hw_init() - initialize the iSMT hardware
644 * @priv: iSMT private data
646 static void ismt_hw_init(struct ismt_priv
*priv
)
649 struct device
*dev
= &priv
->pci_dev
->dev
;
651 /* initialize the Master Descriptor Base Address (MDBA) */
652 writeq(priv
->io_rng_dma
, priv
->smba
+ ISMT_MSTR_MDBA
);
654 /* initialize the Master Control Register (MCTRL) */
655 writel(ISMT_MCTRL_MEIE
, priv
->smba
+ ISMT_MSTR_MCTRL
);
657 /* initialize the Master Status Register (MSTS) */
658 writel(0, priv
->smba
+ ISMT_MSTR_MSTS
);
660 /* initialize the Master Descriptor Size (MDS) */
661 val
= readl(priv
->smba
+ ISMT_MSTR_MDS
);
662 writel((val
& ~ISMT_MDS_MASK
) | (ISMT_DESC_ENTRIES
- 1),
663 priv
->smba
+ ISMT_MSTR_MDS
);
666 * Set the SMBus speed (could use this for slow HW debuggers)
669 val
= readl(priv
->smba
+ ISMT_SPGT
);
676 dev_dbg(dev
, "Setting SMBus clock to 80 kHz\n");
677 writel(((val
& ~ISMT_SPGT_SPD_MASK
) | ISMT_SPGT_SPD_80K
),
678 priv
->smba
+ ISMT_SPGT
);
682 dev_dbg(dev
, "Setting SMBus clock to 100 kHz\n");
683 writel(((val
& ~ISMT_SPGT_SPD_MASK
) | ISMT_SPGT_SPD_100K
),
684 priv
->smba
+ ISMT_SPGT
);
688 dev_dbg(dev
, "Setting SMBus clock to 400 kHz\n");
689 writel(((val
& ~ISMT_SPGT_SPD_MASK
) | ISMT_SPGT_SPD_400K
),
690 priv
->smba
+ ISMT_SPGT
);
694 dev_dbg(dev
, "Setting SMBus clock to 1000 kHz\n");
695 writel(((val
& ~ISMT_SPGT_SPD_MASK
) | ISMT_SPGT_SPD_1M
),
696 priv
->smba
+ ISMT_SPGT
);
700 dev_warn(dev
, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
704 val
= readl(priv
->smba
+ ISMT_SPGT
);
706 switch (val
& ISMT_SPGT_SPD_MASK
) {
707 case ISMT_SPGT_SPD_80K
:
710 case ISMT_SPGT_SPD_100K
:
713 case ISMT_SPGT_SPD_400K
:
716 case ISMT_SPGT_SPD_1M
:
720 dev_dbg(dev
, "SMBus clock is running at %d kHz\n", bus_speed
);
724 * ismt_dev_init() - initialize the iSMT data structures
725 * @priv: iSMT private data
727 static int ismt_dev_init(struct ismt_priv
*priv
)
729 /* allocate memory for the descriptor */
730 priv
->hw
= dmam_alloc_coherent(&priv
->pci_dev
->dev
,
732 * sizeof(struct ismt_desc
)),
738 memset(priv
->hw
, 0, (ISMT_DESC_ENTRIES
* sizeof(struct ismt_desc
)));
741 init_completion(&priv
->cmp
);
747 * ismt_int_init() - initialize interrupts
748 * @priv: iSMT private data
750 static int ismt_int_init(struct ismt_priv
*priv
)
754 /* Try using MSI interrupts */
755 err
= pci_enable_msi(priv
->pci_dev
);
757 dev_warn(&priv
->pci_dev
->dev
,
758 "Unable to use MSI interrupts, falling back to legacy\n");
762 err
= devm_request_irq(&priv
->pci_dev
->dev
,
764 ismt_do_msi_interrupt
,
769 pci_disable_msi(priv
->pci_dev
);
773 priv
->using_msi
= true;
776 /* Try using legacy interrupts */
778 err
= devm_request_irq(&priv
->pci_dev
->dev
,
785 dev_err(&priv
->pci_dev
->dev
, "no usable interrupts\n");
789 priv
->using_msi
= false;
795 static struct pci_driver ismt_driver
;
798 * ismt_probe() - probe for iSMT devices
799 * @pdev: PCI-Express device
800 * @id: PCI-Express device ID
803 ismt_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
806 struct ismt_priv
*priv
;
807 unsigned long start
, len
;
809 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
813 pci_set_drvdata(pdev
, priv
);
814 i2c_set_adapdata(&priv
->adapter
, priv
);
815 priv
->adapter
.owner
= THIS_MODULE
;
817 priv
->adapter
.class = I2C_CLASS_HWMON
;
819 priv
->adapter
.algo
= &smbus_algorithm
;
821 /* set up the sysfs linkage to our parent device */
822 priv
->adapter
.dev
.parent
= &pdev
->dev
;
824 /* number of retries on lost arbitration */
825 priv
->adapter
.retries
= ISMT_MAX_RETRIES
;
827 priv
->pci_dev
= pdev
;
829 err
= pcim_enable_device(pdev
);
831 dev_err(&pdev
->dev
, "Failed to enable SMBus PCI device (%d)\n",
836 /* enable bus mastering */
837 pci_set_master(pdev
);
839 /* Determine the address of the SMBus area */
840 start
= pci_resource_start(pdev
, SMBBAR
);
841 len
= pci_resource_len(pdev
, SMBBAR
);
842 if (!start
|| !len
) {
844 "SMBus base address uninitialized, upgrade BIOS\n");
848 snprintf(priv
->adapter
.name
, sizeof(priv
->adapter
.name
),
849 "SMBus iSMT adapter at %lx", start
);
851 dev_dbg(&priv
->pci_dev
->dev
, " start=0x%lX\n", start
);
852 dev_dbg(&priv
->pci_dev
->dev
, " len=0x%lX\n", len
);
854 err
= acpi_check_resource_conflict(&pdev
->resource
[SMBBAR
]);
856 dev_err(&pdev
->dev
, "ACPI resource conflict!\n");
860 err
= pci_request_region(pdev
, SMBBAR
, ismt_driver
.name
);
863 "Failed to request SMBus region 0x%lx-0x%lx\n",
868 priv
->smba
= pcim_iomap(pdev
, SMBBAR
, len
);
870 dev_err(&pdev
->dev
, "Unable to ioremap SMBus BAR\n");
875 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0) ||
876 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0)) {
877 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0) ||
878 (pci_set_consistent_dma_mask(pdev
,
879 DMA_BIT_MASK(32)) != 0)) {
880 dev_err(&pdev
->dev
, "pci_set_dma_mask fail %p\n",
886 err
= ismt_dev_init(priv
);
892 err
= ismt_int_init(priv
);
896 err
= i2c_add_adapter(&priv
->adapter
);
898 dev_err(&pdev
->dev
, "Failed to add SMBus iSMT adapter\n");
905 pci_release_region(pdev
, SMBBAR
);
910 * ismt_remove() - release driver resources
911 * @pdev: PCI-Express device
913 static void ismt_remove(struct pci_dev
*pdev
)
915 struct ismt_priv
*priv
= pci_get_drvdata(pdev
);
917 i2c_del_adapter(&priv
->adapter
);
918 pci_release_region(pdev
, SMBBAR
);
922 * ismt_suspend() - place the device in suspend
923 * @pdev: PCI-Express device
927 static int ismt_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
929 pci_save_state(pdev
);
930 pci_set_power_state(pdev
, pci_choose_state(pdev
, mesg
));
935 * ismt_resume() - PCI resume code
936 * @pdev: PCI-Express device
938 static int ismt_resume(struct pci_dev
*pdev
)
940 pci_set_power_state(pdev
, PCI_D0
);
941 pci_restore_state(pdev
);
942 return pci_enable_device(pdev
);
947 #define ismt_suspend NULL
948 #define ismt_resume NULL
952 static struct pci_driver ismt_driver
= {
953 .name
= "ismt_smbus",
954 .id_table
= ismt_ids
,
956 .remove
= ismt_remove
,
957 .suspend
= ismt_suspend
,
958 .resume
= ismt_resume
,
961 module_pci_driver(ismt_driver
);
963 MODULE_LICENSE("Dual BSD/GPL");
964 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
965 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");