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Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 Avoton (SOC) 0x1f3c 32 hard yes yes yes
57 Wellsburg (PCH) 0x8d22 32 hard yes yes yes
58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61
62 Features supported by this driver:
63 Software PEC no
64 Hardware PEC yes
65 Block buffer yes
66 Block process call transaction no
67 I2C block read transaction yes (doesn't use the block buffer)
68 Slave mode no
69 Interrupt processing yes
70
71 See the file Documentation/i2c/busses/i2c-i801 for details.
72 */
73
74 #include <linux/interrupt.h>
75 #include <linux/module.h>
76 #include <linux/pci.h>
77 #include <linux/kernel.h>
78 #include <linux/stddef.h>
79 #include <linux/delay.h>
80 #include <linux/ioport.h>
81 #include <linux/init.h>
82 #include <linux/i2c.h>
83 #include <linux/acpi.h>
84 #include <linux/io.h>
85 #include <linux/dmi.h>
86 #include <linux/slab.h>
87 #include <linux/wait.h>
88 #include <linux/err.h>
89 #include <linux/of_i2c.h>
90
91 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
92 defined CONFIG_DMI
93 #include <linux/gpio.h>
94 #include <linux/i2c-mux-gpio.h>
95 #include <linux/platform_device.h>
96 #endif
97
98 /* I801 SMBus address offsets */
99 #define SMBHSTSTS(p) (0 + (p)->smba)
100 #define SMBHSTCNT(p) (2 + (p)->smba)
101 #define SMBHSTCMD(p) (3 + (p)->smba)
102 #define SMBHSTADD(p) (4 + (p)->smba)
103 #define SMBHSTDAT0(p) (5 + (p)->smba)
104 #define SMBHSTDAT1(p) (6 + (p)->smba)
105 #define SMBBLKDAT(p) (7 + (p)->smba)
106 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
107 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
108 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
109
110 /* PCI Address Constants */
111 #define SMBBAR 4
112 #define SMBPCISTS 0x006
113 #define SMBHSTCFG 0x040
114
115 /* Host status bits for SMBPCISTS */
116 #define SMBPCISTS_INTS 0x08
117
118 /* Host configuration bits for SMBHSTCFG */
119 #define SMBHSTCFG_HST_EN 1
120 #define SMBHSTCFG_SMB_SMI_EN 2
121 #define SMBHSTCFG_I2C_EN 4
122
123 /* Auxiliary control register bits, ICH4+ only */
124 #define SMBAUXCTL_CRC 1
125 #define SMBAUXCTL_E32B 2
126
127 /* Other settings */
128 #define MAX_RETRIES 400
129
130 /* I801 command constants */
131 #define I801_QUICK 0x00
132 #define I801_BYTE 0x04
133 #define I801_BYTE_DATA 0x08
134 #define I801_WORD_DATA 0x0C
135 #define I801_PROC_CALL 0x10 /* unimplemented */
136 #define I801_BLOCK_DATA 0x14
137 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
138
139 /* I801 Host Control register bits */
140 #define SMBHSTCNT_INTREN 0x01
141 #define SMBHSTCNT_KILL 0x02
142 #define SMBHSTCNT_LAST_BYTE 0x20
143 #define SMBHSTCNT_START 0x40
144 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
145
146 /* I801 Hosts Status register bits */
147 #define SMBHSTSTS_BYTE_DONE 0x80
148 #define SMBHSTSTS_INUSE_STS 0x40
149 #define SMBHSTSTS_SMBALERT_STS 0x20
150 #define SMBHSTSTS_FAILED 0x10
151 #define SMBHSTSTS_BUS_ERR 0x08
152 #define SMBHSTSTS_DEV_ERR 0x04
153 #define SMBHSTSTS_INTR 0x02
154 #define SMBHSTSTS_HOST_BUSY 0x01
155
156 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
157 SMBHSTSTS_DEV_ERR)
158
159 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
160 STATUS_ERROR_FLAGS)
161
162 /* Older devices have their ID defined in <linux/pci_ids.h> */
163 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
164 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
165 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
166 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
167 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
169 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
170 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
171 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
172 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
173 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
174 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
175 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
176 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
177 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
178 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
179
180 struct i801_mux_config {
181 char *gpio_chip;
182 unsigned values[3];
183 int n_values;
184 unsigned classes[3];
185 unsigned gpios[2]; /* Relative to gpio_chip->base */
186 int n_gpios;
187 };
188
189 struct i801_priv {
190 struct i2c_adapter adapter;
191 unsigned long smba;
192 unsigned char original_hstcfg;
193 struct pci_dev *pci_dev;
194 unsigned int features;
195
196 /* isr processing */
197 wait_queue_head_t waitq;
198 u8 status;
199
200 /* Command state used by isr for byte-by-byte block transactions */
201 u8 cmd;
202 bool is_read;
203 int count;
204 int len;
205 u8 *data;
206
207 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
208 defined CONFIG_DMI
209 const struct i801_mux_config *mux_drvdata;
210 struct platform_device *mux_pdev;
211 #endif
212 };
213
214 static struct pci_driver i801_driver;
215
216 #define FEATURE_SMBUS_PEC (1 << 0)
217 #define FEATURE_BLOCK_BUFFER (1 << 1)
218 #define FEATURE_BLOCK_PROC (1 << 2)
219 #define FEATURE_I2C_BLOCK_READ (1 << 3)
220 #define FEATURE_IRQ (1 << 4)
221 /* Not really a feature, but it's convenient to handle it as such */
222 #define FEATURE_IDF (1 << 15)
223
224 static const char *i801_feature_names[] = {
225 "SMBus PEC",
226 "Block buffer",
227 "Block process call",
228 "I2C block read",
229 "Interrupt",
230 };
231
232 static unsigned int disable_features;
233 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
234 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
235 "\t\t 0x01 disable SMBus PEC\n"
236 "\t\t 0x02 disable the block buffer\n"
237 "\t\t 0x08 disable the I2C block read functionality\n"
238 "\t\t 0x10 don't use interrupts ");
239
240 /* Make sure the SMBus host is ready to start transmitting.
241 Return 0 if it is, -EBUSY if it is not. */
242 static int i801_check_pre(struct i801_priv *priv)
243 {
244 int status;
245
246 status = inb_p(SMBHSTSTS(priv));
247 if (status & SMBHSTSTS_HOST_BUSY) {
248 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
249 return -EBUSY;
250 }
251
252 status &= STATUS_FLAGS;
253 if (status) {
254 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
255 status);
256 outb_p(status, SMBHSTSTS(priv));
257 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
258 if (status) {
259 dev_err(&priv->pci_dev->dev,
260 "Failed clearing status flags (%02x)\n",
261 status);
262 return -EBUSY;
263 }
264 }
265
266 return 0;
267 }
268
269 /*
270 * Convert the status register to an error code, and clear it.
271 * Note that status only contains the bits we want to clear, not the
272 * actual register value.
273 */
274 static int i801_check_post(struct i801_priv *priv, int status)
275 {
276 int result = 0;
277
278 /*
279 * If the SMBus is still busy, we give up
280 * Note: This timeout condition only happens when using polling
281 * transactions. For interrupt operation, NAK/timeout is indicated by
282 * DEV_ERR.
283 */
284 if (unlikely(status < 0)) {
285 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
286 /* try to stop the current command */
287 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
288 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
289 SMBHSTCNT(priv));
290 usleep_range(1000, 2000);
291 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
292 SMBHSTCNT(priv));
293
294 /* Check if it worked */
295 status = inb_p(SMBHSTSTS(priv));
296 if ((status & SMBHSTSTS_HOST_BUSY) ||
297 !(status & SMBHSTSTS_FAILED))
298 dev_err(&priv->pci_dev->dev,
299 "Failed terminating the transaction\n");
300 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
301 return -ETIMEDOUT;
302 }
303
304 if (status & SMBHSTSTS_FAILED) {
305 result = -EIO;
306 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
307 }
308 if (status & SMBHSTSTS_DEV_ERR) {
309 result = -ENXIO;
310 dev_dbg(&priv->pci_dev->dev, "No response\n");
311 }
312 if (status & SMBHSTSTS_BUS_ERR) {
313 result = -EAGAIN;
314 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
315 }
316
317 /* Clear status flags except BYTE_DONE, to be cleared by caller */
318 outb_p(status, SMBHSTSTS(priv));
319
320 return result;
321 }
322
323 /* Wait for BUSY being cleared and either INTR or an error flag being set */
324 static int i801_wait_intr(struct i801_priv *priv)
325 {
326 int timeout = 0;
327 int status;
328
329 /* We will always wait for a fraction of a second! */
330 do {
331 usleep_range(250, 500);
332 status = inb_p(SMBHSTSTS(priv));
333 } while (((status & SMBHSTSTS_HOST_BUSY) ||
334 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
335 (timeout++ < MAX_RETRIES));
336
337 if (timeout > MAX_RETRIES) {
338 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
339 return -ETIMEDOUT;
340 }
341 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
342 }
343
344 /* Wait for either BYTE_DONE or an error flag being set */
345 static int i801_wait_byte_done(struct i801_priv *priv)
346 {
347 int timeout = 0;
348 int status;
349
350 /* We will always wait for a fraction of a second! */
351 do {
352 usleep_range(250, 500);
353 status = inb_p(SMBHSTSTS(priv));
354 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
355 (timeout++ < MAX_RETRIES));
356
357 if (timeout > MAX_RETRIES) {
358 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
359 return -ETIMEDOUT;
360 }
361 return status & STATUS_ERROR_FLAGS;
362 }
363
364 static int i801_transaction(struct i801_priv *priv, int xact)
365 {
366 int status;
367 int result;
368
369 result = i801_check_pre(priv);
370 if (result < 0)
371 return result;
372
373 if (priv->features & FEATURE_IRQ) {
374 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
375 SMBHSTCNT(priv));
376 wait_event(priv->waitq, (status = priv->status));
377 priv->status = 0;
378 return i801_check_post(priv, status);
379 }
380
381 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
382 * SMBSCMD are passed in xact */
383 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
384
385 status = i801_wait_intr(priv);
386 return i801_check_post(priv, status);
387 }
388
389 static int i801_block_transaction_by_block(struct i801_priv *priv,
390 union i2c_smbus_data *data,
391 char read_write, int hwpec)
392 {
393 int i, len;
394 int status;
395
396 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
397
398 /* Use 32-byte buffer to process this transaction */
399 if (read_write == I2C_SMBUS_WRITE) {
400 len = data->block[0];
401 outb_p(len, SMBHSTDAT0(priv));
402 for (i = 0; i < len; i++)
403 outb_p(data->block[i+1], SMBBLKDAT(priv));
404 }
405
406 status = i801_transaction(priv, I801_BLOCK_DATA |
407 (hwpec ? SMBHSTCNT_PEC_EN : 0));
408 if (status)
409 return status;
410
411 if (read_write == I2C_SMBUS_READ) {
412 len = inb_p(SMBHSTDAT0(priv));
413 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
414 return -EPROTO;
415
416 data->block[0] = len;
417 for (i = 0; i < len; i++)
418 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
419 }
420 return 0;
421 }
422
423 static void i801_isr_byte_done(struct i801_priv *priv)
424 {
425 if (priv->is_read) {
426 /* For SMBus block reads, length is received with first byte */
427 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
428 (priv->count == 0)) {
429 priv->len = inb_p(SMBHSTDAT0(priv));
430 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
431 dev_err(&priv->pci_dev->dev,
432 "Illegal SMBus block read size %d\n",
433 priv->len);
434 /* FIXME: Recover */
435 priv->len = I2C_SMBUS_BLOCK_MAX;
436 } else {
437 dev_dbg(&priv->pci_dev->dev,
438 "SMBus block read size is %d\n",
439 priv->len);
440 }
441 priv->data[-1] = priv->len;
442 }
443
444 /* Read next byte */
445 if (priv->count < priv->len)
446 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
447 else
448 dev_dbg(&priv->pci_dev->dev,
449 "Discarding extra byte on block read\n");
450
451 /* Set LAST_BYTE for last byte of read transaction */
452 if (priv->count == priv->len - 1)
453 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
454 SMBHSTCNT(priv));
455 } else if (priv->count < priv->len - 1) {
456 /* Write next byte, except for IRQ after last byte */
457 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
458 }
459
460 /* Clear BYTE_DONE to continue with next byte */
461 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
462 }
463
464 /*
465 * There are two kinds of interrupts:
466 *
467 * 1) i801 signals transaction completion with one of these interrupts:
468 * INTR - Success
469 * DEV_ERR - Invalid command, NAK or communication timeout
470 * BUS_ERR - SMI# transaction collision
471 * FAILED - transaction was canceled due to a KILL request
472 * When any of these occur, update ->status and wake up the waitq.
473 * ->status must be cleared before kicking off the next transaction.
474 *
475 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
476 * occurs for each byte of a byte-by-byte to prepare the next byte.
477 */
478 static irqreturn_t i801_isr(int irq, void *dev_id)
479 {
480 struct i801_priv *priv = dev_id;
481 u16 pcists;
482 u8 status;
483
484 /* Confirm this is our interrupt */
485 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
486 if (!(pcists & SMBPCISTS_INTS))
487 return IRQ_NONE;
488
489 status = inb_p(SMBHSTSTS(priv));
490 if (status != 0x42)
491 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
492
493 if (status & SMBHSTSTS_BYTE_DONE)
494 i801_isr_byte_done(priv);
495
496 /*
497 * Clear irq sources and report transaction result.
498 * ->status must be cleared before the next transaction is started.
499 */
500 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
501 if (status) {
502 outb_p(status, SMBHSTSTS(priv));
503 priv->status |= status;
504 wake_up(&priv->waitq);
505 }
506
507 return IRQ_HANDLED;
508 }
509
510 /*
511 * For "byte-by-byte" block transactions:
512 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
513 * I2C read uses cmd=I801_I2C_BLOCK_DATA
514 */
515 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
516 union i2c_smbus_data *data,
517 char read_write, int command,
518 int hwpec)
519 {
520 int i, len;
521 int smbcmd;
522 int status;
523 int result;
524
525 result = i801_check_pre(priv);
526 if (result < 0)
527 return result;
528
529 len = data->block[0];
530
531 if (read_write == I2C_SMBUS_WRITE) {
532 outb_p(len, SMBHSTDAT0(priv));
533 outb_p(data->block[1], SMBBLKDAT(priv));
534 }
535
536 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
537 read_write == I2C_SMBUS_READ)
538 smbcmd = I801_I2C_BLOCK_DATA;
539 else
540 smbcmd = I801_BLOCK_DATA;
541
542 if (priv->features & FEATURE_IRQ) {
543 priv->is_read = (read_write == I2C_SMBUS_READ);
544 if (len == 1 && priv->is_read)
545 smbcmd |= SMBHSTCNT_LAST_BYTE;
546 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
547 priv->len = len;
548 priv->count = 0;
549 priv->data = &data->block[1];
550
551 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
552 wait_event(priv->waitq, (status = priv->status));
553 priv->status = 0;
554 return i801_check_post(priv, status);
555 }
556
557 for (i = 1; i <= len; i++) {
558 if (i == len && read_write == I2C_SMBUS_READ)
559 smbcmd |= SMBHSTCNT_LAST_BYTE;
560 outb_p(smbcmd, SMBHSTCNT(priv));
561
562 if (i == 1)
563 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
564 SMBHSTCNT(priv));
565
566 status = i801_wait_byte_done(priv);
567 if (status)
568 goto exit;
569
570 if (i == 1 && read_write == I2C_SMBUS_READ
571 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
572 len = inb_p(SMBHSTDAT0(priv));
573 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
574 dev_err(&priv->pci_dev->dev,
575 "Illegal SMBus block read size %d\n",
576 len);
577 /* Recover */
578 while (inb_p(SMBHSTSTS(priv)) &
579 SMBHSTSTS_HOST_BUSY)
580 outb_p(SMBHSTSTS_BYTE_DONE,
581 SMBHSTSTS(priv));
582 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
583 return -EPROTO;
584 }
585 data->block[0] = len;
586 }
587
588 /* Retrieve/store value in SMBBLKDAT */
589 if (read_write == I2C_SMBUS_READ)
590 data->block[i] = inb_p(SMBBLKDAT(priv));
591 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
592 outb_p(data->block[i+1], SMBBLKDAT(priv));
593
594 /* signals SMBBLKDAT ready */
595 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
596 }
597
598 status = i801_wait_intr(priv);
599 exit:
600 return i801_check_post(priv, status);
601 }
602
603 static int i801_set_block_buffer_mode(struct i801_priv *priv)
604 {
605 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
606 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
607 return -EIO;
608 return 0;
609 }
610
611 /* Block transaction function */
612 static int i801_block_transaction(struct i801_priv *priv,
613 union i2c_smbus_data *data, char read_write,
614 int command, int hwpec)
615 {
616 int result = 0;
617 unsigned char hostc;
618
619 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
620 if (read_write == I2C_SMBUS_WRITE) {
621 /* set I2C_EN bit in configuration register */
622 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
623 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
624 hostc | SMBHSTCFG_I2C_EN);
625 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
626 dev_err(&priv->pci_dev->dev,
627 "I2C block read is unsupported!\n");
628 return -EOPNOTSUPP;
629 }
630 }
631
632 if (read_write == I2C_SMBUS_WRITE
633 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
634 if (data->block[0] < 1)
635 data->block[0] = 1;
636 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
637 data->block[0] = I2C_SMBUS_BLOCK_MAX;
638 } else {
639 data->block[0] = 32; /* max for SMBus block reads */
640 }
641
642 /* Experience has shown that the block buffer can only be used for
643 SMBus (not I2C) block transactions, even though the datasheet
644 doesn't mention this limitation. */
645 if ((priv->features & FEATURE_BLOCK_BUFFER)
646 && command != I2C_SMBUS_I2C_BLOCK_DATA
647 && i801_set_block_buffer_mode(priv) == 0)
648 result = i801_block_transaction_by_block(priv, data,
649 read_write, hwpec);
650 else
651 result = i801_block_transaction_byte_by_byte(priv, data,
652 read_write,
653 command, hwpec);
654
655 if (command == I2C_SMBUS_I2C_BLOCK_DATA
656 && read_write == I2C_SMBUS_WRITE) {
657 /* restore saved configuration register value */
658 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
659 }
660 return result;
661 }
662
663 /* Return negative errno on error. */
664 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
665 unsigned short flags, char read_write, u8 command,
666 int size, union i2c_smbus_data *data)
667 {
668 int hwpec;
669 int block = 0;
670 int ret, xact = 0;
671 struct i801_priv *priv = i2c_get_adapdata(adap);
672
673 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
674 && size != I2C_SMBUS_QUICK
675 && size != I2C_SMBUS_I2C_BLOCK_DATA;
676
677 switch (size) {
678 case I2C_SMBUS_QUICK:
679 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
680 SMBHSTADD(priv));
681 xact = I801_QUICK;
682 break;
683 case I2C_SMBUS_BYTE:
684 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
685 SMBHSTADD(priv));
686 if (read_write == I2C_SMBUS_WRITE)
687 outb_p(command, SMBHSTCMD(priv));
688 xact = I801_BYTE;
689 break;
690 case I2C_SMBUS_BYTE_DATA:
691 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
692 SMBHSTADD(priv));
693 outb_p(command, SMBHSTCMD(priv));
694 if (read_write == I2C_SMBUS_WRITE)
695 outb_p(data->byte, SMBHSTDAT0(priv));
696 xact = I801_BYTE_DATA;
697 break;
698 case I2C_SMBUS_WORD_DATA:
699 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
700 SMBHSTADD(priv));
701 outb_p(command, SMBHSTCMD(priv));
702 if (read_write == I2C_SMBUS_WRITE) {
703 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
704 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
705 }
706 xact = I801_WORD_DATA;
707 break;
708 case I2C_SMBUS_BLOCK_DATA:
709 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
710 SMBHSTADD(priv));
711 outb_p(command, SMBHSTCMD(priv));
712 block = 1;
713 break;
714 case I2C_SMBUS_I2C_BLOCK_DATA:
715 /* NB: page 240 of ICH5 datasheet shows that the R/#W
716 * bit should be cleared here, even when reading */
717 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
718 if (read_write == I2C_SMBUS_READ) {
719 /* NB: page 240 of ICH5 datasheet also shows
720 * that DATA1 is the cmd field when reading */
721 outb_p(command, SMBHSTDAT1(priv));
722 } else
723 outb_p(command, SMBHSTCMD(priv));
724 block = 1;
725 break;
726 default:
727 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
728 size);
729 return -EOPNOTSUPP;
730 }
731
732 if (hwpec) /* enable/disable hardware PEC */
733 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
734 else
735 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
736 SMBAUXCTL(priv));
737
738 if (block)
739 ret = i801_block_transaction(priv, data, read_write, size,
740 hwpec);
741 else
742 ret = i801_transaction(priv, xact);
743
744 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
745 time, so we forcibly disable it after every transaction. Turn off
746 E32B for the same reason. */
747 if (hwpec || block)
748 outb_p(inb_p(SMBAUXCTL(priv)) &
749 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
750
751 if (block)
752 return ret;
753 if (ret)
754 return ret;
755 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
756 return 0;
757
758 switch (xact & 0x7f) {
759 case I801_BYTE: /* Result put in SMBHSTDAT0 */
760 case I801_BYTE_DATA:
761 data->byte = inb_p(SMBHSTDAT0(priv));
762 break;
763 case I801_WORD_DATA:
764 data->word = inb_p(SMBHSTDAT0(priv)) +
765 (inb_p(SMBHSTDAT1(priv)) << 8);
766 break;
767 }
768 return 0;
769 }
770
771
772 static u32 i801_func(struct i2c_adapter *adapter)
773 {
774 struct i801_priv *priv = i2c_get_adapdata(adapter);
775
776 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
777 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
778 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
779 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
780 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
781 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
782 }
783
784 static const struct i2c_algorithm smbus_algorithm = {
785 .smbus_xfer = i801_access,
786 .functionality = i801_func,
787 };
788
789 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
790 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
791 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
792 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
794 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
820 { 0, }
821 };
822
823 MODULE_DEVICE_TABLE(pci, i801_ids);
824
825 #if defined CONFIG_X86 && defined CONFIG_DMI
826 static unsigned char apanel_addr;
827
828 /* Scan the system ROM for the signature "FJKEYINF" */
829 static __init const void __iomem *bios_signature(const void __iomem *bios)
830 {
831 ssize_t offset;
832 const unsigned char signature[] = "FJKEYINF";
833
834 for (offset = 0; offset < 0x10000; offset += 0x10) {
835 if (check_signature(bios + offset, signature,
836 sizeof(signature)-1))
837 return bios + offset;
838 }
839 return NULL;
840 }
841
842 static void __init input_apanel_init(void)
843 {
844 void __iomem *bios;
845 const void __iomem *p;
846
847 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
848 p = bios_signature(bios);
849 if (p) {
850 /* just use the first address */
851 apanel_addr = readb(p + 8 + 3) >> 1;
852 }
853 iounmap(bios);
854 }
855
856 struct dmi_onboard_device_info {
857 const char *name;
858 u8 type;
859 unsigned short i2c_addr;
860 const char *i2c_type;
861 };
862
863 static const struct dmi_onboard_device_info dmi_devices[] = {
864 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
865 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
866 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
867 };
868
869 static void dmi_check_onboard_device(u8 type, const char *name,
870 struct i2c_adapter *adap)
871 {
872 int i;
873 struct i2c_board_info info;
874
875 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
876 /* & ~0x80, ignore enabled/disabled bit */
877 if ((type & ~0x80) != dmi_devices[i].type)
878 continue;
879 if (strcasecmp(name, dmi_devices[i].name))
880 continue;
881
882 memset(&info, 0, sizeof(struct i2c_board_info));
883 info.addr = dmi_devices[i].i2c_addr;
884 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
885 i2c_new_device(adap, &info);
886 break;
887 }
888 }
889
890 /* We use our own function to check for onboard devices instead of
891 dmi_find_device() as some buggy BIOS's have the devices we are interested
892 in marked as disabled */
893 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
894 {
895 int i, count;
896
897 if (dm->type != 10)
898 return;
899
900 count = (dm->length - sizeof(struct dmi_header)) / 2;
901 for (i = 0; i < count; i++) {
902 const u8 *d = (char *)(dm + 1) + (i * 2);
903 const char *name = ((char *) dm) + dm->length;
904 u8 type = d[0];
905 u8 s = d[1];
906
907 if (!s)
908 continue;
909 s--;
910 while (s > 0 && name[0]) {
911 name += strlen(name) + 1;
912 s--;
913 }
914 if (name[0] == 0) /* Bogus string reference */
915 continue;
916
917 dmi_check_onboard_device(type, name, adap);
918 }
919 }
920
921 /* Register optional slaves */
922 static void i801_probe_optional_slaves(struct i801_priv *priv)
923 {
924 /* Only register slaves on main SMBus channel */
925 if (priv->features & FEATURE_IDF)
926 return;
927
928 if (apanel_addr) {
929 struct i2c_board_info info;
930
931 memset(&info, 0, sizeof(struct i2c_board_info));
932 info.addr = apanel_addr;
933 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
934 i2c_new_device(&priv->adapter, &info);
935 }
936
937 if (dmi_name_in_vendors("FUJITSU"))
938 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
939 }
940 #else
941 static void __init input_apanel_init(void) {}
942 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
943 #endif /* CONFIG_X86 && CONFIG_DMI */
944
945 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
946 defined CONFIG_DMI
947 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
948 .gpio_chip = "gpio_ich",
949 .values = { 0x02, 0x03 },
950 .n_values = 2,
951 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
952 .gpios = { 52, 53 },
953 .n_gpios = 2,
954 };
955
956 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
957 .gpio_chip = "gpio_ich",
958 .values = { 0x02, 0x03, 0x01 },
959 .n_values = 3,
960 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
961 .gpios = { 52, 53 },
962 .n_gpios = 2,
963 };
964
965 static const struct dmi_system_id mux_dmi_table[] = {
966 {
967 .matches = {
968 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
969 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
970 },
971 .driver_data = &i801_mux_config_asus_z8_d12,
972 },
973 {
974 .matches = {
975 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
976 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
977 },
978 .driver_data = &i801_mux_config_asus_z8_d12,
979 },
980 {
981 .matches = {
982 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
983 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
984 },
985 .driver_data = &i801_mux_config_asus_z8_d12,
986 },
987 {
988 .matches = {
989 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
990 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
991 },
992 .driver_data = &i801_mux_config_asus_z8_d12,
993 },
994 {
995 .matches = {
996 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
997 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
998 },
999 .driver_data = &i801_mux_config_asus_z8_d12,
1000 },
1001 {
1002 .matches = {
1003 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1004 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1005 },
1006 .driver_data = &i801_mux_config_asus_z8_d12,
1007 },
1008 {
1009 .matches = {
1010 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1011 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1012 },
1013 .driver_data = &i801_mux_config_asus_z8_d18,
1014 },
1015 {
1016 .matches = {
1017 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1018 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1019 },
1020 .driver_data = &i801_mux_config_asus_z8_d18,
1021 },
1022 {
1023 .matches = {
1024 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1025 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1026 },
1027 .driver_data = &i801_mux_config_asus_z8_d12,
1028 },
1029 { }
1030 };
1031
1032 /* Setup multiplexing if needed */
1033 static int i801_add_mux(struct i801_priv *priv)
1034 {
1035 struct device *dev = &priv->adapter.dev;
1036 const struct i801_mux_config *mux_config;
1037 struct i2c_mux_gpio_platform_data gpio_data;
1038 int err;
1039
1040 if (!priv->mux_drvdata)
1041 return 0;
1042 mux_config = priv->mux_drvdata;
1043
1044 /* Prepare the platform data */
1045 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1046 gpio_data.parent = priv->adapter.nr;
1047 gpio_data.values = mux_config->values;
1048 gpio_data.n_values = mux_config->n_values;
1049 gpio_data.classes = mux_config->classes;
1050 gpio_data.gpio_chip = mux_config->gpio_chip;
1051 gpio_data.gpios = mux_config->gpios;
1052 gpio_data.n_gpios = mux_config->n_gpios;
1053 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1054
1055 /* Register the mux device */
1056 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1057 PLATFORM_DEVID_AUTO, &gpio_data,
1058 sizeof(struct i2c_mux_gpio_platform_data));
1059 if (IS_ERR(priv->mux_pdev)) {
1060 err = PTR_ERR(priv->mux_pdev);
1061 priv->mux_pdev = NULL;
1062 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1063 return err;
1064 }
1065
1066 return 0;
1067 }
1068
1069 static void i801_del_mux(struct i801_priv *priv)
1070 {
1071 if (priv->mux_pdev)
1072 platform_device_unregister(priv->mux_pdev);
1073 }
1074
1075 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1076 {
1077 const struct dmi_system_id *id;
1078 const struct i801_mux_config *mux_config;
1079 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1080 int i;
1081
1082 id = dmi_first_match(mux_dmi_table);
1083 if (id) {
1084 /* Remove branch classes from trunk */
1085 mux_config = id->driver_data;
1086 for (i = 0; i < mux_config->n_values; i++)
1087 class &= ~mux_config->classes[i];
1088
1089 /* Remember for later */
1090 priv->mux_drvdata = mux_config;
1091 }
1092
1093 return class;
1094 }
1095 #else
1096 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1097 static inline void i801_del_mux(struct i801_priv *priv) { }
1098
1099 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1100 {
1101 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1102 }
1103 #endif
1104
1105 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1106 {
1107 unsigned char temp;
1108 int err, i;
1109 struct i801_priv *priv;
1110
1111 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1112 if (!priv)
1113 return -ENOMEM;
1114
1115 i2c_set_adapdata(&priv->adapter, priv);
1116 priv->adapter.owner = THIS_MODULE;
1117 priv->adapter.class = i801_get_adapter_class(priv);
1118 priv->adapter.algo = &smbus_algorithm;
1119
1120 priv->pci_dev = dev;
1121 switch (dev->device) {
1122 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1123 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1124 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1125 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1126 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1127 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1128 priv->features |= FEATURE_IDF;
1129 /* fall through */
1130 default:
1131 priv->features |= FEATURE_I2C_BLOCK_READ;
1132 priv->features |= FEATURE_IRQ;
1133 /* fall through */
1134 case PCI_DEVICE_ID_INTEL_82801DB_3:
1135 priv->features |= FEATURE_SMBUS_PEC;
1136 priv->features |= FEATURE_BLOCK_BUFFER;
1137 /* fall through */
1138 case PCI_DEVICE_ID_INTEL_82801CA_3:
1139 case PCI_DEVICE_ID_INTEL_82801BA_2:
1140 case PCI_DEVICE_ID_INTEL_82801AB_3:
1141 case PCI_DEVICE_ID_INTEL_82801AA_3:
1142 break;
1143 }
1144
1145 /* Disable features on user request */
1146 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1147 if (priv->features & disable_features & (1 << i))
1148 dev_notice(&dev->dev, "%s disabled by user\n",
1149 i801_feature_names[i]);
1150 }
1151 priv->features &= ~disable_features;
1152
1153 err = pci_enable_device(dev);
1154 if (err) {
1155 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1156 err);
1157 goto exit;
1158 }
1159
1160 /* Determine the address of the SMBus area */
1161 priv->smba = pci_resource_start(dev, SMBBAR);
1162 if (!priv->smba) {
1163 dev_err(&dev->dev, "SMBus base address uninitialized, "
1164 "upgrade BIOS\n");
1165 err = -ENODEV;
1166 goto exit;
1167 }
1168
1169 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1170 if (err) {
1171 err = -ENODEV;
1172 goto exit;
1173 }
1174
1175 err = pci_request_region(dev, SMBBAR, i801_driver.name);
1176 if (err) {
1177 dev_err(&dev->dev, "Failed to request SMBus region "
1178 "0x%lx-0x%Lx\n", priv->smba,
1179 (unsigned long long)pci_resource_end(dev, SMBBAR));
1180 goto exit;
1181 }
1182
1183 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1184 priv->original_hstcfg = temp;
1185 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1186 if (!(temp & SMBHSTCFG_HST_EN)) {
1187 dev_info(&dev->dev, "Enabling SMBus device\n");
1188 temp |= SMBHSTCFG_HST_EN;
1189 }
1190 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1191
1192 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1193 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1194 /* Disable SMBus interrupt feature if SMBus using SMI# */
1195 priv->features &= ~FEATURE_IRQ;
1196 }
1197
1198 /* Clear special mode bits */
1199 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1200 outb_p(inb_p(SMBAUXCTL(priv)) &
1201 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1202
1203 if (priv->features & FEATURE_IRQ) {
1204 init_waitqueue_head(&priv->waitq);
1205
1206 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1207 i801_driver.name, priv);
1208 if (err) {
1209 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1210 dev->irq, err);
1211 goto exit_release;
1212 }
1213 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1214 }
1215
1216 /* set up the sysfs linkage to our parent device */
1217 priv->adapter.dev.parent = &dev->dev;
1218
1219 /* Retry up to 3 times on lost arbitration */
1220 priv->adapter.retries = 3;
1221
1222 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1223 "SMBus I801 adapter at %04lx", priv->smba);
1224 err = i2c_add_adapter(&priv->adapter);
1225 if (err) {
1226 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1227 goto exit_free_irq;
1228 }
1229
1230 of_i2c_register_devices(&priv->adapter);
1231 i801_probe_optional_slaves(priv);
1232 /* We ignore errors - multiplexing is optional */
1233 i801_add_mux(priv);
1234
1235 pci_set_drvdata(dev, priv);
1236
1237 return 0;
1238
1239 exit_free_irq:
1240 if (priv->features & FEATURE_IRQ)
1241 free_irq(dev->irq, priv);
1242 exit_release:
1243 pci_release_region(dev, SMBBAR);
1244 exit:
1245 kfree(priv);
1246 return err;
1247 }
1248
1249 static void i801_remove(struct pci_dev *dev)
1250 {
1251 struct i801_priv *priv = pci_get_drvdata(dev);
1252
1253 i801_del_mux(priv);
1254 i2c_del_adapter(&priv->adapter);
1255 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1256
1257 if (priv->features & FEATURE_IRQ)
1258 free_irq(dev->irq, priv);
1259 pci_release_region(dev, SMBBAR);
1260
1261 kfree(priv);
1262 /*
1263 * do not call pci_disable_device(dev) since it can cause hard hangs on
1264 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1265 */
1266 }
1267
1268 #ifdef CONFIG_PM
1269 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1270 {
1271 struct i801_priv *priv = pci_get_drvdata(dev);
1272
1273 pci_save_state(dev);
1274 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1275 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1276 return 0;
1277 }
1278
1279 static int i801_resume(struct pci_dev *dev)
1280 {
1281 pci_set_power_state(dev, PCI_D0);
1282 pci_restore_state(dev);
1283 return pci_enable_device(dev);
1284 }
1285 #else
1286 #define i801_suspend NULL
1287 #define i801_resume NULL
1288 #endif
1289
1290 static struct pci_driver i801_driver = {
1291 .name = "i801_smbus",
1292 .id_table = i801_ids,
1293 .probe = i801_probe,
1294 .remove = i801_remove,
1295 .suspend = i801_suspend,
1296 .resume = i801_resume,
1297 };
1298
1299 static int __init i2c_i801_init(void)
1300 {
1301 if (dmi_name_in_vendors("FUJITSU"))
1302 input_apanel_init();
1303 return pci_register_driver(&i801_driver);
1304 }
1305
1306 static void __exit i2c_i801_exit(void)
1307 {
1308 pci_unregister_driver(&i801_driver);
1309 }
1310
1311 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
1312 "Jean Delvare <khali@linux-fr.org>");
1313 MODULE_DESCRIPTION("I801 SMBus driver");
1314 MODULE_LICENSE("GPL");
1315
1316 module_init(i2c_i801_init);
1317 module_exit(i2c_i801_exit);
kernel source for telekom puls (alcatel/mediatek)