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Merge tag 'vfio-for-v3.8-v2' of git://github.com/awilliam/linux-vfio
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56
57 Features supported by this driver:
58 Software PEC no
59 Hardware PEC yes
60 Block buffer yes
61 Block process call transaction no
62 I2C block read transaction yes (doesn't use the block buffer)
63 Slave mode no
64 Interrupt processing yes
65
66 See the file Documentation/i2c/busses/i2c-i801 for details.
67 */
68
69 #include <linux/interrupt.h>
70 #include <linux/module.h>
71 #include <linux/pci.h>
72 #include <linux/kernel.h>
73 #include <linux/stddef.h>
74 #include <linux/delay.h>
75 #include <linux/ioport.h>
76 #include <linux/init.h>
77 #include <linux/i2c.h>
78 #include <linux/acpi.h>
79 #include <linux/io.h>
80 #include <linux/dmi.h>
81 #include <linux/slab.h>
82 #include <linux/wait.h>
83 #include <linux/err.h>
84 #include <linux/of_i2c.h>
85
86 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
87 defined CONFIG_DMI
88 #include <linux/gpio.h>
89 #include <linux/i2c-mux-gpio.h>
90 #include <linux/platform_device.h>
91 #endif
92
93 /* I801 SMBus address offsets */
94 #define SMBHSTSTS(p) (0 + (p)->smba)
95 #define SMBHSTCNT(p) (2 + (p)->smba)
96 #define SMBHSTCMD(p) (3 + (p)->smba)
97 #define SMBHSTADD(p) (4 + (p)->smba)
98 #define SMBHSTDAT0(p) (5 + (p)->smba)
99 #define SMBHSTDAT1(p) (6 + (p)->smba)
100 #define SMBBLKDAT(p) (7 + (p)->smba)
101 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
102 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
103 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
104
105 /* PCI Address Constants */
106 #define SMBBAR 4
107 #define SMBPCISTS 0x006
108 #define SMBHSTCFG 0x040
109
110 /* Host status bits for SMBPCISTS */
111 #define SMBPCISTS_INTS 0x08
112
113 /* Host configuration bits for SMBHSTCFG */
114 #define SMBHSTCFG_HST_EN 1
115 #define SMBHSTCFG_SMB_SMI_EN 2
116 #define SMBHSTCFG_I2C_EN 4
117
118 /* Auxiliary control register bits, ICH4+ only */
119 #define SMBAUXCTL_CRC 1
120 #define SMBAUXCTL_E32B 2
121
122 /* Other settings */
123 #define MAX_RETRIES 400
124
125 /* I801 command constants */
126 #define I801_QUICK 0x00
127 #define I801_BYTE 0x04
128 #define I801_BYTE_DATA 0x08
129 #define I801_WORD_DATA 0x0C
130 #define I801_PROC_CALL 0x10 /* unimplemented */
131 #define I801_BLOCK_DATA 0x14
132 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
133
134 /* I801 Host Control register bits */
135 #define SMBHSTCNT_INTREN 0x01
136 #define SMBHSTCNT_KILL 0x02
137 #define SMBHSTCNT_LAST_BYTE 0x20
138 #define SMBHSTCNT_START 0x40
139 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
140
141 /* I801 Hosts Status register bits */
142 #define SMBHSTSTS_BYTE_DONE 0x80
143 #define SMBHSTSTS_INUSE_STS 0x40
144 #define SMBHSTSTS_SMBALERT_STS 0x20
145 #define SMBHSTSTS_FAILED 0x10
146 #define SMBHSTSTS_BUS_ERR 0x08
147 #define SMBHSTSTS_DEV_ERR 0x04
148 #define SMBHSTSTS_INTR 0x02
149 #define SMBHSTSTS_HOST_BUSY 0x01
150
151 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
152 SMBHSTSTS_DEV_ERR)
153
154 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
155 STATUS_ERROR_FLAGS)
156
157 /* Older devices have their ID defined in <linux/pci_ids.h> */
158 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
159 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
160 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
161 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
162 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
163 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
164 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
165 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
166 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
167 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
168 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
169
170 struct i801_mux_config {
171 char *gpio_chip;
172 unsigned values[3];
173 int n_values;
174 unsigned classes[3];
175 unsigned gpios[2]; /* Relative to gpio_chip->base */
176 int n_gpios;
177 };
178
179 struct i801_priv {
180 struct i2c_adapter adapter;
181 unsigned long smba;
182 unsigned char original_hstcfg;
183 struct pci_dev *pci_dev;
184 unsigned int features;
185
186 /* isr processing */
187 wait_queue_head_t waitq;
188 u8 status;
189
190 /* Command state used by isr for byte-by-byte block transactions */
191 u8 cmd;
192 bool is_read;
193 int count;
194 int len;
195 u8 *data;
196
197 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
198 defined CONFIG_DMI
199 const struct i801_mux_config *mux_drvdata;
200 struct platform_device *mux_pdev;
201 #endif
202 };
203
204 static struct pci_driver i801_driver;
205
206 #define FEATURE_SMBUS_PEC (1 << 0)
207 #define FEATURE_BLOCK_BUFFER (1 << 1)
208 #define FEATURE_BLOCK_PROC (1 << 2)
209 #define FEATURE_I2C_BLOCK_READ (1 << 3)
210 #define FEATURE_IRQ (1 << 4)
211 /* Not really a feature, but it's convenient to handle it as such */
212 #define FEATURE_IDF (1 << 15)
213
214 static const char *i801_feature_names[] = {
215 "SMBus PEC",
216 "Block buffer",
217 "Block process call",
218 "I2C block read",
219 "Interrupt",
220 };
221
222 static unsigned int disable_features;
223 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
224 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
225
226 /* Make sure the SMBus host is ready to start transmitting.
227 Return 0 if it is, -EBUSY if it is not. */
228 static int i801_check_pre(struct i801_priv *priv)
229 {
230 int status;
231
232 status = inb_p(SMBHSTSTS(priv));
233 if (status & SMBHSTSTS_HOST_BUSY) {
234 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
235 return -EBUSY;
236 }
237
238 status &= STATUS_FLAGS;
239 if (status) {
240 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
241 status);
242 outb_p(status, SMBHSTSTS(priv));
243 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
244 if (status) {
245 dev_err(&priv->pci_dev->dev,
246 "Failed clearing status flags (%02x)\n",
247 status);
248 return -EBUSY;
249 }
250 }
251
252 return 0;
253 }
254
255 /*
256 * Convert the status register to an error code, and clear it.
257 * Note that status only contains the bits we want to clear, not the
258 * actual register value.
259 */
260 static int i801_check_post(struct i801_priv *priv, int status)
261 {
262 int result = 0;
263
264 /*
265 * If the SMBus is still busy, we give up
266 * Note: This timeout condition only happens when using polling
267 * transactions. For interrupt operation, NAK/timeout is indicated by
268 * DEV_ERR.
269 */
270 if (unlikely(status < 0)) {
271 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
272 /* try to stop the current command */
273 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
274 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
275 SMBHSTCNT(priv));
276 usleep_range(1000, 2000);
277 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
278 SMBHSTCNT(priv));
279
280 /* Check if it worked */
281 status = inb_p(SMBHSTSTS(priv));
282 if ((status & SMBHSTSTS_HOST_BUSY) ||
283 !(status & SMBHSTSTS_FAILED))
284 dev_err(&priv->pci_dev->dev,
285 "Failed terminating the transaction\n");
286 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
287 return -ETIMEDOUT;
288 }
289
290 if (status & SMBHSTSTS_FAILED) {
291 result = -EIO;
292 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
293 }
294 if (status & SMBHSTSTS_DEV_ERR) {
295 result = -ENXIO;
296 dev_dbg(&priv->pci_dev->dev, "No response\n");
297 }
298 if (status & SMBHSTSTS_BUS_ERR) {
299 result = -EAGAIN;
300 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
301 }
302
303 /* Clear status flags except BYTE_DONE, to be cleared by caller */
304 outb_p(status, SMBHSTSTS(priv));
305
306 return result;
307 }
308
309 /* Wait for BUSY being cleared and either INTR or an error flag being set */
310 static int i801_wait_intr(struct i801_priv *priv)
311 {
312 int timeout = 0;
313 int status;
314
315 /* We will always wait for a fraction of a second! */
316 do {
317 usleep_range(250, 500);
318 status = inb_p(SMBHSTSTS(priv));
319 } while (((status & SMBHSTSTS_HOST_BUSY) ||
320 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
321 (timeout++ < MAX_RETRIES));
322
323 if (timeout > MAX_RETRIES) {
324 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
325 return -ETIMEDOUT;
326 }
327 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
328 }
329
330 /* Wait for either BYTE_DONE or an error flag being set */
331 static int i801_wait_byte_done(struct i801_priv *priv)
332 {
333 int timeout = 0;
334 int status;
335
336 /* We will always wait for a fraction of a second! */
337 do {
338 usleep_range(250, 500);
339 status = inb_p(SMBHSTSTS(priv));
340 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
341 (timeout++ < MAX_RETRIES));
342
343 if (timeout > MAX_RETRIES) {
344 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
345 return -ETIMEDOUT;
346 }
347 return status & STATUS_ERROR_FLAGS;
348 }
349
350 static int i801_transaction(struct i801_priv *priv, int xact)
351 {
352 int status;
353 int result;
354
355 result = i801_check_pre(priv);
356 if (result < 0)
357 return result;
358
359 if (priv->features & FEATURE_IRQ) {
360 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
361 SMBHSTCNT(priv));
362 wait_event(priv->waitq, (status = priv->status));
363 priv->status = 0;
364 return i801_check_post(priv, status);
365 }
366
367 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
368 * SMBSCMD are passed in xact */
369 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
370
371 status = i801_wait_intr(priv);
372 return i801_check_post(priv, status);
373 }
374
375 static int i801_block_transaction_by_block(struct i801_priv *priv,
376 union i2c_smbus_data *data,
377 char read_write, int hwpec)
378 {
379 int i, len;
380 int status;
381
382 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
383
384 /* Use 32-byte buffer to process this transaction */
385 if (read_write == I2C_SMBUS_WRITE) {
386 len = data->block[0];
387 outb_p(len, SMBHSTDAT0(priv));
388 for (i = 0; i < len; i++)
389 outb_p(data->block[i+1], SMBBLKDAT(priv));
390 }
391
392 status = i801_transaction(priv, I801_BLOCK_DATA |
393 (hwpec ? SMBHSTCNT_PEC_EN : 0));
394 if (status)
395 return status;
396
397 if (read_write == I2C_SMBUS_READ) {
398 len = inb_p(SMBHSTDAT0(priv));
399 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
400 return -EPROTO;
401
402 data->block[0] = len;
403 for (i = 0; i < len; i++)
404 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
405 }
406 return 0;
407 }
408
409 static void i801_isr_byte_done(struct i801_priv *priv)
410 {
411 if (priv->is_read) {
412 /* For SMBus block reads, length is received with first byte */
413 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
414 (priv->count == 0)) {
415 priv->len = inb_p(SMBHSTDAT0(priv));
416 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
417 dev_err(&priv->pci_dev->dev,
418 "Illegal SMBus block read size %d\n",
419 priv->len);
420 /* FIXME: Recover */
421 priv->len = I2C_SMBUS_BLOCK_MAX;
422 } else {
423 dev_dbg(&priv->pci_dev->dev,
424 "SMBus block read size is %d\n",
425 priv->len);
426 }
427 priv->data[-1] = priv->len;
428 }
429
430 /* Read next byte */
431 if (priv->count < priv->len)
432 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
433 else
434 dev_dbg(&priv->pci_dev->dev,
435 "Discarding extra byte on block read\n");
436
437 /* Set LAST_BYTE for last byte of read transaction */
438 if (priv->count == priv->len - 1)
439 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
440 SMBHSTCNT(priv));
441 } else if (priv->count < priv->len - 1) {
442 /* Write next byte, except for IRQ after last byte */
443 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
444 }
445
446 /* Clear BYTE_DONE to continue with next byte */
447 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
448 }
449
450 /*
451 * There are two kinds of interrupts:
452 *
453 * 1) i801 signals transaction completion with one of these interrupts:
454 * INTR - Success
455 * DEV_ERR - Invalid command, NAK or communication timeout
456 * BUS_ERR - SMI# transaction collision
457 * FAILED - transaction was canceled due to a KILL request
458 * When any of these occur, update ->status and wake up the waitq.
459 * ->status must be cleared before kicking off the next transaction.
460 *
461 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
462 * occurs for each byte of a byte-by-byte to prepare the next byte.
463 */
464 static irqreturn_t i801_isr(int irq, void *dev_id)
465 {
466 struct i801_priv *priv = dev_id;
467 u16 pcists;
468 u8 status;
469
470 /* Confirm this is our interrupt */
471 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
472 if (!(pcists & SMBPCISTS_INTS))
473 return IRQ_NONE;
474
475 status = inb_p(SMBHSTSTS(priv));
476 if (status != 0x42)
477 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
478
479 if (status & SMBHSTSTS_BYTE_DONE)
480 i801_isr_byte_done(priv);
481
482 /*
483 * Clear irq sources and report transaction result.
484 * ->status must be cleared before the next transaction is started.
485 */
486 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
487 if (status) {
488 outb_p(status, SMBHSTSTS(priv));
489 priv->status |= status;
490 wake_up(&priv->waitq);
491 }
492
493 return IRQ_HANDLED;
494 }
495
496 /*
497 * For "byte-by-byte" block transactions:
498 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
499 * I2C read uses cmd=I801_I2C_BLOCK_DATA
500 */
501 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
502 union i2c_smbus_data *data,
503 char read_write, int command,
504 int hwpec)
505 {
506 int i, len;
507 int smbcmd;
508 int status;
509 int result;
510
511 result = i801_check_pre(priv);
512 if (result < 0)
513 return result;
514
515 len = data->block[0];
516
517 if (read_write == I2C_SMBUS_WRITE) {
518 outb_p(len, SMBHSTDAT0(priv));
519 outb_p(data->block[1], SMBBLKDAT(priv));
520 }
521
522 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
523 read_write == I2C_SMBUS_READ)
524 smbcmd = I801_I2C_BLOCK_DATA;
525 else
526 smbcmd = I801_BLOCK_DATA;
527
528 if (priv->features & FEATURE_IRQ) {
529 priv->is_read = (read_write == I2C_SMBUS_READ);
530 if (len == 1 && priv->is_read)
531 smbcmd |= SMBHSTCNT_LAST_BYTE;
532 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
533 priv->len = len;
534 priv->count = 0;
535 priv->data = &data->block[1];
536
537 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
538 wait_event(priv->waitq, (status = priv->status));
539 priv->status = 0;
540 return i801_check_post(priv, status);
541 }
542
543 for (i = 1; i <= len; i++) {
544 if (i == len && read_write == I2C_SMBUS_READ)
545 smbcmd |= SMBHSTCNT_LAST_BYTE;
546 outb_p(smbcmd, SMBHSTCNT(priv));
547
548 if (i == 1)
549 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
550 SMBHSTCNT(priv));
551
552 status = i801_wait_byte_done(priv);
553 if (status)
554 goto exit;
555
556 if (i == 1 && read_write == I2C_SMBUS_READ
557 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
558 len = inb_p(SMBHSTDAT0(priv));
559 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
560 dev_err(&priv->pci_dev->dev,
561 "Illegal SMBus block read size %d\n",
562 len);
563 /* Recover */
564 while (inb_p(SMBHSTSTS(priv)) &
565 SMBHSTSTS_HOST_BUSY)
566 outb_p(SMBHSTSTS_BYTE_DONE,
567 SMBHSTSTS(priv));
568 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
569 return -EPROTO;
570 }
571 data->block[0] = len;
572 }
573
574 /* Retrieve/store value in SMBBLKDAT */
575 if (read_write == I2C_SMBUS_READ)
576 data->block[i] = inb_p(SMBBLKDAT(priv));
577 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
578 outb_p(data->block[i+1], SMBBLKDAT(priv));
579
580 /* signals SMBBLKDAT ready */
581 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
582 }
583
584 status = i801_wait_intr(priv);
585 exit:
586 return i801_check_post(priv, status);
587 }
588
589 static int i801_set_block_buffer_mode(struct i801_priv *priv)
590 {
591 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
592 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
593 return -EIO;
594 return 0;
595 }
596
597 /* Block transaction function */
598 static int i801_block_transaction(struct i801_priv *priv,
599 union i2c_smbus_data *data, char read_write,
600 int command, int hwpec)
601 {
602 int result = 0;
603 unsigned char hostc;
604
605 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
606 if (read_write == I2C_SMBUS_WRITE) {
607 /* set I2C_EN bit in configuration register */
608 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
609 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
610 hostc | SMBHSTCFG_I2C_EN);
611 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
612 dev_err(&priv->pci_dev->dev,
613 "I2C block read is unsupported!\n");
614 return -EOPNOTSUPP;
615 }
616 }
617
618 if (read_write == I2C_SMBUS_WRITE
619 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
620 if (data->block[0] < 1)
621 data->block[0] = 1;
622 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
623 data->block[0] = I2C_SMBUS_BLOCK_MAX;
624 } else {
625 data->block[0] = 32; /* max for SMBus block reads */
626 }
627
628 /* Experience has shown that the block buffer can only be used for
629 SMBus (not I2C) block transactions, even though the datasheet
630 doesn't mention this limitation. */
631 if ((priv->features & FEATURE_BLOCK_BUFFER)
632 && command != I2C_SMBUS_I2C_BLOCK_DATA
633 && i801_set_block_buffer_mode(priv) == 0)
634 result = i801_block_transaction_by_block(priv, data,
635 read_write, hwpec);
636 else
637 result = i801_block_transaction_byte_by_byte(priv, data,
638 read_write,
639 command, hwpec);
640
641 if (command == I2C_SMBUS_I2C_BLOCK_DATA
642 && read_write == I2C_SMBUS_WRITE) {
643 /* restore saved configuration register value */
644 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
645 }
646 return result;
647 }
648
649 /* Return negative errno on error. */
650 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
651 unsigned short flags, char read_write, u8 command,
652 int size, union i2c_smbus_data *data)
653 {
654 int hwpec;
655 int block = 0;
656 int ret, xact = 0;
657 struct i801_priv *priv = i2c_get_adapdata(adap);
658
659 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
660 && size != I2C_SMBUS_QUICK
661 && size != I2C_SMBUS_I2C_BLOCK_DATA;
662
663 switch (size) {
664 case I2C_SMBUS_QUICK:
665 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
666 SMBHSTADD(priv));
667 xact = I801_QUICK;
668 break;
669 case I2C_SMBUS_BYTE:
670 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
671 SMBHSTADD(priv));
672 if (read_write == I2C_SMBUS_WRITE)
673 outb_p(command, SMBHSTCMD(priv));
674 xact = I801_BYTE;
675 break;
676 case I2C_SMBUS_BYTE_DATA:
677 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
678 SMBHSTADD(priv));
679 outb_p(command, SMBHSTCMD(priv));
680 if (read_write == I2C_SMBUS_WRITE)
681 outb_p(data->byte, SMBHSTDAT0(priv));
682 xact = I801_BYTE_DATA;
683 break;
684 case I2C_SMBUS_WORD_DATA:
685 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
686 SMBHSTADD(priv));
687 outb_p(command, SMBHSTCMD(priv));
688 if (read_write == I2C_SMBUS_WRITE) {
689 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
690 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
691 }
692 xact = I801_WORD_DATA;
693 break;
694 case I2C_SMBUS_BLOCK_DATA:
695 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
696 SMBHSTADD(priv));
697 outb_p(command, SMBHSTCMD(priv));
698 block = 1;
699 break;
700 case I2C_SMBUS_I2C_BLOCK_DATA:
701 /* NB: page 240 of ICH5 datasheet shows that the R/#W
702 * bit should be cleared here, even when reading */
703 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
704 if (read_write == I2C_SMBUS_READ) {
705 /* NB: page 240 of ICH5 datasheet also shows
706 * that DATA1 is the cmd field when reading */
707 outb_p(command, SMBHSTDAT1(priv));
708 } else
709 outb_p(command, SMBHSTCMD(priv));
710 block = 1;
711 break;
712 default:
713 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
714 size);
715 return -EOPNOTSUPP;
716 }
717
718 if (hwpec) /* enable/disable hardware PEC */
719 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
720 else
721 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
722 SMBAUXCTL(priv));
723
724 if (block)
725 ret = i801_block_transaction(priv, data, read_write, size,
726 hwpec);
727 else
728 ret = i801_transaction(priv, xact);
729
730 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
731 time, so we forcibly disable it after every transaction. Turn off
732 E32B for the same reason. */
733 if (hwpec || block)
734 outb_p(inb_p(SMBAUXCTL(priv)) &
735 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
736
737 if (block)
738 return ret;
739 if (ret)
740 return ret;
741 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
742 return 0;
743
744 switch (xact & 0x7f) {
745 case I801_BYTE: /* Result put in SMBHSTDAT0 */
746 case I801_BYTE_DATA:
747 data->byte = inb_p(SMBHSTDAT0(priv));
748 break;
749 case I801_WORD_DATA:
750 data->word = inb_p(SMBHSTDAT0(priv)) +
751 (inb_p(SMBHSTDAT1(priv)) << 8);
752 break;
753 }
754 return 0;
755 }
756
757
758 static u32 i801_func(struct i2c_adapter *adapter)
759 {
760 struct i801_priv *priv = i2c_get_adapdata(adapter);
761
762 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
763 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
764 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
765 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
766 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
767 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
768 }
769
770 static const struct i2c_algorithm smbus_algorithm = {
771 .smbus_xfer = i801_access,
772 .functionality = i801_func,
773 };
774
775 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
776 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
777 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
778 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
779 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
780 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
781 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
782 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
783 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
784 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
785 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
786 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
787 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
788 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
789 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
790 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
791 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
792 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
794 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
801 { 0, }
802 };
803
804 MODULE_DEVICE_TABLE(pci, i801_ids);
805
806 #if defined CONFIG_X86 && defined CONFIG_DMI
807 static unsigned char apanel_addr;
808
809 /* Scan the system ROM for the signature "FJKEYINF" */
810 static __init const void __iomem *bios_signature(const void __iomem *bios)
811 {
812 ssize_t offset;
813 const unsigned char signature[] = "FJKEYINF";
814
815 for (offset = 0; offset < 0x10000; offset += 0x10) {
816 if (check_signature(bios + offset, signature,
817 sizeof(signature)-1))
818 return bios + offset;
819 }
820 return NULL;
821 }
822
823 static void __init input_apanel_init(void)
824 {
825 void __iomem *bios;
826 const void __iomem *p;
827
828 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
829 p = bios_signature(bios);
830 if (p) {
831 /* just use the first address */
832 apanel_addr = readb(p + 8 + 3) >> 1;
833 }
834 iounmap(bios);
835 }
836
837 struct dmi_onboard_device_info {
838 const char *name;
839 u8 type;
840 unsigned short i2c_addr;
841 const char *i2c_type;
842 };
843
844 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
845 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
846 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
847 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
848 };
849
850 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
851 struct i2c_adapter *adap)
852 {
853 int i;
854 struct i2c_board_info info;
855
856 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
857 /* & ~0x80, ignore enabled/disabled bit */
858 if ((type & ~0x80) != dmi_devices[i].type)
859 continue;
860 if (strcasecmp(name, dmi_devices[i].name))
861 continue;
862
863 memset(&info, 0, sizeof(struct i2c_board_info));
864 info.addr = dmi_devices[i].i2c_addr;
865 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
866 i2c_new_device(adap, &info);
867 break;
868 }
869 }
870
871 /* We use our own function to check for onboard devices instead of
872 dmi_find_device() as some buggy BIOS's have the devices we are interested
873 in marked as disabled */
874 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
875 void *adap)
876 {
877 int i, count;
878
879 if (dm->type != 10)
880 return;
881
882 count = (dm->length - sizeof(struct dmi_header)) / 2;
883 for (i = 0; i < count; i++) {
884 const u8 *d = (char *)(dm + 1) + (i * 2);
885 const char *name = ((char *) dm) + dm->length;
886 u8 type = d[0];
887 u8 s = d[1];
888
889 if (!s)
890 continue;
891 s--;
892 while (s > 0 && name[0]) {
893 name += strlen(name) + 1;
894 s--;
895 }
896 if (name[0] == 0) /* Bogus string reference */
897 continue;
898
899 dmi_check_onboard_device(type, name, adap);
900 }
901 }
902
903 /* Register optional slaves */
904 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
905 {
906 /* Only register slaves on main SMBus channel */
907 if (priv->features & FEATURE_IDF)
908 return;
909
910 if (apanel_addr) {
911 struct i2c_board_info info;
912
913 memset(&info, 0, sizeof(struct i2c_board_info));
914 info.addr = apanel_addr;
915 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
916 i2c_new_device(&priv->adapter, &info);
917 }
918
919 if (dmi_name_in_vendors("FUJITSU"))
920 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
921 }
922 #else
923 static void __init input_apanel_init(void) {}
924 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
925 #endif /* CONFIG_X86 && CONFIG_DMI */
926
927 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
928 defined CONFIG_DMI
929 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
930 .gpio_chip = "gpio_ich",
931 .values = { 0x02, 0x03 },
932 .n_values = 2,
933 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
934 .gpios = { 52, 53 },
935 .n_gpios = 2,
936 };
937
938 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
939 .gpio_chip = "gpio_ich",
940 .values = { 0x02, 0x03, 0x01 },
941 .n_values = 3,
942 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
943 .gpios = { 52, 53 },
944 .n_gpios = 2,
945 };
946
947 static struct dmi_system_id __devinitdata mux_dmi_table[] = {
948 {
949 .matches = {
950 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
951 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
952 },
953 .driver_data = &i801_mux_config_asus_z8_d12,
954 },
955 {
956 .matches = {
957 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
958 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
959 },
960 .driver_data = &i801_mux_config_asus_z8_d12,
961 },
962 {
963 .matches = {
964 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
965 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
966 },
967 .driver_data = &i801_mux_config_asus_z8_d12,
968 },
969 {
970 .matches = {
971 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
972 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
973 },
974 .driver_data = &i801_mux_config_asus_z8_d12,
975 },
976 {
977 .matches = {
978 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
979 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
980 },
981 .driver_data = &i801_mux_config_asus_z8_d12,
982 },
983 {
984 .matches = {
985 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
986 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
987 },
988 .driver_data = &i801_mux_config_asus_z8_d12,
989 },
990 {
991 .matches = {
992 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
993 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
994 },
995 .driver_data = &i801_mux_config_asus_z8_d18,
996 },
997 {
998 .matches = {
999 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1000 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1001 },
1002 .driver_data = &i801_mux_config_asus_z8_d18,
1003 },
1004 {
1005 .matches = {
1006 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1007 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1008 },
1009 .driver_data = &i801_mux_config_asus_z8_d12,
1010 },
1011 { }
1012 };
1013
1014 /* Setup multiplexing if needed */
1015 static int __devinit i801_add_mux(struct i801_priv *priv)
1016 {
1017 struct device *dev = &priv->adapter.dev;
1018 const struct i801_mux_config *mux_config;
1019 struct i2c_mux_gpio_platform_data gpio_data;
1020 int err;
1021
1022 if (!priv->mux_drvdata)
1023 return 0;
1024 mux_config = priv->mux_drvdata;
1025
1026 /* Prepare the platform data */
1027 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1028 gpio_data.parent = priv->adapter.nr;
1029 gpio_data.values = mux_config->values;
1030 gpio_data.n_values = mux_config->n_values;
1031 gpio_data.classes = mux_config->classes;
1032 gpio_data.gpio_chip = mux_config->gpio_chip;
1033 gpio_data.gpios = mux_config->gpios;
1034 gpio_data.n_gpios = mux_config->n_gpios;
1035 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1036
1037 /* Register the mux device */
1038 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1039 PLATFORM_DEVID_AUTO, &gpio_data,
1040 sizeof(struct i2c_mux_gpio_platform_data));
1041 if (IS_ERR(priv->mux_pdev)) {
1042 err = PTR_ERR(priv->mux_pdev);
1043 priv->mux_pdev = NULL;
1044 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1045 return err;
1046 }
1047
1048 return 0;
1049 }
1050
1051 static void __devexit i801_del_mux(struct i801_priv *priv)
1052 {
1053 if (priv->mux_pdev)
1054 platform_device_unregister(priv->mux_pdev);
1055 }
1056
1057 static unsigned int __devinit i801_get_adapter_class(struct i801_priv *priv)
1058 {
1059 const struct dmi_system_id *id;
1060 const struct i801_mux_config *mux_config;
1061 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1062 int i;
1063
1064 id = dmi_first_match(mux_dmi_table);
1065 if (id) {
1066 /* Remove branch classes from trunk */
1067 mux_config = id->driver_data;
1068 for (i = 0; i < mux_config->n_values; i++)
1069 class &= ~mux_config->classes[i];
1070
1071 /* Remember for later */
1072 priv->mux_drvdata = mux_config;
1073 }
1074
1075 return class;
1076 }
1077 #else
1078 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1079 static inline void i801_del_mux(struct i801_priv *priv) { }
1080
1081 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1082 {
1083 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1084 }
1085 #endif
1086
1087 static int __devinit i801_probe(struct pci_dev *dev,
1088 const struct pci_device_id *id)
1089 {
1090 unsigned char temp;
1091 int err, i;
1092 struct i801_priv *priv;
1093
1094 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1095 if (!priv)
1096 return -ENOMEM;
1097
1098 i2c_set_adapdata(&priv->adapter, priv);
1099 priv->adapter.owner = THIS_MODULE;
1100 priv->adapter.class = i801_get_adapter_class(priv);
1101 priv->adapter.algo = &smbus_algorithm;
1102
1103 priv->pci_dev = dev;
1104 switch (dev->device) {
1105 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1106 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1107 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1108 priv->features |= FEATURE_IDF;
1109 /* fall through */
1110 default:
1111 priv->features |= FEATURE_I2C_BLOCK_READ;
1112 priv->features |= FEATURE_IRQ;
1113 /* fall through */
1114 case PCI_DEVICE_ID_INTEL_82801DB_3:
1115 priv->features |= FEATURE_SMBUS_PEC;
1116 priv->features |= FEATURE_BLOCK_BUFFER;
1117 /* fall through */
1118 case PCI_DEVICE_ID_INTEL_82801CA_3:
1119 case PCI_DEVICE_ID_INTEL_82801BA_2:
1120 case PCI_DEVICE_ID_INTEL_82801AB_3:
1121 case PCI_DEVICE_ID_INTEL_82801AA_3:
1122 break;
1123 }
1124
1125 /* Disable features on user request */
1126 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1127 if (priv->features & disable_features & (1 << i))
1128 dev_notice(&dev->dev, "%s disabled by user\n",
1129 i801_feature_names[i]);
1130 }
1131 priv->features &= ~disable_features;
1132
1133 err = pci_enable_device(dev);
1134 if (err) {
1135 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1136 err);
1137 goto exit;
1138 }
1139
1140 /* Determine the address of the SMBus area */
1141 priv->smba = pci_resource_start(dev, SMBBAR);
1142 if (!priv->smba) {
1143 dev_err(&dev->dev, "SMBus base address uninitialized, "
1144 "upgrade BIOS\n");
1145 err = -ENODEV;
1146 goto exit;
1147 }
1148
1149 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1150 if (err) {
1151 err = -ENODEV;
1152 goto exit;
1153 }
1154
1155 err = pci_request_region(dev, SMBBAR, i801_driver.name);
1156 if (err) {
1157 dev_err(&dev->dev, "Failed to request SMBus region "
1158 "0x%lx-0x%Lx\n", priv->smba,
1159 (unsigned long long)pci_resource_end(dev, SMBBAR));
1160 goto exit;
1161 }
1162
1163 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1164 priv->original_hstcfg = temp;
1165 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1166 if (!(temp & SMBHSTCFG_HST_EN)) {
1167 dev_info(&dev->dev, "Enabling SMBus device\n");
1168 temp |= SMBHSTCFG_HST_EN;
1169 }
1170 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1171
1172 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1173 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1174 /* Disable SMBus interrupt feature if SMBus using SMI# */
1175 priv->features &= ~FEATURE_IRQ;
1176 }
1177
1178 /* Clear special mode bits */
1179 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1180 outb_p(inb_p(SMBAUXCTL(priv)) &
1181 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1182
1183 if (priv->features & FEATURE_IRQ) {
1184 init_waitqueue_head(&priv->waitq);
1185
1186 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1187 i801_driver.name, priv);
1188 if (err) {
1189 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1190 dev->irq, err);
1191 goto exit_release;
1192 }
1193 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1194 }
1195
1196 /* set up the sysfs linkage to our parent device */
1197 priv->adapter.dev.parent = &dev->dev;
1198
1199 /* Retry up to 3 times on lost arbitration */
1200 priv->adapter.retries = 3;
1201
1202 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1203 "SMBus I801 adapter at %04lx", priv->smba);
1204 err = i2c_add_adapter(&priv->adapter);
1205 if (err) {
1206 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1207 goto exit_free_irq;
1208 }
1209
1210 of_i2c_register_devices(&priv->adapter);
1211 i801_probe_optional_slaves(priv);
1212 /* We ignore errors - multiplexing is optional */
1213 i801_add_mux(priv);
1214
1215 pci_set_drvdata(dev, priv);
1216
1217 return 0;
1218
1219 exit_free_irq:
1220 if (priv->features & FEATURE_IRQ)
1221 free_irq(dev->irq, priv);
1222 exit_release:
1223 pci_release_region(dev, SMBBAR);
1224 exit:
1225 kfree(priv);
1226 return err;
1227 }
1228
1229 static void __devexit i801_remove(struct pci_dev *dev)
1230 {
1231 struct i801_priv *priv = pci_get_drvdata(dev);
1232
1233 i801_del_mux(priv);
1234 i2c_del_adapter(&priv->adapter);
1235 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1236
1237 if (priv->features & FEATURE_IRQ)
1238 free_irq(dev->irq, priv);
1239 pci_release_region(dev, SMBBAR);
1240
1241 pci_set_drvdata(dev, NULL);
1242 kfree(priv);
1243 /*
1244 * do not call pci_disable_device(dev) since it can cause hard hangs on
1245 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1246 */
1247 }
1248
1249 #ifdef CONFIG_PM
1250 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1251 {
1252 struct i801_priv *priv = pci_get_drvdata(dev);
1253
1254 pci_save_state(dev);
1255 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1256 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1257 return 0;
1258 }
1259
1260 static int i801_resume(struct pci_dev *dev)
1261 {
1262 pci_set_power_state(dev, PCI_D0);
1263 pci_restore_state(dev);
1264 return pci_enable_device(dev);
1265 }
1266 #else
1267 #define i801_suspend NULL
1268 #define i801_resume NULL
1269 #endif
1270
1271 static struct pci_driver i801_driver = {
1272 .name = "i801_smbus",
1273 .id_table = i801_ids,
1274 .probe = i801_probe,
1275 .remove = __devexit_p(i801_remove),
1276 .suspend = i801_suspend,
1277 .resume = i801_resume,
1278 };
1279
1280 static int __init i2c_i801_init(void)
1281 {
1282 if (dmi_name_in_vendors("FUJITSU"))
1283 input_apanel_init();
1284 return pci_register_driver(&i801_driver);
1285 }
1286
1287 static void __exit i2c_i801_exit(void)
1288 {
1289 pci_unregister_driver(&i801_driver);
1290 }
1291
1292 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
1293 "Jean Delvare <khali@linux-fr.org>");
1294 MODULE_DESCRIPTION("I801 SMBus driver");
1295 MODULE_LICENSE("GPL");
1296
1297 module_init(i2c_i801_init);
1298 module_exit(i2c_i801_exit);
kernel source for telekom puls (alcatel/mediatek)