drivers/i2c/busses/i2c-designware-core.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  * ----------------------------------------------------------------------------
  26  *
  27  */
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/errno.h>
  31 #include <linux/err.h>
  32 #include <linux/i2c.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/io.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/delay.h>
  37 #include <linux/module.h>
  38 #include "i2c-designware-core.h"
  39
  40 /*
  41  * Registers offset
  42  */
  43 #define DW_IC_CON               0x0
  44 #define DW_IC_TAR               0x4
  45 #define DW_IC_DATA_CMD          0x10
  46 #define DW_IC_SS_SCL_HCNT       0x14
  47 #define DW_IC_SS_SCL_LCNT       0x18
  48 #define DW_IC_FS_SCL_HCNT       0x1c
  49 #define DW_IC_FS_SCL_LCNT       0x20
  50 #define DW_IC_INTR_STAT         0x2c
  51 #define DW_IC_INTR_MASK         0x30
  52 #define DW_IC_RAW_INTR_STAT     0x34
  53 #define DW_IC_RX_TL             0x38
  54 #define DW_IC_TX_TL             0x3c
  55 #define DW_IC_CLR_INTR          0x40
  56 #define DW_IC_CLR_RX_UNDER      0x44
  57 #define DW_IC_CLR_RX_OVER       0x48
  58 #define DW_IC_CLR_TX_OVER       0x4c
  59 #define DW_IC_CLR_RD_REQ        0x50
  60 #define DW_IC_CLR_TX_ABRT       0x54
  61 #define DW_IC_CLR_RX_DONE       0x58
  62 #define DW_IC_CLR_ACTIVITY      0x5c
  63 #define DW_IC_CLR_STOP_DET      0x60
  64 #define DW_IC_CLR_START_DET     0x64
  65 #define DW_IC_CLR_GEN_CALL      0x68
  66 #define DW_IC_ENABLE            0x6c
  67 #define DW_IC_STATUS            0x70
  68 #define DW_IC_TXFLR             0x74
  69 #define DW_IC_RXFLR             0x78
  70 #define DW_IC_TX_ABRT_SOURCE    0x80
  71 #define DW_IC_ENABLE_STATUS     0x9c
  72 #define DW_IC_COMP_PARAM_1      0xf4
  73 #define DW_IC_COMP_TYPE         0xfc
  74 #define DW_IC_COMP_TYPE_VALUE   0x44570140
  75
  76 #define DW_IC_INTR_RX_UNDER     0x001
  77 #define DW_IC_INTR_RX_OVER      0x002
  78 #define DW_IC_INTR_RX_FULL      0x004
  79 #define DW_IC_INTR_TX_OVER      0x008
  80 #define DW_IC_INTR_TX_EMPTY     0x010
  81 #define DW_IC_INTR_RD_REQ       0x020
  82 #define DW_IC_INTR_TX_ABRT      0x040
  83 #define DW_IC_INTR_RX_DONE      0x080
  84 #define DW_IC_INTR_ACTIVITY     0x100
  85 #define DW_IC_INTR_STOP_DET     0x200
  86 #define DW_IC_INTR_START_DET    0x400
  87 #define DW_IC_INTR_GEN_CALL     0x800
  88
  89 #define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
  90                                          DW_IC_INTR_TX_EMPTY | \
  91                                          DW_IC_INTR_TX_ABRT | \
  92                                          DW_IC_INTR_STOP_DET)
  93
  94 #define DW_IC_STATUS_ACTIVITY   0x1
  95
  96 #define DW_IC_ERR_TX_ABRT       0x1
  97
  98 /*
  99  * status codes
 100  */
 101 #define STATUS_IDLE                     0x0
 102 #define STATUS_WRITE_IN_PROGRESS        0x1
 103 #define STATUS_READ_IN_PROGRESS         0x2
 104
 105 #define TIMEOUT                 20 /* ms */
 106
 107 /*
 108  * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 109  *
 110  * only expected abort codes are listed here
 111  * refer to the datasheet for the full list
 112  */
 113 #define ABRT_7B_ADDR_NOACK      0
 114 #define ABRT_10ADDR1_NOACK      1
 115 #define ABRT_10ADDR2_NOACK      2
 116 #define ABRT_TXDATA_NOACK       3
 117 #define ABRT_GCALL_NOACK        4
 118 #define ABRT_GCALL_READ         5
 119 #define ABRT_SBYTE_ACKDET       7
 120 #define ABRT_SBYTE_NORSTRT      9
 121 #define ABRT_10B_RD_NORSTRT     10
 122 #define ABRT_MASTER_DIS         11
 123 #define ARB_LOST                12
 124
 125 #define DW_IC_TX_ABRT_7B_ADDR_NOACK     (1UL << ABRT_7B_ADDR_NOACK)
 126 #define DW_IC_TX_ABRT_10ADDR1_NOACK     (1UL << ABRT_10ADDR1_NOACK)
 127 #define DW_IC_TX_ABRT_10ADDR2_NOACK     (1UL << ABRT_10ADDR2_NOACK)
 128 #define DW_IC_TX_ABRT_TXDATA_NOACK      (1UL << ABRT_TXDATA_NOACK)
 129 #define DW_IC_TX_ABRT_GCALL_NOACK       (1UL << ABRT_GCALL_NOACK)
 130 #define DW_IC_TX_ABRT_GCALL_READ        (1UL << ABRT_GCALL_READ)
 131 #define DW_IC_TX_ABRT_SBYTE_ACKDET      (1UL << ABRT_SBYTE_ACKDET)
 132 #define DW_IC_TX_ABRT_SBYTE_NORSTRT     (1UL << ABRT_SBYTE_NORSTRT)
 133 #define DW_IC_TX_ABRT_10B_RD_NORSTRT    (1UL << ABRT_10B_RD_NORSTRT)
 134 #define DW_IC_TX_ABRT_MASTER_DIS        (1UL << ABRT_MASTER_DIS)
 135 #define DW_IC_TX_ARB_LOST               (1UL << ARB_LOST)
 136
 137 #define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 138                                          DW_IC_TX_ABRT_10ADDR1_NOACK | \
 139                                          DW_IC_TX_ABRT_10ADDR2_NOACK | \
 140                                          DW_IC_TX_ABRT_TXDATA_NOACK | \
 141                                          DW_IC_TX_ABRT_GCALL_NOACK)
 142
 143 static char *abort_sources[] = {
 144         [ABRT_7B_ADDR_NOACK] =
 145                 "slave address not acknowledged (7bit mode)",
 146         [ABRT_10ADDR1_NOACK] =
 147                 "first address byte not acknowledged (10bit mode)",
 148         [ABRT_10ADDR2_NOACK] =
 149                 "second address byte not acknowledged (10bit mode)",
 150         [ABRT_TXDATA_NOACK] =
 151                 "data not acknowledged",
 152         [ABRT_GCALL_NOACK] =
 153                 "no acknowledgement for a general call",
 154         [ABRT_GCALL_READ] =
 155                 "read after general call",
 156         [ABRT_SBYTE_ACKDET] =
 157                 "start byte acknowledged",
 158         [ABRT_SBYTE_NORSTRT] =
 159                 "trying to send start byte when restart is disabled",
 160         [ABRT_10B_RD_NORSTRT] =
 161                 "trying to read when restart is disabled (10bit mode)",
 162         [ABRT_MASTER_DIS] =
 163                 "trying to use disabled adapter",
 164         [ARB_LOST] =
 165                 "lost arbitration",
 166 };
 167
 168 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
 169 {
 170         u32 value;
 171
 172         if (dev->accessor_flags & ACCESS_16BIT)
 173                 value = readw(dev->base + offset) |
 174                         (readw(dev->base + offset + 2) << 16);
 175         else
 176                 value = readl(dev->base + offset);
 177
 178         if (dev->accessor_flags & ACCESS_SWAP)
 179                 return swab32(value);
 180         else
 181                 return value;
 182 }
 183
 184 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
 185 {
 186         if (dev->accessor_flags & ACCESS_SWAP)
 187                 b = swab32(b);
 188
 189         if (dev->accessor_flags & ACCESS_16BIT) {
 190                 writew((u16)b, dev->base + offset);
 191                 writew((u16)(b >> 16), dev->base + offset + 2);
 192         } else {
 193                 writel(b, dev->base + offset);
 194         }
 195 }
 196
 197 static u32
 198 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
 199 {
 200         /*
 201          * DesignWare I2C core doesn't seem to have solid strategy to meet
 202          * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
 203          * will result in violation of the tHD;STA spec.
 204          */
 205         if (cond)
 206                 /*
 207                  * Conditional expression:
 208                  *
 209                  *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
 210                  *
 211                  * This is based on the DW manuals, and represents an ideal
 212                  * configuration.  The resulting I2C bus speed will be
 213                  * faster than any of the others.
 214                  *
 215                  * If your hardware is free from tHD;STA issue, try this one.
 216                  */
 217                 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
 218         else
 219                 /*
 220                  * Conditional expression:
 221                  *
 222                  *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
 223                  *
 224                  * This is just experimental rule; the tHD;STA period turned
 225                  * out to be proportinal to (_HCNT + 3).  With this setting,
 226                  * we could meet both tHIGH and tHD;STA timing specs.
 227                  *
 228                  * If unsure, you'd better to take this alternative.
 229                  *
 230                  * The reason why we need to take into account "tf" here,
 231                  * is the same as described in i2c_dw_scl_lcnt().
 232                  */
 233                 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
 234 }
 235
 236 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
 237 {
 238         /*
 239          * Conditional expression:
 240          *
 241          *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
 242          *
 243          * DW I2C core starts counting the SCL CNTs for the LOW period
 244          * of the SCL clock (tLOW) as soon as it pulls the SCL line.
 245          * In order to meet the tLOW timing spec, we need to take into
 246          * account the fall time of SCL signal (tf).  Default tf value
 247          * should be 0.3 us, for safety.
 248          */
 249         return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
 250 }
 251
 252 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
 253 {
 254         int timeout = 100;
 255
 256         do {
 257                 dw_writel(dev, enable, DW_IC_ENABLE);
 258                 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
 259                         return;
 260
 261                 /*
 262                  * Wait 10 times the signaling period of the highest I2C
 263                  * transfer supported by the driver (for 400KHz this is
 264                  * 25us) as described in the DesignWare I2C databook.
 265                  */
 266                 usleep_range(25, 250);
 267         } while (timeout--);
 268
 269         dev_warn(dev->dev, "timeout in %sabling adapter\n",
 270                  enable ? "en" : "dis");
 271 }
 272
 273 /**
 274  * i2c_dw_init() - initialize the designware i2c master hardware
 275  * @dev: device private data
 276  *
 277  * This functions configures and enables the I2C master.
 278  * This function is called during I2C init function, and in case of timeout at
 279  * run time.
 280  */
 281 int i2c_dw_init(struct dw_i2c_dev *dev)
 282 {
 283         u32 input_clock_khz;
 284         u32 hcnt, lcnt;
 285         u32 reg;
 286
 287         input_clock_khz = dev->get_clk_rate_khz(dev);
 288
 289         reg = dw_readl(dev, DW_IC_COMP_TYPE);
 290         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
 291                 /* Configure register endianess access */
 292                 dev->accessor_flags |= ACCESS_SWAP;
 293         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
 294                 /* Configure register access mode 16bit */
 295                 dev->accessor_flags |= ACCESS_16BIT;
 296         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
 297                 dev_err(dev->dev, "Unknown Synopsys component type: "
 298                         "0x%08x\n", reg);
 299                 return -ENODEV;
 300         }
 301
 302         /* Disable the adapter */
 303         __i2c_dw_enable(dev, false);
 304
 305         /* set standard and fast speed deviders for high/low periods */
 306
 307         /* Standard-mode */
 308         hcnt = i2c_dw_scl_hcnt(input_clock_khz,
 309                                 40,     /* tHD;STA = tHIGH = 4.0 us */
 310                                 3,      /* tf = 0.3 us */
 311                                 0,      /* 0: DW default, 1: Ideal */
 312                                 0);     /* No offset */
 313         lcnt = i2c_dw_scl_lcnt(input_clock_khz,
 314                                 47,     /* tLOW = 4.7 us */
 315                                 3,      /* tf = 0.3 us */
 316                                 0);     /* No offset */
 317         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 318         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 319         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 320
 321         /* Fast-mode */
 322         hcnt = i2c_dw_scl_hcnt(input_clock_khz,
 323                                 6,      /* tHD;STA = tHIGH = 0.6 us */
 324                                 3,      /* tf = 0.3 us */
 325                                 0,      /* 0: DW default, 1: Ideal */
 326                                 0);     /* No offset */
 327         lcnt = i2c_dw_scl_lcnt(input_clock_khz,
 328                                 13,     /* tLOW = 1.3 us */
 329                                 3,      /* tf = 0.3 us */
 330                                 0);     /* No offset */
 331         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 332         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 333         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 334
 335         /* Configure Tx/Rx FIFO threshold levels */
 336         dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
 337         dw_writel(dev, 0, DW_IC_RX_TL);
 338
 339         /* configure the i2c master */
 340         dw_writel(dev, dev->master_cfg , DW_IC_CON);
 341         return 0;
 342 }
 343 EXPORT_SYMBOL_GPL(i2c_dw_init);
 344
 345 /*
 346  * Waiting for bus not busy
 347  */
 348 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 349 {
 350         int timeout = TIMEOUT;
 351
 352         while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
 353                 if (timeout <= 0) {
 354                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 355                         return -ETIMEDOUT;
 356                 }
 357                 timeout--;
 358                 usleep_range(1000, 1100);
 359         }
 360
 361         return 0;
 362 }
 363
 364 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 365 {
 366         struct i2c_msg *msgs = dev->msgs;
 367         u32 ic_con;
 368
 369         /* Disable the adapter */
 370         __i2c_dw_enable(dev, false);
 371
 372         /* set the slave (target) address */
 373         dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
 374
 375         /* if the slave address is ten bit address, enable 10BITADDR */
 376         ic_con = dw_readl(dev, DW_IC_CON);
 377         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
 378                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 379         else
 380                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 381         dw_writel(dev, ic_con, DW_IC_CON);
 382
 383         /* Enable the adapter */
 384         __i2c_dw_enable(dev, true);
 385
 386         /* Clear and enable interrupts */
 387         i2c_dw_clear_int(dev);
 388         dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
 389 }
 390
 391 /*
 392  * Initiate (and continue) low level master read/write transaction.
 393  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 394  * messages into the tx buffer.  Even if the size of i2c_msg data is
 395  * longer than the size of the tx buffer, it handles everything.
 396  */
 397 static void
 398 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 399 {
 400         struct i2c_msg *msgs = dev->msgs;
 401         u32 intr_mask;
 402         int tx_limit, rx_limit;
 403         u32 addr = msgs[dev->msg_write_idx].addr;
 404         u32 buf_len = dev->tx_buf_len;
 405         u8 *buf = dev->tx_buf;
 406
 407         intr_mask = DW_IC_INTR_DEFAULT_MASK;
 408
 409         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 410                 /*
 411                  * if target address has changed, we need to
 412                  * reprogram the target address in the i2c
 413                  * adapter when we are done with this transfer
 414                  */
 415                 if (msgs[dev->msg_write_idx].addr != addr) {
 416                         dev_err(dev->dev,
 417                                 "%s: invalid target address\n", __func__);
 418                         dev->msg_err = -EINVAL;
 419                         break;
 420                 }
 421
 422                 if (msgs[dev->msg_write_idx].len == 0) {
 423                         dev_err(dev->dev,
 424                                 "%s: invalid message length\n", __func__);
 425                         dev->msg_err = -EINVAL;
 426                         break;
 427                 }
 428
 429                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 430                         /* new i2c_msg */
 431                         buf = msgs[dev->msg_write_idx].buf;
 432                         buf_len = msgs[dev->msg_write_idx].len;
 433                 }
 434
 435                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 436                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 437
 438                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 439                         u32 cmd = 0;
 440
 441                         /*
 442                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 443                          * manually set the stop bit. However, it cannot be
 444                          * detected from the registers so we set it always
 445                          * when writing/reading the last byte.
 446                          */
 447                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 448                             buf_len == 1)
 449                                 cmd |= BIT(9);
 450
 451                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 452
 453                                 /* avoid rx buffer overrun */
 454                                 if (rx_limit - dev->rx_outstanding <= 0)
 455                                         break;
 456
 457                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 458                                 rx_limit--;
 459                                 dev->rx_outstanding++;
 460                         } else
 461                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 462                         tx_limit--; buf_len--;
 463                 }
 464
 465                 dev->tx_buf = buf;
 466                 dev->tx_buf_len = buf_len;
 467
 468                 if (buf_len > 0) {
 469                         /* more bytes to be written */
 470                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 471                         break;
 472                 } else
 473                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 474         }
 475
 476         /*
 477          * If i2c_msg index search is completed, we don't need TX_EMPTY
 478          * interrupt any more.
 479          */
 480         if (dev->msg_write_idx == dev->msgs_num)
 481                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 482
 483         if (dev->msg_err)
 484                 intr_mask = 0;
 485
 486         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 487 }
 488
 489 static void
 490 i2c_dw_read(struct dw_i2c_dev *dev)
 491 {
 492         struct i2c_msg *msgs = dev->msgs;
 493         int rx_valid;
 494
 495         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 496                 u32 len;
 497                 u8 *buf;
 498
 499                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 500                         continue;
 501
 502                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 503                         len = msgs[dev->msg_read_idx].len;
 504                         buf = msgs[dev->msg_read_idx].buf;
 505                 } else {
 506                         len = dev->rx_buf_len;
 507                         buf = dev->rx_buf;
 508                 }
 509
 510                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 511
 512                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 513                         *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
 514                         dev->rx_outstanding--;
 515                 }
 516
 517                 if (len > 0) {
 518                         dev->status |= STATUS_READ_IN_PROGRESS;
 519                         dev->rx_buf_len = len;
 520                         dev->rx_buf = buf;
 521                         return;
 522                 } else
 523                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 524         }
 525 }
 526
 527 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
 528 {
 529         unsigned long abort_source = dev->abort_source;
 530         int i;
 531
 532         if (abort_source & DW_IC_TX_ABRT_NOACK) {
 533                 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 534                         dev_dbg(dev->dev,
 535                                 "%s: %s\n", __func__, abort_sources[i]);
 536                 return -EREMOTEIO;
 537         }
 538
 539         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 540                 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
 541
 542         if (abort_source & DW_IC_TX_ARB_LOST)
 543                 return -EAGAIN;
 544         else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
 545                 return -EINVAL; /* wrong msgs[] data */
 546         else
 547                 return -EIO;
 548 }
 549
 550 /*
 551  * Prepare controller for a transaction and call i2c_dw_xfer_msg
 552  */
 553 int
 554 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 555 {
 556         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 557         int ret;
 558
 559         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 560
 561         mutex_lock(&dev->lock);
 562         pm_runtime_get_sync(dev->dev);
 563
 564         INIT_COMPLETION(dev->cmd_complete);
 565         dev->msgs = msgs;
 566         dev->msgs_num = num;
 567         dev->cmd_err = 0;
 568         dev->msg_write_idx = 0;
 569         dev->msg_read_idx = 0;
 570         dev->msg_err = 0;
 571         dev->status = STATUS_IDLE;
 572         dev->abort_source = 0;
 573         dev->rx_outstanding = 0;
 574
 575         ret = i2c_dw_wait_bus_not_busy(dev);
 576         if (ret < 0)
 577                 goto done;
 578
 579         /* start the transfers */
 580         i2c_dw_xfer_init(dev);
 581
 582         /* wait for tx to complete */
 583         ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
 584         if (ret == 0) {
 585                 dev_err(dev->dev, "controller timed out\n");
 586                 i2c_dw_init(dev);
 587                 ret = -ETIMEDOUT;
 588                 goto done;
 589         } else if (ret < 0)
 590                 goto done;
 591
 592         if (dev->msg_err) {
 593                 ret = dev->msg_err;
 594                 goto done;
 595         }
 596
 597         /* no error */
 598         if (likely(!dev->cmd_err)) {
 599                 /* Disable the adapter */
 600                 __i2c_dw_enable(dev, false);
 601                 ret = num;
 602                 goto done;
 603         }
 604
 605         /* We have an error */
 606         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 607                 ret = i2c_dw_handle_tx_abort(dev);
 608                 goto done;
 609         }
 610         ret = -EIO;
 611
 612 done:
 613         pm_runtime_mark_last_busy(dev->dev);
 614         pm_runtime_put_autosuspend(dev->dev);
 615         mutex_unlock(&dev->lock);
 616
 617         return ret;
 618 }
 619 EXPORT_SYMBOL_GPL(i2c_dw_xfer);
 620
 621 u32 i2c_dw_func(struct i2c_adapter *adap)
 622 {
 623         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 624         return dev->functionality;
 625 }
 626 EXPORT_SYMBOL_GPL(i2c_dw_func);
 627
 628 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 629 {
 630         u32 stat;
 631
 632         /*
 633          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 634          * Ths unmasked raw version of interrupt status bits are available
 635          * in the IC_RAW_INTR_STAT register.
 636          *
 637          * That is,
 638          *   stat = dw_readl(IC_INTR_STAT);
 639          * equals to,
 640          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 641          *
 642          * The raw version might be useful for debugging purposes.
 643          */
 644         stat = dw_readl(dev, DW_IC_INTR_STAT);
 645
 646         /*
 647          * Do not use the IC_CLR_INTR register to clear interrupts, or
 648          * you'll miss some interrupts, triggered during the period from
 649          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 650          *
 651          * Instead, use the separately-prepared IC_CLR_* registers.
 652          */
 653         if (stat & DW_IC_INTR_RX_UNDER)
 654                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 655         if (stat & DW_IC_INTR_RX_OVER)
 656                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 657         if (stat & DW_IC_INTR_TX_OVER)
 658                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 659         if (stat & DW_IC_INTR_RD_REQ)
 660                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 661         if (stat & DW_IC_INTR_TX_ABRT) {
 662                 /*
 663                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 664                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 665                  */
 666                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 667                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 668         }
 669         if (stat & DW_IC_INTR_RX_DONE)
 670                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 671         if (stat & DW_IC_INTR_ACTIVITY)
 672                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 673         if (stat & DW_IC_INTR_STOP_DET)
 674                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 675         if (stat & DW_IC_INTR_START_DET)
 676                 dw_readl(dev, DW_IC_CLR_START_DET);
 677         if (stat & DW_IC_INTR_GEN_CALL)
 678                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 679
 680         return stat;
 681 }
 682
 683 /*
 684  * Interrupt service routine. This gets called whenever an I2C interrupt
 685  * occurs.
 686  */
 687 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 688 {
 689         struct dw_i2c_dev *dev = dev_id;
 690         u32 stat, enabled;
 691
 692         enabled = dw_readl(dev, DW_IC_ENABLE);
 693         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 694         dev_dbg(dev->dev, "%s:  %s enabled= 0x%x stat=0x%x\n", __func__,
 695                 dev->adapter.name, enabled, stat);
 696         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 697                 return IRQ_NONE;
 698
 699         stat = i2c_dw_read_clear_intrbits(dev);
 700
 701         if (stat & DW_IC_INTR_TX_ABRT) {
 702                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 703                 dev->status = STATUS_IDLE;
 704
 705                 /*
 706                  * Anytime TX_ABRT is set, the contents of the tx/rx
 707                  * buffers are flushed.  Make sure to skip them.
 708                  */
 709                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 710                 goto tx_aborted;
 711         }
 712
 713         if (stat & DW_IC_INTR_RX_FULL)
 714                 i2c_dw_read(dev);
 715
 716         if (stat & DW_IC_INTR_TX_EMPTY)
 717                 i2c_dw_xfer_msg(dev);
 718
 719         /*
 720          * No need to modify or disable the interrupt mask here.
 721          * i2c_dw_xfer_msg() will take care of it according to
 722          * the current transmit status.
 723          */
 724
 725 tx_aborted:
 726         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 727                 complete(&dev->cmd_complete);
 728
 729         return IRQ_HANDLED;
 730 }
 731 EXPORT_SYMBOL_GPL(i2c_dw_isr);
 732
 733 void i2c_dw_enable(struct dw_i2c_dev *dev)
 734 {
 735        /* Enable the adapter */
 736         __i2c_dw_enable(dev, true);
 737 }
 738 EXPORT_SYMBOL_GPL(i2c_dw_enable);
 739
 740 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
 741 {
 742         return dw_readl(dev, DW_IC_ENABLE);
 743 }
 744 EXPORT_SYMBOL_GPL(i2c_dw_is_enabled);
 745
 746 void i2c_dw_disable(struct dw_i2c_dev *dev)
 747 {
 748         /* Disable controller */
 749         __i2c_dw_enable(dev, false);
 750
 751         /* Disable all interupts */
 752         dw_writel(dev, 0, DW_IC_INTR_MASK);
 753         dw_readl(dev, DW_IC_CLR_INTR);
 754 }
 755 EXPORT_SYMBOL_GPL(i2c_dw_disable);
 756
 757 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
 758 {
 759         dw_readl(dev, DW_IC_CLR_INTR);
 760 }
 761 EXPORT_SYMBOL_GPL(i2c_dw_clear_int);
 762
 763 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
 764 {
 765         dw_writel(dev, 0, DW_IC_INTR_MASK);
 766 }
 767 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
 768
 769 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
 770 {
 771         return dw_readl(dev, DW_IC_COMP_PARAM_1);
 772 }
 773 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
 774
 775 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
 776 MODULE_LICENSE("GPL");