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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / i2c / busses / i2c-designware-core.c
1 /*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
26 *
27 */
28 #include <linux/clk.h>
29 #include <linux/errno.h>
30 #include <linux/err.h>
31 #include <linux/i2c.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/delay.h>
36 #include "i2c-designware-core.h"
37
38 /*
39 * Registers offset
40 */
41 #define DW_IC_CON 0x0
42 #define DW_IC_TAR 0x4
43 #define DW_IC_DATA_CMD 0x10
44 #define DW_IC_SS_SCL_HCNT 0x14
45 #define DW_IC_SS_SCL_LCNT 0x18
46 #define DW_IC_FS_SCL_HCNT 0x1c
47 #define DW_IC_FS_SCL_LCNT 0x20
48 #define DW_IC_INTR_STAT 0x2c
49 #define DW_IC_INTR_MASK 0x30
50 #define DW_IC_RAW_INTR_STAT 0x34
51 #define DW_IC_RX_TL 0x38
52 #define DW_IC_TX_TL 0x3c
53 #define DW_IC_CLR_INTR 0x40
54 #define DW_IC_CLR_RX_UNDER 0x44
55 #define DW_IC_CLR_RX_OVER 0x48
56 #define DW_IC_CLR_TX_OVER 0x4c
57 #define DW_IC_CLR_RD_REQ 0x50
58 #define DW_IC_CLR_TX_ABRT 0x54
59 #define DW_IC_CLR_RX_DONE 0x58
60 #define DW_IC_CLR_ACTIVITY 0x5c
61 #define DW_IC_CLR_STOP_DET 0x60
62 #define DW_IC_CLR_START_DET 0x64
63 #define DW_IC_CLR_GEN_CALL 0x68
64 #define DW_IC_ENABLE 0x6c
65 #define DW_IC_STATUS 0x70
66 #define DW_IC_TXFLR 0x74
67 #define DW_IC_RXFLR 0x78
68 #define DW_IC_TX_ABRT_SOURCE 0x80
69 #define DW_IC_COMP_PARAM_1 0xf4
70 #define DW_IC_COMP_TYPE 0xfc
71 #define DW_IC_COMP_TYPE_VALUE 0x44570140
72
73 #define DW_IC_INTR_RX_UNDER 0x001
74 #define DW_IC_INTR_RX_OVER 0x002
75 #define DW_IC_INTR_RX_FULL 0x004
76 #define DW_IC_INTR_TX_OVER 0x008
77 #define DW_IC_INTR_TX_EMPTY 0x010
78 #define DW_IC_INTR_RD_REQ 0x020
79 #define DW_IC_INTR_TX_ABRT 0x040
80 #define DW_IC_INTR_RX_DONE 0x080
81 #define DW_IC_INTR_ACTIVITY 0x100
82 #define DW_IC_INTR_STOP_DET 0x200
83 #define DW_IC_INTR_START_DET 0x400
84 #define DW_IC_INTR_GEN_CALL 0x800
85
86 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
87 DW_IC_INTR_TX_EMPTY | \
88 DW_IC_INTR_TX_ABRT | \
89 DW_IC_INTR_STOP_DET)
90
91 #define DW_IC_STATUS_ACTIVITY 0x1
92
93 #define DW_IC_ERR_TX_ABRT 0x1
94
95 /*
96 * status codes
97 */
98 #define STATUS_IDLE 0x0
99 #define STATUS_WRITE_IN_PROGRESS 0x1
100 #define STATUS_READ_IN_PROGRESS 0x2
101
102 #define TIMEOUT 20 /* ms */
103
104 /*
105 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
106 *
107 * only expected abort codes are listed here
108 * refer to the datasheet for the full list
109 */
110 #define ABRT_7B_ADDR_NOACK 0
111 #define ABRT_10ADDR1_NOACK 1
112 #define ABRT_10ADDR2_NOACK 2
113 #define ABRT_TXDATA_NOACK 3
114 #define ABRT_GCALL_NOACK 4
115 #define ABRT_GCALL_READ 5
116 #define ABRT_SBYTE_ACKDET 7
117 #define ABRT_SBYTE_NORSTRT 9
118 #define ABRT_10B_RD_NORSTRT 10
119 #define ABRT_MASTER_DIS 11
120 #define ARB_LOST 12
121
122 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
123 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
124 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
125 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
126 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
127 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
128 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
129 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
130 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
131 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
132 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
133
134 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
135 DW_IC_TX_ABRT_10ADDR1_NOACK | \
136 DW_IC_TX_ABRT_10ADDR2_NOACK | \
137 DW_IC_TX_ABRT_TXDATA_NOACK | \
138 DW_IC_TX_ABRT_GCALL_NOACK)
139
140 static char *abort_sources[] = {
141 [ABRT_7B_ADDR_NOACK] =
142 "slave address not acknowledged (7bit mode)",
143 [ABRT_10ADDR1_NOACK] =
144 "first address byte not acknowledged (10bit mode)",
145 [ABRT_10ADDR2_NOACK] =
146 "second address byte not acknowledged (10bit mode)",
147 [ABRT_TXDATA_NOACK] =
148 "data not acknowledged",
149 [ABRT_GCALL_NOACK] =
150 "no acknowledgement for a general call",
151 [ABRT_GCALL_READ] =
152 "read after general call",
153 [ABRT_SBYTE_ACKDET] =
154 "start byte acknowledged",
155 [ABRT_SBYTE_NORSTRT] =
156 "trying to send start byte when restart is disabled",
157 [ABRT_10B_RD_NORSTRT] =
158 "trying to read when restart is disabled (10bit mode)",
159 [ABRT_MASTER_DIS] =
160 "trying to use disabled adapter",
161 [ARB_LOST] =
162 "lost arbitration",
163 };
164
165 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
166 {
167 u32 value = readl(dev->base + offset);
168
169 if (dev->swab)
170 return swab32(value);
171 else
172 return value;
173 }
174
175 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
176 {
177 if (dev->swab)
178 b = swab32(b);
179
180 writel(b, dev->base + offset);
181 }
182
183 static u32
184 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
185 {
186 /*
187 * DesignWare I2C core doesn't seem to have solid strategy to meet
188 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
189 * will result in violation of the tHD;STA spec.
190 */
191 if (cond)
192 /*
193 * Conditional expression:
194 *
195 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
196 *
197 * This is based on the DW manuals, and represents an ideal
198 * configuration. The resulting I2C bus speed will be
199 * faster than any of the others.
200 *
201 * If your hardware is free from tHD;STA issue, try this one.
202 */
203 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
204 else
205 /*
206 * Conditional expression:
207 *
208 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
209 *
210 * This is just experimental rule; the tHD;STA period turned
211 * out to be proportinal to (_HCNT + 3). With this setting,
212 * we could meet both tHIGH and tHD;STA timing specs.
213 *
214 * If unsure, you'd better to take this alternative.
215 *
216 * The reason why we need to take into account "tf" here,
217 * is the same as described in i2c_dw_scl_lcnt().
218 */
219 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
220 }
221
222 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
223 {
224 /*
225 * Conditional expression:
226 *
227 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
228 *
229 * DW I2C core starts counting the SCL CNTs for the LOW period
230 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
231 * In order to meet the tLOW timing spec, we need to take into
232 * account the fall time of SCL signal (tf). Default tf value
233 * should be 0.3 us, for safety.
234 */
235 return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
236 }
237
238 /**
239 * i2c_dw_init() - initialize the designware i2c master hardware
240 * @dev: device private data
241 *
242 * This functions configures and enables the I2C master.
243 * This function is called during I2C init function, and in case of timeout at
244 * run time.
245 */
246 int i2c_dw_init(struct dw_i2c_dev *dev)
247 {
248 u32 input_clock_khz;
249 u32 hcnt, lcnt;
250 u32 reg;
251
252 input_clock_khz = dev->get_clk_rate_khz(dev);
253
254 /* Configure register endianess access */
255 reg = dw_readl(dev, DW_IC_COMP_TYPE);
256 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
257 dev->swab = 1;
258 reg = DW_IC_COMP_TYPE_VALUE;
259 }
260
261 if (reg != DW_IC_COMP_TYPE_VALUE) {
262 dev_err(dev->dev, "Unknown Synopsys component type: "
263 "0x%08x\n", reg);
264 return -ENODEV;
265 }
266
267 /* Disable the adapter */
268 dw_writel(dev, 0, DW_IC_ENABLE);
269
270 /* set standard and fast speed deviders for high/low periods */
271
272 /* Standard-mode */
273 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
274 40, /* tHD;STA = tHIGH = 4.0 us */
275 3, /* tf = 0.3 us */
276 0, /* 0: DW default, 1: Ideal */
277 0); /* No offset */
278 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
279 47, /* tLOW = 4.7 us */
280 3, /* tf = 0.3 us */
281 0); /* No offset */
282 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
283 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
284 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
285
286 /* Fast-mode */
287 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
288 6, /* tHD;STA = tHIGH = 0.6 us */
289 3, /* tf = 0.3 us */
290 0, /* 0: DW default, 1: Ideal */
291 0); /* No offset */
292 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
293 13, /* tLOW = 1.3 us */
294 3, /* tf = 0.3 us */
295 0); /* No offset */
296 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
297 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
298 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
299
300 /* Configure Tx/Rx FIFO threshold levels */
301 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
302 dw_writel(dev, 0, DW_IC_RX_TL);
303
304 /* configure the i2c master */
305 dw_writel(dev, dev->master_cfg , DW_IC_CON);
306 return 0;
307 }
308
309 /*
310 * Waiting for bus not busy
311 */
312 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
313 {
314 int timeout = TIMEOUT;
315
316 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
317 if (timeout <= 0) {
318 dev_warn(dev->dev, "timeout waiting for bus ready\n");
319 return -ETIMEDOUT;
320 }
321 timeout--;
322 mdelay(1);
323 }
324
325 return 0;
326 }
327
328 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
329 {
330 struct i2c_msg *msgs = dev->msgs;
331 u32 ic_con;
332
333 /* Disable the adapter */
334 dw_writel(dev, 0, DW_IC_ENABLE);
335
336 /* set the slave (target) address */
337 dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
338
339 /* if the slave address is ten bit address, enable 10BITADDR */
340 ic_con = dw_readl(dev, DW_IC_CON);
341 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
342 ic_con |= DW_IC_CON_10BITADDR_MASTER;
343 else
344 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
345 dw_writel(dev, ic_con, DW_IC_CON);
346
347 /* Enable the adapter */
348 dw_writel(dev, 1, DW_IC_ENABLE);
349
350 /* Enable interrupts */
351 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
352 }
353
354 /*
355 * Initiate (and continue) low level master read/write transaction.
356 * This function is only called from i2c_dw_isr, and pumping i2c_msg
357 * messages into the tx buffer. Even if the size of i2c_msg data is
358 * longer than the size of the tx buffer, it handles everything.
359 */
360 void
361 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
362 {
363 struct i2c_msg *msgs = dev->msgs;
364 u32 intr_mask;
365 int tx_limit, rx_limit;
366 u32 addr = msgs[dev->msg_write_idx].addr;
367 u32 buf_len = dev->tx_buf_len;
368 u8 *buf = dev->tx_buf;
369
370 intr_mask = DW_IC_INTR_DEFAULT_MASK;
371
372 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
373 /*
374 * if target address has changed, we need to
375 * reprogram the target address in the i2c
376 * adapter when we are done with this transfer
377 */
378 if (msgs[dev->msg_write_idx].addr != addr) {
379 dev_err(dev->dev,
380 "%s: invalid target address\n", __func__);
381 dev->msg_err = -EINVAL;
382 break;
383 }
384
385 if (msgs[dev->msg_write_idx].len == 0) {
386 dev_err(dev->dev,
387 "%s: invalid message length\n", __func__);
388 dev->msg_err = -EINVAL;
389 break;
390 }
391
392 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
393 /* new i2c_msg */
394 buf = msgs[dev->msg_write_idx].buf;
395 buf_len = msgs[dev->msg_write_idx].len;
396 }
397
398 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
399 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
400
401 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
402 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
403 dw_writel(dev, 0x100, DW_IC_DATA_CMD);
404 rx_limit--;
405 } else
406 dw_writel(dev, *buf++, DW_IC_DATA_CMD);
407 tx_limit--; buf_len--;
408 }
409
410 dev->tx_buf = buf;
411 dev->tx_buf_len = buf_len;
412
413 if (buf_len > 0) {
414 /* more bytes to be written */
415 dev->status |= STATUS_WRITE_IN_PROGRESS;
416 break;
417 } else
418 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
419 }
420
421 /*
422 * If i2c_msg index search is completed, we don't need TX_EMPTY
423 * interrupt any more.
424 */
425 if (dev->msg_write_idx == dev->msgs_num)
426 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
427
428 if (dev->msg_err)
429 intr_mask = 0;
430
431 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
432 }
433
434 static void
435 i2c_dw_read(struct dw_i2c_dev *dev)
436 {
437 struct i2c_msg *msgs = dev->msgs;
438 int rx_valid;
439
440 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
441 u32 len;
442 u8 *buf;
443
444 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
445 continue;
446
447 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
448 len = msgs[dev->msg_read_idx].len;
449 buf = msgs[dev->msg_read_idx].buf;
450 } else {
451 len = dev->rx_buf_len;
452 buf = dev->rx_buf;
453 }
454
455 rx_valid = dw_readl(dev, DW_IC_RXFLR);
456
457 for (; len > 0 && rx_valid > 0; len--, rx_valid--)
458 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
459
460 if (len > 0) {
461 dev->status |= STATUS_READ_IN_PROGRESS;
462 dev->rx_buf_len = len;
463 dev->rx_buf = buf;
464 return;
465 } else
466 dev->status &= ~STATUS_READ_IN_PROGRESS;
467 }
468 }
469
470 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
471 {
472 unsigned long abort_source = dev->abort_source;
473 int i;
474
475 if (abort_source & DW_IC_TX_ABRT_NOACK) {
476 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
477 dev_dbg(dev->dev,
478 "%s: %s\n", __func__, abort_sources[i]);
479 return -EREMOTEIO;
480 }
481
482 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
483 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
484
485 if (abort_source & DW_IC_TX_ARB_LOST)
486 return -EAGAIN;
487 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
488 return -EINVAL; /* wrong msgs[] data */
489 else
490 return -EIO;
491 }
492
493 /*
494 * Prepare controller for a transaction and call i2c_dw_xfer_msg
495 */
496 int
497 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
498 {
499 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
500 int ret;
501
502 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
503
504 mutex_lock(&dev->lock);
505 pm_runtime_get_sync(dev->dev);
506
507 INIT_COMPLETION(dev->cmd_complete);
508 dev->msgs = msgs;
509 dev->msgs_num = num;
510 dev->cmd_err = 0;
511 dev->msg_write_idx = 0;
512 dev->msg_read_idx = 0;
513 dev->msg_err = 0;
514 dev->status = STATUS_IDLE;
515 dev->abort_source = 0;
516
517 ret = i2c_dw_wait_bus_not_busy(dev);
518 if (ret < 0)
519 goto done;
520
521 /* start the transfers */
522 i2c_dw_xfer_init(dev);
523
524 /* wait for tx to complete */
525 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
526 if (ret == 0) {
527 dev_err(dev->dev, "controller timed out\n");
528 i2c_dw_init(dev);
529 ret = -ETIMEDOUT;
530 goto done;
531 } else if (ret < 0)
532 goto done;
533
534 if (dev->msg_err) {
535 ret = dev->msg_err;
536 goto done;
537 }
538
539 /* no error */
540 if (likely(!dev->cmd_err)) {
541 /* Disable the adapter */
542 dw_writel(dev, 0, DW_IC_ENABLE);
543 ret = num;
544 goto done;
545 }
546
547 /* We have an error */
548 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
549 ret = i2c_dw_handle_tx_abort(dev);
550 goto done;
551 }
552 ret = -EIO;
553
554 done:
555 pm_runtime_put(dev->dev);
556 mutex_unlock(&dev->lock);
557
558 return ret;
559 }
560
561 u32 i2c_dw_func(struct i2c_adapter *adap)
562 {
563 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
564 return dev->functionality;
565 }
566
567 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
568 {
569 u32 stat;
570
571 /*
572 * The IC_INTR_STAT register just indicates "enabled" interrupts.
573 * Ths unmasked raw version of interrupt status bits are available
574 * in the IC_RAW_INTR_STAT register.
575 *
576 * That is,
577 * stat = dw_readl(IC_INTR_STAT);
578 * equals to,
579 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
580 *
581 * The raw version might be useful for debugging purposes.
582 */
583 stat = dw_readl(dev, DW_IC_INTR_STAT);
584
585 /*
586 * Do not use the IC_CLR_INTR register to clear interrupts, or
587 * you'll miss some interrupts, triggered during the period from
588 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
589 *
590 * Instead, use the separately-prepared IC_CLR_* registers.
591 */
592 if (stat & DW_IC_INTR_RX_UNDER)
593 dw_readl(dev, DW_IC_CLR_RX_UNDER);
594 if (stat & DW_IC_INTR_RX_OVER)
595 dw_readl(dev, DW_IC_CLR_RX_OVER);
596 if (stat & DW_IC_INTR_TX_OVER)
597 dw_readl(dev, DW_IC_CLR_TX_OVER);
598 if (stat & DW_IC_INTR_RD_REQ)
599 dw_readl(dev, DW_IC_CLR_RD_REQ);
600 if (stat & DW_IC_INTR_TX_ABRT) {
601 /*
602 * The IC_TX_ABRT_SOURCE register is cleared whenever
603 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
604 */
605 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
606 dw_readl(dev, DW_IC_CLR_TX_ABRT);
607 }
608 if (stat & DW_IC_INTR_RX_DONE)
609 dw_readl(dev, DW_IC_CLR_RX_DONE);
610 if (stat & DW_IC_INTR_ACTIVITY)
611 dw_readl(dev, DW_IC_CLR_ACTIVITY);
612 if (stat & DW_IC_INTR_STOP_DET)
613 dw_readl(dev, DW_IC_CLR_STOP_DET);
614 if (stat & DW_IC_INTR_START_DET)
615 dw_readl(dev, DW_IC_CLR_START_DET);
616 if (stat & DW_IC_INTR_GEN_CALL)
617 dw_readl(dev, DW_IC_CLR_GEN_CALL);
618
619 return stat;
620 }
621
622 /*
623 * Interrupt service routine. This gets called whenever an I2C interrupt
624 * occurs.
625 */
626 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
627 {
628 struct dw_i2c_dev *dev = dev_id;
629 u32 stat, enabled;
630
631 enabled = dw_readl(dev, DW_IC_ENABLE);
632 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
633 dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
634 dev->adapter.name, enabled, stat);
635 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
636 return IRQ_NONE;
637
638 stat = i2c_dw_read_clear_intrbits(dev);
639
640 if (stat & DW_IC_INTR_TX_ABRT) {
641 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
642 dev->status = STATUS_IDLE;
643
644 /*
645 * Anytime TX_ABRT is set, the contents of the tx/rx
646 * buffers are flushed. Make sure to skip them.
647 */
648 dw_writel(dev, 0, DW_IC_INTR_MASK);
649 goto tx_aborted;
650 }
651
652 if (stat & DW_IC_INTR_RX_FULL)
653 i2c_dw_read(dev);
654
655 if (stat & DW_IC_INTR_TX_EMPTY)
656 i2c_dw_xfer_msg(dev);
657
658 /*
659 * No need to modify or disable the interrupt mask here.
660 * i2c_dw_xfer_msg() will take care of it according to
661 * the current transmit status.
662 */
663
664 tx_aborted:
665 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
666 complete(&dev->cmd_complete);
667
668 return IRQ_HANDLED;
669 }
670
671 void i2c_dw_enable(struct dw_i2c_dev *dev)
672 {
673 /* Enable the adapter */
674 dw_writel(dev, 1, DW_IC_ENABLE);
675 }
676
677 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
678 {
679 return dw_readl(dev, DW_IC_ENABLE);
680 }
681
682 void i2c_dw_disable(struct dw_i2c_dev *dev)
683 {
684 /* Disable controller */
685 dw_writel(dev, 0, DW_IC_ENABLE);
686
687 /* Disable all interupts */
688 dw_writel(dev, 0, DW_IC_INTR_MASK);
689 dw_readl(dev, DW_IC_CLR_INTR);
690 }
691
692 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
693 {
694 dw_readl(dev, DW_IC_CLR_INTR);
695 }
696
697 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
698 {
699 dw_writel(dev, 0, DW_IC_INTR_MASK);
700 }
701
702 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
703 {
704 return dw_readl(dev, DW_IC_COMP_PARAM_1);
705 }
kernel source for telekom puls (alcatel/mediatek)