drivers/i2c/busses/i2c-designware-core.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  * ----------------------------------------------------------------------------
  26  *
  27  */
  28 #include <linux/clk.h>
  29 #include <linux/errno.h>
  30 #include <linux/err.h>
  31 #include <linux/i2c.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/delay.h>
  36 #include "i2c-designware-core.h"
  37
  38 /*
  39  * Registers offset
  40  */
  41 #define DW_IC_CON               0x0
  42 #define DW_IC_TAR               0x4
  43 #define DW_IC_DATA_CMD          0x10
  44 #define DW_IC_SS_SCL_HCNT       0x14
  45 #define DW_IC_SS_SCL_LCNT       0x18
  46 #define DW_IC_FS_SCL_HCNT       0x1c
  47 #define DW_IC_FS_SCL_LCNT       0x20
  48 #define DW_IC_INTR_STAT         0x2c
  49 #define DW_IC_INTR_MASK         0x30
  50 #define DW_IC_RAW_INTR_STAT     0x34
  51 #define DW_IC_RX_TL             0x38
  52 #define DW_IC_TX_TL             0x3c
  53 #define DW_IC_CLR_INTR          0x40
  54 #define DW_IC_CLR_RX_UNDER      0x44
  55 #define DW_IC_CLR_RX_OVER       0x48
  56 #define DW_IC_CLR_TX_OVER       0x4c
  57 #define DW_IC_CLR_RD_REQ        0x50
  58 #define DW_IC_CLR_TX_ABRT       0x54
  59 #define DW_IC_CLR_RX_DONE       0x58
  60 #define DW_IC_CLR_ACTIVITY      0x5c
  61 #define DW_IC_CLR_STOP_DET      0x60
  62 #define DW_IC_CLR_START_DET     0x64
  63 #define DW_IC_CLR_GEN_CALL      0x68
  64 #define DW_IC_ENABLE            0x6c
  65 #define DW_IC_STATUS            0x70
  66 #define DW_IC_TXFLR             0x74
  67 #define DW_IC_RXFLR             0x78
  68 #define DW_IC_TX_ABRT_SOURCE    0x80
  69 #define DW_IC_COMP_PARAM_1      0xf4
  70 #define DW_IC_COMP_TYPE         0xfc
  71 #define DW_IC_COMP_TYPE_VALUE   0x44570140
  72
  73 #define DW_IC_INTR_RX_UNDER     0x001
  74 #define DW_IC_INTR_RX_OVER      0x002
  75 #define DW_IC_INTR_RX_FULL      0x004
  76 #define DW_IC_INTR_TX_OVER      0x008
  77 #define DW_IC_INTR_TX_EMPTY     0x010
  78 #define DW_IC_INTR_RD_REQ       0x020
  79 #define DW_IC_INTR_TX_ABRT      0x040
  80 #define DW_IC_INTR_RX_DONE      0x080
  81 #define DW_IC_INTR_ACTIVITY     0x100
  82 #define DW_IC_INTR_STOP_DET     0x200
  83 #define DW_IC_INTR_START_DET    0x400
  84 #define DW_IC_INTR_GEN_CALL     0x800
  85
  86 #define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
  87                                          DW_IC_INTR_TX_EMPTY | \
  88                                          DW_IC_INTR_TX_ABRT | \
  89                                          DW_IC_INTR_STOP_DET)
  90
  91 #define DW_IC_STATUS_ACTIVITY   0x1
  92
  93 #define DW_IC_ERR_TX_ABRT       0x1
  94
  95 /*
  96  * status codes
  97  */
  98 #define STATUS_IDLE                     0x0
  99 #define STATUS_WRITE_IN_PROGRESS        0x1
 100 #define STATUS_READ_IN_PROGRESS         0x2
 101
 102 #define TIMEOUT                 20 /* ms */
 103
 104 /*
 105  * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 106  *
 107  * only expected abort codes are listed here
 108  * refer to the datasheet for the full list
 109  */
 110 #define ABRT_7B_ADDR_NOACK      0
 111 #define ABRT_10ADDR1_NOACK      1
 112 #define ABRT_10ADDR2_NOACK      2
 113 #define ABRT_TXDATA_NOACK       3
 114 #define ABRT_GCALL_NOACK        4
 115 #define ABRT_GCALL_READ         5
 116 #define ABRT_SBYTE_ACKDET       7
 117 #define ABRT_SBYTE_NORSTRT      9
 118 #define ABRT_10B_RD_NORSTRT     10
 119 #define ABRT_MASTER_DIS         11
 120 #define ARB_LOST                12
 121
 122 #define DW_IC_TX_ABRT_7B_ADDR_NOACK     (1UL << ABRT_7B_ADDR_NOACK)
 123 #define DW_IC_TX_ABRT_10ADDR1_NOACK     (1UL << ABRT_10ADDR1_NOACK)
 124 #define DW_IC_TX_ABRT_10ADDR2_NOACK     (1UL << ABRT_10ADDR2_NOACK)
 125 #define DW_IC_TX_ABRT_TXDATA_NOACK      (1UL << ABRT_TXDATA_NOACK)
 126 #define DW_IC_TX_ABRT_GCALL_NOACK       (1UL << ABRT_GCALL_NOACK)
 127 #define DW_IC_TX_ABRT_GCALL_READ        (1UL << ABRT_GCALL_READ)
 128 #define DW_IC_TX_ABRT_SBYTE_ACKDET      (1UL << ABRT_SBYTE_ACKDET)
 129 #define DW_IC_TX_ABRT_SBYTE_NORSTRT     (1UL << ABRT_SBYTE_NORSTRT)
 130 #define DW_IC_TX_ABRT_10B_RD_NORSTRT    (1UL << ABRT_10B_RD_NORSTRT)
 131 #define DW_IC_TX_ABRT_MASTER_DIS        (1UL << ABRT_MASTER_DIS)
 132 #define DW_IC_TX_ARB_LOST               (1UL << ARB_LOST)
 133
 134 #define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 135                                          DW_IC_TX_ABRT_10ADDR1_NOACK | \
 136                                          DW_IC_TX_ABRT_10ADDR2_NOACK | \
 137                                          DW_IC_TX_ABRT_TXDATA_NOACK | \
 138                                          DW_IC_TX_ABRT_GCALL_NOACK)
 139
 140 static char *abort_sources[] = {
 141         [ABRT_7B_ADDR_NOACK] =
 142                 "slave address not acknowledged (7bit mode)",
 143         [ABRT_10ADDR1_NOACK] =
 144                 "first address byte not acknowledged (10bit mode)",
 145         [ABRT_10ADDR2_NOACK] =
 146                 "second address byte not acknowledged (10bit mode)",
 147         [ABRT_TXDATA_NOACK] =
 148                 "data not acknowledged",
 149         [ABRT_GCALL_NOACK] =
 150                 "no acknowledgement for a general call",
 151         [ABRT_GCALL_READ] =
 152                 "read after general call",
 153         [ABRT_SBYTE_ACKDET] =
 154                 "start byte acknowledged",
 155         [ABRT_SBYTE_NORSTRT] =
 156                 "trying to send start byte when restart is disabled",
 157         [ABRT_10B_RD_NORSTRT] =
 158                 "trying to read when restart is disabled (10bit mode)",
 159         [ABRT_MASTER_DIS] =
 160                 "trying to use disabled adapter",
 161         [ARB_LOST] =
 162                 "lost arbitration",
 163 };
 164
 165 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
 166 {
 167         u32 value;
 168
 169         if (dev->accessor_flags & ACCESS_16BIT)
 170                 value = readw(dev->base + offset) |
 171                         (readw(dev->base + offset + 2) << 16);
 172         else
 173                 value = readl(dev->base + offset);
 174
 175         if (dev->accessor_flags & ACCESS_SWAP)
 176                 return swab32(value);
 177         else
 178                 return value;
 179 }
 180
 181 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
 182 {
 183         if (dev->accessor_flags & ACCESS_SWAP)
 184                 b = swab32(b);
 185
 186         if (dev->accessor_flags & ACCESS_16BIT) {
 187                 writew((u16)b, dev->base + offset);
 188                 writew((u16)(b >> 16), dev->base + offset + 2);
 189         } else {
 190                 writel(b, dev->base + offset);
 191         }
 192 }
 193
 194 static u32
 195 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
 196 {
 197         /*
 198          * DesignWare I2C core doesn't seem to have solid strategy to meet
 199          * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
 200          * will result in violation of the tHD;STA spec.
 201          */
 202         if (cond)
 203                 /*
 204                  * Conditional expression:
 205                  *
 206                  *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
 207                  *
 208                  * This is based on the DW manuals, and represents an ideal
 209                  * configuration.  The resulting I2C bus speed will be
 210                  * faster than any of the others.
 211                  *
 212                  * If your hardware is free from tHD;STA issue, try this one.
 213                  */
 214                 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
 215         else
 216                 /*
 217                  * Conditional expression:
 218                  *
 219                  *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
 220                  *
 221                  * This is just experimental rule; the tHD;STA period turned
 222                  * out to be proportinal to (_HCNT + 3).  With this setting,
 223                  * we could meet both tHIGH and tHD;STA timing specs.
 224                  *
 225                  * If unsure, you'd better to take this alternative.
 226                  *
 227                  * The reason why we need to take into account "tf" here,
 228                  * is the same as described in i2c_dw_scl_lcnt().
 229                  */
 230                 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
 231 }
 232
 233 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
 234 {
 235         /*
 236          * Conditional expression:
 237          *
 238          *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
 239          *
 240          * DW I2C core starts counting the SCL CNTs for the LOW period
 241          * of the SCL clock (tLOW) as soon as it pulls the SCL line.
 242          * In order to meet the tLOW timing spec, we need to take into
 243          * account the fall time of SCL signal (tf).  Default tf value
 244          * should be 0.3 us, for safety.
 245          */
 246         return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
 247 }
 248
 249 /**
 250  * i2c_dw_init() - initialize the designware i2c master hardware
 251  * @dev: device private data
 252  *
 253  * This functions configures and enables the I2C master.
 254  * This function is called during I2C init function, and in case of timeout at
 255  * run time.
 256  */
 257 int i2c_dw_init(struct dw_i2c_dev *dev)
 258 {
 259         u32 input_clock_khz;
 260         u32 hcnt, lcnt;
 261         u32 reg;
 262
 263         input_clock_khz = dev->get_clk_rate_khz(dev);
 264
 265         reg = dw_readl(dev, DW_IC_COMP_TYPE);
 266         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
 267                 /* Configure register endianess access */
 268                 dev->accessor_flags |= ACCESS_SWAP;
 269         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
 270                 /* Configure register access mode 16bit */
 271                 dev->accessor_flags |= ACCESS_16BIT;
 272         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
 273                 dev_err(dev->dev, "Unknown Synopsys component type: "
 274                         "0x%08x\n", reg);
 275                 return -ENODEV;
 276         }
 277
 278         /* Disable the adapter */
 279         dw_writel(dev, 0, DW_IC_ENABLE);
 280
 281         /* set standard and fast speed deviders for high/low periods */
 282
 283         /* Standard-mode */
 284         hcnt = i2c_dw_scl_hcnt(input_clock_khz,
 285                                 40,     /* tHD;STA = tHIGH = 4.0 us */
 286                                 3,      /* tf = 0.3 us */
 287                                 0,      /* 0: DW default, 1: Ideal */
 288                                 0);     /* No offset */
 289         lcnt = i2c_dw_scl_lcnt(input_clock_khz,
 290                                 47,     /* tLOW = 4.7 us */
 291                                 3,      /* tf = 0.3 us */
 292                                 0);     /* No offset */
 293         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 294         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 295         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 296
 297         /* Fast-mode */
 298         hcnt = i2c_dw_scl_hcnt(input_clock_khz,
 299                                 6,      /* tHD;STA = tHIGH = 0.6 us */
 300                                 3,      /* tf = 0.3 us */
 301                                 0,      /* 0: DW default, 1: Ideal */
 302                                 0);     /* No offset */
 303         lcnt = i2c_dw_scl_lcnt(input_clock_khz,
 304                                 13,     /* tLOW = 1.3 us */
 305                                 3,      /* tf = 0.3 us */
 306                                 0);     /* No offset */
 307         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 308         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 309         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 310
 311         /* Configure Tx/Rx FIFO threshold levels */
 312         dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
 313         dw_writel(dev, 0, DW_IC_RX_TL);
 314
 315         /* configure the i2c master */
 316         dw_writel(dev, dev->master_cfg , DW_IC_CON);
 317         return 0;
 318 }
 319
 320 /*
 321  * Waiting for bus not busy
 322  */
 323 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 324 {
 325         int timeout = TIMEOUT;
 326
 327         while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
 328                 if (timeout <= 0) {
 329                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 330                         return -ETIMEDOUT;
 331                 }
 332                 timeout--;
 333                 mdelay(1);
 334         }
 335
 336         return 0;
 337 }
 338
 339 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 340 {
 341         struct i2c_msg *msgs = dev->msgs;
 342         u32 ic_con;
 343
 344         /* Disable the adapter */
 345         dw_writel(dev, 0, DW_IC_ENABLE);
 346
 347         /* set the slave (target) address */
 348         dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
 349
 350         /* if the slave address is ten bit address, enable 10BITADDR */
 351         ic_con = dw_readl(dev, DW_IC_CON);
 352         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
 353                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 354         else
 355                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 356         dw_writel(dev, ic_con, DW_IC_CON);
 357
 358         /* Enable the adapter */
 359         dw_writel(dev, 1, DW_IC_ENABLE);
 360
 361         /* Enable interrupts */
 362         dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
 363 }
 364
 365 /*
 366  * Initiate (and continue) low level master read/write transaction.
 367  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 368  * messages into the tx buffer.  Even if the size of i2c_msg data is
 369  * longer than the size of the tx buffer, it handles everything.
 370  */
 371 void
 372 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 373 {
 374         struct i2c_msg *msgs = dev->msgs;
 375         u32 intr_mask;
 376         int tx_limit, rx_limit;
 377         u32 addr = msgs[dev->msg_write_idx].addr;
 378         u32 buf_len = dev->tx_buf_len;
 379         u8 *buf = dev->tx_buf;
 380
 381         intr_mask = DW_IC_INTR_DEFAULT_MASK;
 382
 383         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 384                 /*
 385                  * if target address has changed, we need to
 386                  * reprogram the target address in the i2c
 387                  * adapter when we are done with this transfer
 388                  */
 389                 if (msgs[dev->msg_write_idx].addr != addr) {
 390                         dev_err(dev->dev,
 391                                 "%s: invalid target address\n", __func__);
 392                         dev->msg_err = -EINVAL;
 393                         break;
 394                 }
 395
 396                 if (msgs[dev->msg_write_idx].len == 0) {
 397                         dev_err(dev->dev,
 398                                 "%s: invalid message length\n", __func__);
 399                         dev->msg_err = -EINVAL;
 400                         break;
 401                 }
 402
 403                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 404                         /* new i2c_msg */
 405                         buf = msgs[dev->msg_write_idx].buf;
 406                         buf_len = msgs[dev->msg_write_idx].len;
 407                 }
 408
 409                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 410                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 411
 412                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 413                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 414                                 dw_writel(dev, 0x100, DW_IC_DATA_CMD);
 415                                 rx_limit--;
 416                         } else
 417                                 dw_writel(dev, *buf++, DW_IC_DATA_CMD);
 418                         tx_limit--; buf_len--;
 419                 }
 420
 421                 dev->tx_buf = buf;
 422                 dev->tx_buf_len = buf_len;
 423
 424                 if (buf_len > 0) {
 425                         /* more bytes to be written */
 426                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 427                         break;
 428                 } else
 429                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 430         }
 431
 432         /*
 433          * If i2c_msg index search is completed, we don't need TX_EMPTY
 434          * interrupt any more.
 435          */
 436         if (dev->msg_write_idx == dev->msgs_num)
 437                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 438
 439         if (dev->msg_err)
 440                 intr_mask = 0;
 441
 442         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 443 }
 444
 445 static void
 446 i2c_dw_read(struct dw_i2c_dev *dev)
 447 {
 448         struct i2c_msg *msgs = dev->msgs;
 449         int rx_valid;
 450
 451         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 452                 u32 len;
 453                 u8 *buf;
 454
 455                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 456                         continue;
 457
 458                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 459                         len = msgs[dev->msg_read_idx].len;
 460                         buf = msgs[dev->msg_read_idx].buf;
 461                 } else {
 462                         len = dev->rx_buf_len;
 463                         buf = dev->rx_buf;
 464                 }
 465
 466                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 467
 468                 for (; len > 0 && rx_valid > 0; len--, rx_valid--)
 469                         *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
 470
 471                 if (len > 0) {
 472                         dev->status |= STATUS_READ_IN_PROGRESS;
 473                         dev->rx_buf_len = len;
 474                         dev->rx_buf = buf;
 475                         return;
 476                 } else
 477                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 478         }
 479 }
 480
 481 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
 482 {
 483         unsigned long abort_source = dev->abort_source;
 484         int i;
 485
 486         if (abort_source & DW_IC_TX_ABRT_NOACK) {
 487                 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 488                         dev_dbg(dev->dev,
 489                                 "%s: %s\n", __func__, abort_sources[i]);
 490                 return -EREMOTEIO;
 491         }
 492
 493         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 494                 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
 495
 496         if (abort_source & DW_IC_TX_ARB_LOST)
 497                 return -EAGAIN;
 498         else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
 499                 return -EINVAL; /* wrong msgs[] data */
 500         else
 501                 return -EIO;
 502 }
 503
 504 /*
 505  * Prepare controller for a transaction and call i2c_dw_xfer_msg
 506  */
 507 int
 508 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 509 {
 510         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 511         int ret;
 512
 513         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 514
 515         mutex_lock(&dev->lock);
 516         pm_runtime_get_sync(dev->dev);
 517
 518         INIT_COMPLETION(dev->cmd_complete);
 519         dev->msgs = msgs;
 520         dev->msgs_num = num;
 521         dev->cmd_err = 0;
 522         dev->msg_write_idx = 0;
 523         dev->msg_read_idx = 0;
 524         dev->msg_err = 0;
 525         dev->status = STATUS_IDLE;
 526         dev->abort_source = 0;
 527
 528         ret = i2c_dw_wait_bus_not_busy(dev);
 529         if (ret < 0)
 530                 goto done;
 531
 532         /* start the transfers */
 533         i2c_dw_xfer_init(dev);
 534
 535         /* wait for tx to complete */
 536         ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
 537         if (ret == 0) {
 538                 dev_err(dev->dev, "controller timed out\n");
 539                 i2c_dw_init(dev);
 540                 ret = -ETIMEDOUT;
 541                 goto done;
 542         } else if (ret < 0)
 543                 goto done;
 544
 545         if (dev->msg_err) {
 546                 ret = dev->msg_err;
 547                 goto done;
 548         }
 549
 550         /* no error */
 551         if (likely(!dev->cmd_err)) {
 552                 /* Disable the adapter */
 553                 dw_writel(dev, 0, DW_IC_ENABLE);
 554                 ret = num;
 555                 goto done;
 556         }
 557
 558         /* We have an error */
 559         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 560                 ret = i2c_dw_handle_tx_abort(dev);
 561                 goto done;
 562         }
 563         ret = -EIO;
 564
 565 done:
 566         pm_runtime_put(dev->dev);
 567         mutex_unlock(&dev->lock);
 568
 569         return ret;
 570 }
 571
 572 u32 i2c_dw_func(struct i2c_adapter *adap)
 573 {
 574         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 575         return dev->functionality;
 576 }
 577
 578 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 579 {
 580         u32 stat;
 581
 582         /*
 583          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 584          * Ths unmasked raw version of interrupt status bits are available
 585          * in the IC_RAW_INTR_STAT register.
 586          *
 587          * That is,
 588          *   stat = dw_readl(IC_INTR_STAT);
 589          * equals to,
 590          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 591          *
 592          * The raw version might be useful for debugging purposes.
 593          */
 594         stat = dw_readl(dev, DW_IC_INTR_STAT);
 595
 596         /*
 597          * Do not use the IC_CLR_INTR register to clear interrupts, or
 598          * you'll miss some interrupts, triggered during the period from
 599          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 600          *
 601          * Instead, use the separately-prepared IC_CLR_* registers.
 602          */
 603         if (stat & DW_IC_INTR_RX_UNDER)
 604                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 605         if (stat & DW_IC_INTR_RX_OVER)
 606                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 607         if (stat & DW_IC_INTR_TX_OVER)
 608                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 609         if (stat & DW_IC_INTR_RD_REQ)
 610                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 611         if (stat & DW_IC_INTR_TX_ABRT) {
 612                 /*
 613                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 614                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 615                  */
 616                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 617                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 618         }
 619         if (stat & DW_IC_INTR_RX_DONE)
 620                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 621         if (stat & DW_IC_INTR_ACTIVITY)
 622                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 623         if (stat & DW_IC_INTR_STOP_DET)
 624                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 625         if (stat & DW_IC_INTR_START_DET)
 626                 dw_readl(dev, DW_IC_CLR_START_DET);
 627         if (stat & DW_IC_INTR_GEN_CALL)
 628                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 629
 630         return stat;
 631 }
 632
 633 /*
 634  * Interrupt service routine. This gets called whenever an I2C interrupt
 635  * occurs.
 636  */
 637 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 638 {
 639         struct dw_i2c_dev *dev = dev_id;
 640         u32 stat, enabled;
 641
 642         enabled = dw_readl(dev, DW_IC_ENABLE);
 643         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 644         dev_dbg(dev->dev, "%s:  %s enabled= 0x%x stat=0x%x\n", __func__,
 645                 dev->adapter.name, enabled, stat);
 646         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 647                 return IRQ_NONE;
 648
 649         stat = i2c_dw_read_clear_intrbits(dev);
 650
 651         if (stat & DW_IC_INTR_TX_ABRT) {
 652                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 653                 dev->status = STATUS_IDLE;
 654
 655                 /*
 656                  * Anytime TX_ABRT is set, the contents of the tx/rx
 657                  * buffers are flushed.  Make sure to skip them.
 658                  */
 659                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 660                 goto tx_aborted;
 661         }
 662
 663         if (stat & DW_IC_INTR_RX_FULL)
 664                 i2c_dw_read(dev);
 665
 666         if (stat & DW_IC_INTR_TX_EMPTY)
 667                 i2c_dw_xfer_msg(dev);
 668
 669         /*
 670          * No need to modify or disable the interrupt mask here.
 671          * i2c_dw_xfer_msg() will take care of it according to
 672          * the current transmit status.
 673          */
 674
 675 tx_aborted:
 676         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 677                 complete(&dev->cmd_complete);
 678
 679         return IRQ_HANDLED;
 680 }
 681
 682 void i2c_dw_enable(struct dw_i2c_dev *dev)
 683 {
 684        /* Enable the adapter */
 685         dw_writel(dev, 1, DW_IC_ENABLE);
 686 }
 687
 688 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
 689 {
 690         return dw_readl(dev, DW_IC_ENABLE);
 691 }
 692
 693 void i2c_dw_disable(struct dw_i2c_dev *dev)
 694 {
 695         /* Disable controller */
 696         dw_writel(dev, 0, DW_IC_ENABLE);
 697
 698         /* Disable all interupts */
 699         dw_writel(dev, 0, DW_IC_INTR_MASK);
 700         dw_readl(dev, DW_IC_CLR_INTR);
 701 }
 702
 703 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
 704 {
 705         dw_readl(dev, DW_IC_CLR_INTR);
 706 }
 707
 708 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
 709 {
 710         dw_writel(dev, 0, DW_IC_INTR_MASK);
 711 }
 712
 713 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
 714 {
 715         return dw_readl(dev, DW_IC_COMP_PARAM_1);
 716 }