drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "vmwgfx_drv.h"
  29 #include "drmP.h"
  30 #include "ttm/ttm_placement.h"
  31
  32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
  33 {
  34         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  35         uint32_t fifo_min, hwversion;
  36
  37         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  38                 return false;
  39
  40         fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  41         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  42                 return false;
  43
  44         hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
  45         if (hwversion == 0)
  46                 return false;
  47
  48         if (hwversion < SVGA3D_HWVERSION_WS8_B1)
  49                 return false;
  50
  51         return true;
  52 }
  53
  54 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  55 {
  56         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  57         uint32_t caps;
  58
  59         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  60                 return false;
  61
  62         caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  63         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  64                 return true;
  65
  66         return false;
  67 }
  68
  69 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  70 {
  71         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  72         uint32_t max;
  73         uint32_t min;
  74         uint32_t dummy;
  75
  76         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
  77         fifo->static_buffer = vmalloc(fifo->static_buffer_size);
  78         if (unlikely(fifo->static_buffer == NULL))
  79                 return -ENOMEM;
  80
  81         fifo->dynamic_buffer = NULL;
  82         fifo->reserved_size = 0;
  83         fifo->using_bounce_buffer = false;
  84
  85         mutex_init(&fifo->fifo_mutex);
  86         init_rwsem(&fifo->rwsem);
  87
  88         /*
  89          * Allow mapping the first page read-only to user-space.
  90          */
  91
  92         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
  93         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
  94         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
  95
  96         mutex_lock(&dev_priv->hw_mutex);
  97         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
  98         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
  99         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 100         vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
 101
 102         min = 4;
 103         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
 104                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
 105         min <<= 2;
 106
 107         if (min < PAGE_SIZE)
 108                 min = PAGE_SIZE;
 109
 110         iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
 111         iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
 112         wmb();
 113         iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
 114         iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
 115         iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
 116         mb();
 117
 118         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
 119         mutex_unlock(&dev_priv->hw_mutex);
 120
 121         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 122         min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
 123         fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
 124
 125         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
 126                  (unsigned int) max,
 127                  (unsigned int) min,
 128                  (unsigned int) fifo->capabilities);
 129
 130         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
 131         iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
 132         vmw_marker_queue_init(&fifo->marker_queue);
 133         return vmw_fifo_send_fence(dev_priv, &dummy);
 134 }
 135
 136 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 137 {
 138         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 139
 140         mutex_lock(&dev_priv->hw_mutex);
 141
 142         if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
 143                 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
 144                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 145         }
 146
 147         mutex_unlock(&dev_priv->hw_mutex);
 148 }
 149
 150 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 151 {
 152         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 153
 154         mutex_lock(&dev_priv->hw_mutex);
 155
 156         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 157                 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 158
 159         dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
 160
 161         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
 162                   dev_priv->config_done_state);
 163         vmw_write(dev_priv, SVGA_REG_ENABLE,
 164                   dev_priv->enable_state);
 165         vmw_write(dev_priv, SVGA_REG_TRACES,
 166                   dev_priv->traces_state);
 167
 168         mutex_unlock(&dev_priv->hw_mutex);
 169         vmw_marker_queue_takedown(&fifo->marker_queue);
 170
 171         if (likely(fifo->static_buffer != NULL)) {
 172                 vfree(fifo->static_buffer);
 173                 fifo->static_buffer = NULL;
 174         }
 175
 176         if (likely(fifo->dynamic_buffer != NULL)) {
 177                 vfree(fifo->dynamic_buffer);
 178                 fifo->dynamic_buffer = NULL;
 179         }
 180 }
 181
 182 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
 183 {
 184         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 185         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 186         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 187         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 188         uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 189
 190         return ((max - next_cmd) + (stop - min) <= bytes);
 191 }
 192
 193 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
 194                                uint32_t bytes, bool interruptible,
 195                                unsigned long timeout)
 196 {
 197         int ret = 0;
 198         unsigned long end_jiffies = jiffies + timeout;
 199         DEFINE_WAIT(__wait);
 200
 201         DRM_INFO("Fifo wait noirq.\n");
 202
 203         for (;;) {
 204                 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
 205                                 (interruptible) ?
 206                                 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
 207                 if (!vmw_fifo_is_full(dev_priv, bytes))
 208                         break;
 209                 if (time_after_eq(jiffies, end_jiffies)) {
 210                         ret = -EBUSY;
 211                         DRM_ERROR("SVGA device lockup.\n");
 212                         break;
 213                 }
 214                 schedule_timeout(1);
 215                 if (interruptible && signal_pending(current)) {
 216                         ret = -ERESTARTSYS;
 217                         break;
 218                 }
 219         }
 220         finish_wait(&dev_priv->fifo_queue, &__wait);
 221         wake_up_all(&dev_priv->fifo_queue);
 222         DRM_INFO("Fifo noirq exit.\n");
 223         return ret;
 224 }
 225
 226 static int vmw_fifo_wait(struct vmw_private *dev_priv,
 227                          uint32_t bytes, bool interruptible,
 228                          unsigned long timeout)
 229 {
 230         long ret = 1L;
 231         unsigned long irq_flags;
 232
 233         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
 234                 return 0;
 235
 236         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
 237         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
 238                 return vmw_fifo_wait_noirq(dev_priv, bytes,
 239                                            interruptible, timeout);
 240
 241         mutex_lock(&dev_priv->hw_mutex);
 242         if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
 243                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 244                 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
 245                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
 246                 vmw_write(dev_priv, SVGA_REG_IRQMASK,
 247                           vmw_read(dev_priv, SVGA_REG_IRQMASK) |
 248                           SVGA_IRQFLAG_FIFO_PROGRESS);
 249                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 250         }
 251         mutex_unlock(&dev_priv->hw_mutex);
 252
 253         if (interruptible)
 254                 ret = wait_event_interruptible_timeout
 255                     (dev_priv->fifo_queue,
 256                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 257         else
 258                 ret = wait_event_timeout
 259                     (dev_priv->fifo_queue,
 260                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 261
 262         if (unlikely(ret == 0))
 263                 ret = -EBUSY;
 264         else if (likely(ret > 0))
 265                 ret = 0;
 266
 267         mutex_lock(&dev_priv->hw_mutex);
 268         if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
 269                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 270                 vmw_write(dev_priv, SVGA_REG_IRQMASK,
 271                           vmw_read(dev_priv, SVGA_REG_IRQMASK) &
 272                           ~SVGA_IRQFLAG_FIFO_PROGRESS);
 273                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 274         }
 275         mutex_unlock(&dev_priv->hw_mutex);
 276
 277         return ret;
 278 }
 279
 280 /**
 281  * Reserve @bytes number of bytes in the fifo.
 282  *
 283  * This function will return NULL (error) on two conditions:
 284  *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 285  *   available fifo space.
 286  *
 287  * Returns:
 288  *   Pointer to the fifo, or null on error (possible hardware hang).
 289  */
 290 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
 291 {
 292         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 293         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 294         uint32_t max;
 295         uint32_t min;
 296         uint32_t next_cmd;
 297         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 298         int ret;
 299
 300         mutex_lock(&fifo_state->fifo_mutex);
 301         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 302         min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 303         next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 304
 305         if (unlikely(bytes >= (max - min)))
 306                 goto out_err;
 307
 308         BUG_ON(fifo_state->reserved_size != 0);
 309         BUG_ON(fifo_state->dynamic_buffer != NULL);
 310
 311         fifo_state->reserved_size = bytes;
 312
 313         while (1) {
 314                 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 315                 bool need_bounce = false;
 316                 bool reserve_in_place = false;
 317
 318                 if (next_cmd >= stop) {
 319                         if (likely((next_cmd + bytes < max ||
 320                                     (next_cmd + bytes == max && stop > min))))
 321                                 reserve_in_place = true;
 322
 323                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
 324                                 ret = vmw_fifo_wait(dev_priv, bytes,
 325                                                     false, 3 * HZ);
 326                                 if (unlikely(ret != 0))
 327                                         goto out_err;
 328                         } else
 329                                 need_bounce = true;
 330
 331                 } else {
 332
 333                         if (likely((next_cmd + bytes < stop)))
 334                                 reserve_in_place = true;
 335                         else {
 336                                 ret = vmw_fifo_wait(dev_priv, bytes,
 337                                                     false, 3 * HZ);
 338                                 if (unlikely(ret != 0))
 339                                         goto out_err;
 340                         }
 341                 }
 342
 343                 if (reserve_in_place) {
 344                         if (reserveable || bytes <= sizeof(uint32_t)) {
 345                                 fifo_state->using_bounce_buffer = false;
 346
 347                                 if (reserveable)
 348                                         iowrite32(bytes, fifo_mem +
 349                                                   SVGA_FIFO_RESERVED);
 350                                 return fifo_mem + (next_cmd >> 2);
 351                         } else {
 352                                 need_bounce = true;
 353                         }
 354                 }
 355
 356                 if (need_bounce) {
 357                         fifo_state->using_bounce_buffer = true;
 358                         if (bytes < fifo_state->static_buffer_size)
 359                                 return fifo_state->static_buffer;
 360                         else {
 361                                 fifo_state->dynamic_buffer = vmalloc(bytes);
 362                                 return fifo_state->dynamic_buffer;
 363                         }
 364                 }
 365         }
 366 out_err:
 367         fifo_state->reserved_size = 0;
 368         mutex_unlock(&fifo_state->fifo_mutex);
 369         return NULL;
 370 }
 371
 372 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
 373                               __le32 __iomem *fifo_mem,
 374                               uint32_t next_cmd,
 375                               uint32_t max, uint32_t min, uint32_t bytes)
 376 {
 377         uint32_t chunk_size = max - next_cmd;
 378         uint32_t rest;
 379         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 380             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 381
 382         if (bytes < chunk_size)
 383                 chunk_size = bytes;
 384
 385         iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
 386         mb();
 387         memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
 388         rest = bytes - chunk_size;
 389         if (rest)
 390                 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
 391                             rest);
 392 }
 393
 394 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
 395                                __le32 __iomem *fifo_mem,
 396                                uint32_t next_cmd,
 397                                uint32_t max, uint32_t min, uint32_t bytes)
 398 {
 399         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 400             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 401
 402         while (bytes > 0) {
 403                 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
 404                 next_cmd += sizeof(uint32_t);
 405                 if (unlikely(next_cmd == max))
 406                         next_cmd = min;
 407                 mb();
 408                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 409                 mb();
 410                 bytes -= sizeof(uint32_t);
 411         }
 412 }
 413
 414 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 415 {
 416         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 417         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 418         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 419         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 420         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 421         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 422
 423         BUG_ON((bytes & 3) != 0);
 424         BUG_ON(bytes > fifo_state->reserved_size);
 425
 426         fifo_state->reserved_size = 0;
 427
 428         if (fifo_state->using_bounce_buffer) {
 429                 if (reserveable)
 430                         vmw_fifo_res_copy(fifo_state, fifo_mem,
 431                                           next_cmd, max, min, bytes);
 432                 else
 433                         vmw_fifo_slow_copy(fifo_state, fifo_mem,
 434                                            next_cmd, max, min, bytes);
 435
 436                 if (fifo_state->dynamic_buffer) {
 437                         vfree(fifo_state->dynamic_buffer);
 438                         fifo_state->dynamic_buffer = NULL;
 439                 }
 440
 441         }
 442
 443         down_write(&fifo_state->rwsem);
 444         if (fifo_state->using_bounce_buffer || reserveable) {
 445                 next_cmd += bytes;
 446                 if (next_cmd >= max)
 447                         next_cmd -= max - min;
 448                 mb();
 449                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 450         }
 451
 452         if (reserveable)
 453                 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
 454         mb();
 455         up_write(&fifo_state->rwsem);
 456         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
 457         mutex_unlock(&fifo_state->fifo_mutex);
 458 }
 459
 460 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
 461 {
 462         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 463         struct svga_fifo_cmd_fence *cmd_fence;
 464         void *fm;
 465         int ret = 0;
 466         uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
 467
 468         fm = vmw_fifo_reserve(dev_priv, bytes);
 469         if (unlikely(fm == NULL)) {
 470                 *seqno = atomic_read(&dev_priv->marker_seq);
 471                 ret = -ENOMEM;
 472                 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
 473                                         false, 3*HZ);
 474                 goto out_err;
 475         }
 476
 477         do {
 478                 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
 479         } while (*seqno == 0);
 480
 481         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
 482
 483                 /*
 484                  * Don't request hardware to send a fence. The
 485                  * waiting code in vmwgfx_irq.c will emulate this.
 486                  */
 487
 488                 vmw_fifo_commit(dev_priv, 0);
 489                 return 0;
 490         }
 491
 492         *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
 493         cmd_fence = (struct svga_fifo_cmd_fence *)
 494             ((unsigned long)fm + sizeof(__le32));
 495
 496         iowrite32(*seqno, &cmd_fence->fence);
 497         vmw_fifo_commit(dev_priv, bytes);
 498         (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
 499         vmw_update_seqno(dev_priv, fifo_state);
 500
 501 out_err:
 502         return ret;
 503 }