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ARM: 7630/1: mmc: mmci: Fixup and cleanup code for DMA handling
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / rv515.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "rv515_reg_safe.h"
36
37 /* This files gather functions specifics to: rv515 */
38 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 static void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42
43 static const u32 crtc_offsets[2] =
44 {
45 0,
46 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
47 };
48
49 void rv515_debugfs(struct radeon_device *rdev)
50 {
51 if (r100_debugfs_rbbm_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
53 }
54 if (rv515_debugfs_pipes_info_init(rdev)) {
55 DRM_ERROR("Failed to register debugfs file for pipes !\n");
56 }
57 if (rv515_debugfs_ga_info_init(rdev)) {
58 DRM_ERROR("Failed to register debugfs file for pipes !\n");
59 }
60 }
61
62 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
63 {
64 int r;
65
66 r = radeon_ring_lock(rdev, ring, 64);
67 if (r) {
68 return;
69 }
70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
71 radeon_ring_write(ring,
72 ISYNC_ANY2D_IDLE3D |
73 ISYNC_ANY3D_IDLE2D |
74 ISYNC_WAIT_IDLEGUI |
75 ISYNC_CPSCRATCH_IDLEGUI);
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
77 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
79 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
81 radeon_ring_write(ring, 0);
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
83 radeon_ring_write(ring, 0);
84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
85 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
87 radeon_ring_write(ring, 0);
88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
89 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
91 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
93 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
94 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
95 radeon_ring_write(ring, 0);
96 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
97 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
98 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
99 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
100 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
101 radeon_ring_write(ring,
102 ((6 << MS_X0_SHIFT) |
103 (6 << MS_Y0_SHIFT) |
104 (6 << MS_X1_SHIFT) |
105 (6 << MS_Y1_SHIFT) |
106 (6 << MS_X2_SHIFT) |
107 (6 << MS_Y2_SHIFT) |
108 (6 << MSBD0_Y_SHIFT) |
109 (6 << MSBD0_X_SHIFT)));
110 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
111 radeon_ring_write(ring,
112 ((6 << MS_X3_SHIFT) |
113 (6 << MS_Y3_SHIFT) |
114 (6 << MS_X4_SHIFT) |
115 (6 << MS_Y4_SHIFT) |
116 (6 << MS_X5_SHIFT) |
117 (6 << MS_Y5_SHIFT) |
118 (6 << MSBD1_SHIFT)));
119 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
120 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
121 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
122 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
123 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
124 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
125 radeon_ring_write(ring, PACKET0(0x20C8, 0));
126 radeon_ring_write(ring, 0);
127 radeon_ring_unlock_commit(rdev, ring);
128 }
129
130 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
131 {
132 unsigned i;
133 uint32_t tmp;
134
135 for (i = 0; i < rdev->usec_timeout; i++) {
136 /* read MC_STATUS */
137 tmp = RREG32_MC(MC_STATUS);
138 if (tmp & MC_STATUS_IDLE) {
139 return 0;
140 }
141 DRM_UDELAY(1);
142 }
143 return -1;
144 }
145
146 void rv515_vga_render_disable(struct radeon_device *rdev)
147 {
148 WREG32(R_000300_VGA_RENDER_CONTROL,
149 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
150 }
151
152 static void rv515_gpu_init(struct radeon_device *rdev)
153 {
154 unsigned pipe_select_current, gb_pipe_select, tmp;
155
156 if (r100_gui_wait_for_idle(rdev)) {
157 printk(KERN_WARNING "Failed to wait GUI idle while "
158 "resetting GPU. Bad things might happen.\n");
159 }
160 rv515_vga_render_disable(rdev);
161 r420_pipes_init(rdev);
162 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
163 tmp = RREG32(R300_DST_PIPE_CONFIG);
164 pipe_select_current = (tmp >> 2) & 3;
165 tmp = (1 << pipe_select_current) |
166 (((gb_pipe_select >> 8) & 0xF) << 4);
167 WREG32_PLL(0x000D, tmp);
168 if (r100_gui_wait_for_idle(rdev)) {
169 printk(KERN_WARNING "Failed to wait GUI idle while "
170 "resetting GPU. Bad things might happen.\n");
171 }
172 if (rv515_mc_wait_for_idle(rdev)) {
173 printk(KERN_WARNING "Failed to wait MC idle while "
174 "programming pipes. Bad things might happen.\n");
175 }
176 }
177
178 static void rv515_vram_get_type(struct radeon_device *rdev)
179 {
180 uint32_t tmp;
181
182 rdev->mc.vram_width = 128;
183 rdev->mc.vram_is_ddr = true;
184 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
185 switch (tmp) {
186 case 0:
187 rdev->mc.vram_width = 64;
188 break;
189 case 1:
190 rdev->mc.vram_width = 128;
191 break;
192 default:
193 rdev->mc.vram_width = 128;
194 break;
195 }
196 }
197
198 static void rv515_mc_init(struct radeon_device *rdev)
199 {
200
201 rv515_vram_get_type(rdev);
202 r100_vram_init_sizes(rdev);
203 radeon_vram_location(rdev, &rdev->mc, 0);
204 rdev->mc.gtt_base_align = 0;
205 if (!(rdev->flags & RADEON_IS_AGP))
206 radeon_gtt_location(rdev, &rdev->mc);
207 radeon_update_bandwidth_info(rdev);
208 }
209
210 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
211 {
212 uint32_t r;
213
214 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
215 r = RREG32(MC_IND_DATA);
216 WREG32(MC_IND_INDEX, 0);
217 return r;
218 }
219
220 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
221 {
222 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
223 WREG32(MC_IND_DATA, (v));
224 WREG32(MC_IND_INDEX, 0);
225 }
226
227 #if defined(CONFIG_DEBUG_FS)
228 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
229 {
230 struct drm_info_node *node = (struct drm_info_node *) m->private;
231 struct drm_device *dev = node->minor->dev;
232 struct radeon_device *rdev = dev->dev_private;
233 uint32_t tmp;
234
235 tmp = RREG32(GB_PIPE_SELECT);
236 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
237 tmp = RREG32(SU_REG_DEST);
238 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
239 tmp = RREG32(GB_TILE_CONFIG);
240 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
241 tmp = RREG32(DST_PIPE_CONFIG);
242 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
243 return 0;
244 }
245
246 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
247 {
248 struct drm_info_node *node = (struct drm_info_node *) m->private;
249 struct drm_device *dev = node->minor->dev;
250 struct radeon_device *rdev = dev->dev_private;
251 uint32_t tmp;
252
253 tmp = RREG32(0x2140);
254 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
255 radeon_asic_reset(rdev);
256 tmp = RREG32(0x425C);
257 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
258 return 0;
259 }
260
261 static struct drm_info_list rv515_pipes_info_list[] = {
262 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
263 };
264
265 static struct drm_info_list rv515_ga_info_list[] = {
266 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
267 };
268 #endif
269
270 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
271 {
272 #if defined(CONFIG_DEBUG_FS)
273 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
274 #else
275 return 0;
276 #endif
277 }
278
279 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
280 {
281 #if defined(CONFIG_DEBUG_FS)
282 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
283 #else
284 return 0;
285 #endif
286 }
287
288 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
289 {
290 u32 crtc_enabled, tmp, frame_count, blackout;
291 int i, j;
292
293 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
294 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
295
296 /* disable VGA render */
297 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
298 /* blank the display controllers */
299 for (i = 0; i < rdev->num_crtc; i++) {
300 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
301 if (crtc_enabled) {
302 save->crtc_enabled[i] = true;
303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
305 radeon_wait_for_vblank(rdev, i);
306 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
307 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
308 }
309 /* wait for the next frame */
310 frame_count = radeon_get_vblank_counter(rdev, i);
311 for (j = 0; j < rdev->usec_timeout; j++) {
312 if (radeon_get_vblank_counter(rdev, i) != frame_count)
313 break;
314 udelay(1);
315 }
316 } else {
317 save->crtc_enabled[i] = false;
318 }
319 }
320
321 radeon_mc_wait_for_idle(rdev);
322
323 if (rdev->family >= CHIP_R600) {
324 if (rdev->family >= CHIP_RV770)
325 blackout = RREG32(R700_MC_CITF_CNTL);
326 else
327 blackout = RREG32(R600_CITF_CNTL);
328 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
329 /* Block CPU access */
330 WREG32(R600_BIF_FB_EN, 0);
331 /* blackout the MC */
332 blackout |= R600_BLACKOUT_MASK;
333 if (rdev->family >= CHIP_RV770)
334 WREG32(R700_MC_CITF_CNTL, blackout);
335 else
336 WREG32(R600_CITF_CNTL, blackout);
337 }
338 }
339 }
340
341 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
342 {
343 u32 tmp, frame_count;
344 int i, j;
345
346 /* update crtc base addresses */
347 for (i = 0; i < rdev->num_crtc; i++) {
348 if (rdev->family >= CHIP_RV770) {
349 if (i == 1) {
350 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
351 upper_32_bits(rdev->mc.vram_start));
352 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
353 upper_32_bits(rdev->mc.vram_start));
354 } else {
355 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
356 upper_32_bits(rdev->mc.vram_start));
357 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
358 upper_32_bits(rdev->mc.vram_start));
359 }
360 }
361 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
362 (u32)rdev->mc.vram_start);
363 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
364 (u32)rdev->mc.vram_start);
365 }
366 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
367
368 if (rdev->family >= CHIP_R600) {
369 /* unblackout the MC */
370 if (rdev->family >= CHIP_RV770)
371 tmp = RREG32(R700_MC_CITF_CNTL);
372 else
373 tmp = RREG32(R600_CITF_CNTL);
374 tmp &= ~R600_BLACKOUT_MASK;
375 if (rdev->family >= CHIP_RV770)
376 WREG32(R700_MC_CITF_CNTL, tmp);
377 else
378 WREG32(R600_CITF_CNTL, tmp);
379 /* allow CPU access */
380 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
381 }
382
383 for (i = 0; i < rdev->num_crtc; i++) {
384 if (save->crtc_enabled[i]) {
385 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
386 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
387 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
388 /* wait for the next frame */
389 frame_count = radeon_get_vblank_counter(rdev, i);
390 for (j = 0; j < rdev->usec_timeout; j++) {
391 if (radeon_get_vblank_counter(rdev, i) != frame_count)
392 break;
393 udelay(1);
394 }
395 }
396 }
397 /* Unlock vga access */
398 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
399 mdelay(1);
400 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
401 }
402
403 static void rv515_mc_program(struct radeon_device *rdev)
404 {
405 struct rv515_mc_save save;
406
407 /* Stops all mc clients */
408 rv515_mc_stop(rdev, &save);
409
410 /* Wait for mc idle */
411 if (rv515_mc_wait_for_idle(rdev))
412 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
413 /* Write VRAM size in case we are limiting it */
414 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
415 /* Program MC, should be a 32bits limited address space */
416 WREG32_MC(R_000001_MC_FB_LOCATION,
417 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
418 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
419 WREG32(R_000134_HDP_FB_LOCATION,
420 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
421 if (rdev->flags & RADEON_IS_AGP) {
422 WREG32_MC(R_000002_MC_AGP_LOCATION,
423 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
424 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
425 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
426 WREG32_MC(R_000004_MC_AGP_BASE_2,
427 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
428 } else {
429 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
430 WREG32_MC(R_000003_MC_AGP_BASE, 0);
431 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
432 }
433
434 rv515_mc_resume(rdev, &save);
435 }
436
437 void rv515_clock_startup(struct radeon_device *rdev)
438 {
439 if (radeon_dynclks != -1 && radeon_dynclks)
440 radeon_atom_set_clock_gating(rdev, 1);
441 /* We need to force on some of the block */
442 WREG32_PLL(R_00000F_CP_DYN_CNTL,
443 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
444 WREG32_PLL(R_000011_E2_DYN_CNTL,
445 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
446 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
447 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
448 }
449
450 static int rv515_startup(struct radeon_device *rdev)
451 {
452 int r;
453
454 rv515_mc_program(rdev);
455 /* Resume clock */
456 rv515_clock_startup(rdev);
457 /* Initialize GPU configuration (# pipes, ...) */
458 rv515_gpu_init(rdev);
459 /* Initialize GART (initialize after TTM so we can allocate
460 * memory through TTM but finalize after TTM) */
461 if (rdev->flags & RADEON_IS_PCIE) {
462 r = rv370_pcie_gart_enable(rdev);
463 if (r)
464 return r;
465 }
466
467 /* allocate wb buffer */
468 r = radeon_wb_init(rdev);
469 if (r)
470 return r;
471
472 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
473 if (r) {
474 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
475 return r;
476 }
477
478 /* Enable IRQ */
479 rs600_irq_set(rdev);
480 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
481 /* 1M ring buffer */
482 r = r100_cp_init(rdev, 1024 * 1024);
483 if (r) {
484 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
485 return r;
486 }
487
488 r = radeon_ib_pool_init(rdev);
489 if (r) {
490 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
491 return r;
492 }
493
494 return 0;
495 }
496
497 int rv515_resume(struct radeon_device *rdev)
498 {
499 int r;
500
501 /* Make sur GART are not working */
502 if (rdev->flags & RADEON_IS_PCIE)
503 rv370_pcie_gart_disable(rdev);
504 /* Resume clock before doing reset */
505 rv515_clock_startup(rdev);
506 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
507 if (radeon_asic_reset(rdev)) {
508 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
509 RREG32(R_000E40_RBBM_STATUS),
510 RREG32(R_0007C0_CP_STAT));
511 }
512 /* post */
513 atom_asic_init(rdev->mode_info.atom_context);
514 /* Resume clock after posting */
515 rv515_clock_startup(rdev);
516 /* Initialize surface registers */
517 radeon_surface_init(rdev);
518
519 rdev->accel_working = true;
520 r = rv515_startup(rdev);
521 if (r) {
522 rdev->accel_working = false;
523 }
524 return r;
525 }
526
527 int rv515_suspend(struct radeon_device *rdev)
528 {
529 r100_cp_disable(rdev);
530 radeon_wb_disable(rdev);
531 rs600_irq_disable(rdev);
532 if (rdev->flags & RADEON_IS_PCIE)
533 rv370_pcie_gart_disable(rdev);
534 return 0;
535 }
536
537 void rv515_set_safe_registers(struct radeon_device *rdev)
538 {
539 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
540 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
541 }
542
543 void rv515_fini(struct radeon_device *rdev)
544 {
545 r100_cp_fini(rdev);
546 radeon_wb_fini(rdev);
547 radeon_ib_pool_fini(rdev);
548 radeon_gem_fini(rdev);
549 rv370_pcie_gart_fini(rdev);
550 radeon_agp_fini(rdev);
551 radeon_irq_kms_fini(rdev);
552 radeon_fence_driver_fini(rdev);
553 radeon_bo_fini(rdev);
554 radeon_atombios_fini(rdev);
555 kfree(rdev->bios);
556 rdev->bios = NULL;
557 }
558
559 int rv515_init(struct radeon_device *rdev)
560 {
561 int r;
562
563 /* Initialize scratch registers */
564 radeon_scratch_init(rdev);
565 /* Initialize surface registers */
566 radeon_surface_init(rdev);
567 /* TODO: disable VGA need to use VGA request */
568 /* restore some register to sane defaults */
569 r100_restore_sanity(rdev);
570 /* BIOS*/
571 if (!radeon_get_bios(rdev)) {
572 if (ASIC_IS_AVIVO(rdev))
573 return -EINVAL;
574 }
575 if (rdev->is_atom_bios) {
576 r = radeon_atombios_init(rdev);
577 if (r)
578 return r;
579 } else {
580 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
581 return -EINVAL;
582 }
583 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
584 if (radeon_asic_reset(rdev)) {
585 dev_warn(rdev->dev,
586 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
587 RREG32(R_000E40_RBBM_STATUS),
588 RREG32(R_0007C0_CP_STAT));
589 }
590 /* check if cards are posted or not */
591 if (radeon_boot_test_post_card(rdev) == false)
592 return -EINVAL;
593 /* Initialize clocks */
594 radeon_get_clock_info(rdev->ddev);
595 /* initialize AGP */
596 if (rdev->flags & RADEON_IS_AGP) {
597 r = radeon_agp_init(rdev);
598 if (r) {
599 radeon_agp_disable(rdev);
600 }
601 }
602 /* initialize memory controller */
603 rv515_mc_init(rdev);
604 rv515_debugfs(rdev);
605 /* Fence driver */
606 r = radeon_fence_driver_init(rdev);
607 if (r)
608 return r;
609 r = radeon_irq_kms_init(rdev);
610 if (r)
611 return r;
612 /* Memory manager */
613 r = radeon_bo_init(rdev);
614 if (r)
615 return r;
616 r = rv370_pcie_gart_init(rdev);
617 if (r)
618 return r;
619 rv515_set_safe_registers(rdev);
620
621 rdev->accel_working = true;
622 r = rv515_startup(rdev);
623 if (r) {
624 /* Somethings want wront with the accel init stop accel */
625 dev_err(rdev->dev, "Disabling GPU acceleration\n");
626 r100_cp_fini(rdev);
627 radeon_wb_fini(rdev);
628 radeon_ib_pool_fini(rdev);
629 radeon_irq_kms_fini(rdev);
630 rv370_pcie_gart_fini(rdev);
631 radeon_agp_fini(rdev);
632 rdev->accel_working = false;
633 }
634 return 0;
635 }
636
637 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
638 {
639 int index_reg = 0x6578 + crtc->crtc_offset;
640 int data_reg = 0x657c + crtc->crtc_offset;
641
642 WREG32(0x659C + crtc->crtc_offset, 0x0);
643 WREG32(0x6594 + crtc->crtc_offset, 0x705);
644 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
645 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
646 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
647 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
648 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
649 WREG32(index_reg, 0x0);
650 WREG32(data_reg, 0x841880A8);
651 WREG32(index_reg, 0x1);
652 WREG32(data_reg, 0x84208680);
653 WREG32(index_reg, 0x2);
654 WREG32(data_reg, 0xBFF880B0);
655 WREG32(index_reg, 0x100);
656 WREG32(data_reg, 0x83D88088);
657 WREG32(index_reg, 0x101);
658 WREG32(data_reg, 0x84608680);
659 WREG32(index_reg, 0x102);
660 WREG32(data_reg, 0xBFF080D0);
661 WREG32(index_reg, 0x200);
662 WREG32(data_reg, 0x83988068);
663 WREG32(index_reg, 0x201);
664 WREG32(data_reg, 0x84A08680);
665 WREG32(index_reg, 0x202);
666 WREG32(data_reg, 0xBFF080F8);
667 WREG32(index_reg, 0x300);
668 WREG32(data_reg, 0x83588058);
669 WREG32(index_reg, 0x301);
670 WREG32(data_reg, 0x84E08660);
671 WREG32(index_reg, 0x302);
672 WREG32(data_reg, 0xBFF88120);
673 WREG32(index_reg, 0x400);
674 WREG32(data_reg, 0x83188040);
675 WREG32(index_reg, 0x401);
676 WREG32(data_reg, 0x85008660);
677 WREG32(index_reg, 0x402);
678 WREG32(data_reg, 0xBFF88150);
679 WREG32(index_reg, 0x500);
680 WREG32(data_reg, 0x82D88030);
681 WREG32(index_reg, 0x501);
682 WREG32(data_reg, 0x85408640);
683 WREG32(index_reg, 0x502);
684 WREG32(data_reg, 0xBFF88180);
685 WREG32(index_reg, 0x600);
686 WREG32(data_reg, 0x82A08018);
687 WREG32(index_reg, 0x601);
688 WREG32(data_reg, 0x85808620);
689 WREG32(index_reg, 0x602);
690 WREG32(data_reg, 0xBFF081B8);
691 WREG32(index_reg, 0x700);
692 WREG32(data_reg, 0x82608010);
693 WREG32(index_reg, 0x701);
694 WREG32(data_reg, 0x85A08600);
695 WREG32(index_reg, 0x702);
696 WREG32(data_reg, 0x800081F0);
697 WREG32(index_reg, 0x800);
698 WREG32(data_reg, 0x8228BFF8);
699 WREG32(index_reg, 0x801);
700 WREG32(data_reg, 0x85E085E0);
701 WREG32(index_reg, 0x802);
702 WREG32(data_reg, 0xBFF88228);
703 WREG32(index_reg, 0x10000);
704 WREG32(data_reg, 0x82A8BF00);
705 WREG32(index_reg, 0x10001);
706 WREG32(data_reg, 0x82A08CC0);
707 WREG32(index_reg, 0x10002);
708 WREG32(data_reg, 0x8008BEF8);
709 WREG32(index_reg, 0x10100);
710 WREG32(data_reg, 0x81F0BF28);
711 WREG32(index_reg, 0x10101);
712 WREG32(data_reg, 0x83608CA0);
713 WREG32(index_reg, 0x10102);
714 WREG32(data_reg, 0x8018BED0);
715 WREG32(index_reg, 0x10200);
716 WREG32(data_reg, 0x8148BF38);
717 WREG32(index_reg, 0x10201);
718 WREG32(data_reg, 0x84408C80);
719 WREG32(index_reg, 0x10202);
720 WREG32(data_reg, 0x8008BEB8);
721 WREG32(index_reg, 0x10300);
722 WREG32(data_reg, 0x80B0BF78);
723 WREG32(index_reg, 0x10301);
724 WREG32(data_reg, 0x85008C20);
725 WREG32(index_reg, 0x10302);
726 WREG32(data_reg, 0x8020BEA0);
727 WREG32(index_reg, 0x10400);
728 WREG32(data_reg, 0x8028BF90);
729 WREG32(index_reg, 0x10401);
730 WREG32(data_reg, 0x85E08BC0);
731 WREG32(index_reg, 0x10402);
732 WREG32(data_reg, 0x8018BE90);
733 WREG32(index_reg, 0x10500);
734 WREG32(data_reg, 0xBFB8BFB0);
735 WREG32(index_reg, 0x10501);
736 WREG32(data_reg, 0x86C08B40);
737 WREG32(index_reg, 0x10502);
738 WREG32(data_reg, 0x8010BE90);
739 WREG32(index_reg, 0x10600);
740 WREG32(data_reg, 0xBF58BFC8);
741 WREG32(index_reg, 0x10601);
742 WREG32(data_reg, 0x87A08AA0);
743 WREG32(index_reg, 0x10602);
744 WREG32(data_reg, 0x8010BE98);
745 WREG32(index_reg, 0x10700);
746 WREG32(data_reg, 0xBF10BFF0);
747 WREG32(index_reg, 0x10701);
748 WREG32(data_reg, 0x886089E0);
749 WREG32(index_reg, 0x10702);
750 WREG32(data_reg, 0x8018BEB0);
751 WREG32(index_reg, 0x10800);
752 WREG32(data_reg, 0xBED8BFE8);
753 WREG32(index_reg, 0x10801);
754 WREG32(data_reg, 0x89408940);
755 WREG32(index_reg, 0x10802);
756 WREG32(data_reg, 0xBFE8BED8);
757 WREG32(index_reg, 0x20000);
758 WREG32(data_reg, 0x80008000);
759 WREG32(index_reg, 0x20001);
760 WREG32(data_reg, 0x90008000);
761 WREG32(index_reg, 0x20002);
762 WREG32(data_reg, 0x80008000);
763 WREG32(index_reg, 0x20003);
764 WREG32(data_reg, 0x80008000);
765 WREG32(index_reg, 0x20100);
766 WREG32(data_reg, 0x80108000);
767 WREG32(index_reg, 0x20101);
768 WREG32(data_reg, 0x8FE0BF70);
769 WREG32(index_reg, 0x20102);
770 WREG32(data_reg, 0xBFE880C0);
771 WREG32(index_reg, 0x20103);
772 WREG32(data_reg, 0x80008000);
773 WREG32(index_reg, 0x20200);
774 WREG32(data_reg, 0x8018BFF8);
775 WREG32(index_reg, 0x20201);
776 WREG32(data_reg, 0x8F80BF08);
777 WREG32(index_reg, 0x20202);
778 WREG32(data_reg, 0xBFD081A0);
779 WREG32(index_reg, 0x20203);
780 WREG32(data_reg, 0xBFF88000);
781 WREG32(index_reg, 0x20300);
782 WREG32(data_reg, 0x80188000);
783 WREG32(index_reg, 0x20301);
784 WREG32(data_reg, 0x8EE0BEC0);
785 WREG32(index_reg, 0x20302);
786 WREG32(data_reg, 0xBFB082A0);
787 WREG32(index_reg, 0x20303);
788 WREG32(data_reg, 0x80008000);
789 WREG32(index_reg, 0x20400);
790 WREG32(data_reg, 0x80188000);
791 WREG32(index_reg, 0x20401);
792 WREG32(data_reg, 0x8E00BEA0);
793 WREG32(index_reg, 0x20402);
794 WREG32(data_reg, 0xBF8883C0);
795 WREG32(index_reg, 0x20403);
796 WREG32(data_reg, 0x80008000);
797 WREG32(index_reg, 0x20500);
798 WREG32(data_reg, 0x80188000);
799 WREG32(index_reg, 0x20501);
800 WREG32(data_reg, 0x8D00BE90);
801 WREG32(index_reg, 0x20502);
802 WREG32(data_reg, 0xBF588500);
803 WREG32(index_reg, 0x20503);
804 WREG32(data_reg, 0x80008008);
805 WREG32(index_reg, 0x20600);
806 WREG32(data_reg, 0x80188000);
807 WREG32(index_reg, 0x20601);
808 WREG32(data_reg, 0x8BC0BE98);
809 WREG32(index_reg, 0x20602);
810 WREG32(data_reg, 0xBF308660);
811 WREG32(index_reg, 0x20603);
812 WREG32(data_reg, 0x80008008);
813 WREG32(index_reg, 0x20700);
814 WREG32(data_reg, 0x80108000);
815 WREG32(index_reg, 0x20701);
816 WREG32(data_reg, 0x8A80BEB0);
817 WREG32(index_reg, 0x20702);
818 WREG32(data_reg, 0xBF0087C0);
819 WREG32(index_reg, 0x20703);
820 WREG32(data_reg, 0x80008008);
821 WREG32(index_reg, 0x20800);
822 WREG32(data_reg, 0x80108000);
823 WREG32(index_reg, 0x20801);
824 WREG32(data_reg, 0x8920BED0);
825 WREG32(index_reg, 0x20802);
826 WREG32(data_reg, 0xBED08920);
827 WREG32(index_reg, 0x20803);
828 WREG32(data_reg, 0x80008010);
829 WREG32(index_reg, 0x30000);
830 WREG32(data_reg, 0x90008000);
831 WREG32(index_reg, 0x30001);
832 WREG32(data_reg, 0x80008000);
833 WREG32(index_reg, 0x30100);
834 WREG32(data_reg, 0x8FE0BF90);
835 WREG32(index_reg, 0x30101);
836 WREG32(data_reg, 0xBFF880A0);
837 WREG32(index_reg, 0x30200);
838 WREG32(data_reg, 0x8F60BF40);
839 WREG32(index_reg, 0x30201);
840 WREG32(data_reg, 0xBFE88180);
841 WREG32(index_reg, 0x30300);
842 WREG32(data_reg, 0x8EC0BF00);
843 WREG32(index_reg, 0x30301);
844 WREG32(data_reg, 0xBFC88280);
845 WREG32(index_reg, 0x30400);
846 WREG32(data_reg, 0x8DE0BEE0);
847 WREG32(index_reg, 0x30401);
848 WREG32(data_reg, 0xBFA083A0);
849 WREG32(index_reg, 0x30500);
850 WREG32(data_reg, 0x8CE0BED0);
851 WREG32(index_reg, 0x30501);
852 WREG32(data_reg, 0xBF7884E0);
853 WREG32(index_reg, 0x30600);
854 WREG32(data_reg, 0x8BA0BED8);
855 WREG32(index_reg, 0x30601);
856 WREG32(data_reg, 0xBF508640);
857 WREG32(index_reg, 0x30700);
858 WREG32(data_reg, 0x8A60BEE8);
859 WREG32(index_reg, 0x30701);
860 WREG32(data_reg, 0xBF2087A0);
861 WREG32(index_reg, 0x30800);
862 WREG32(data_reg, 0x8900BF00);
863 WREG32(index_reg, 0x30801);
864 WREG32(data_reg, 0xBF008900);
865 }
866
867 struct rv515_watermark {
868 u32 lb_request_fifo_depth;
869 fixed20_12 num_line_pair;
870 fixed20_12 estimated_width;
871 fixed20_12 worst_case_latency;
872 fixed20_12 consumption_rate;
873 fixed20_12 active_time;
874 fixed20_12 dbpp;
875 fixed20_12 priority_mark_max;
876 fixed20_12 priority_mark;
877 fixed20_12 sclk;
878 };
879
880 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
881 struct radeon_crtc *crtc,
882 struct rv515_watermark *wm)
883 {
884 struct drm_display_mode *mode = &crtc->base.mode;
885 fixed20_12 a, b, c;
886 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
887 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
888
889 if (!crtc->base.enabled) {
890 /* FIXME: wouldn't it better to set priority mark to maximum */
891 wm->lb_request_fifo_depth = 4;
892 return;
893 }
894
895 if (crtc->vsc.full > dfixed_const(2))
896 wm->num_line_pair.full = dfixed_const(2);
897 else
898 wm->num_line_pair.full = dfixed_const(1);
899
900 b.full = dfixed_const(mode->crtc_hdisplay);
901 c.full = dfixed_const(256);
902 a.full = dfixed_div(b, c);
903 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
904 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
905 if (a.full < dfixed_const(4)) {
906 wm->lb_request_fifo_depth = 4;
907 } else {
908 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
909 }
910
911 /* Determine consumption rate
912 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
913 * vtaps = number of vertical taps,
914 * vsc = vertical scaling ratio, defined as source/destination
915 * hsc = horizontal scaling ration, defined as source/destination
916 */
917 a.full = dfixed_const(mode->clock);
918 b.full = dfixed_const(1000);
919 a.full = dfixed_div(a, b);
920 pclk.full = dfixed_div(b, a);
921 if (crtc->rmx_type != RMX_OFF) {
922 b.full = dfixed_const(2);
923 if (crtc->vsc.full > b.full)
924 b.full = crtc->vsc.full;
925 b.full = dfixed_mul(b, crtc->hsc);
926 c.full = dfixed_const(2);
927 b.full = dfixed_div(b, c);
928 consumption_time.full = dfixed_div(pclk, b);
929 } else {
930 consumption_time.full = pclk.full;
931 }
932 a.full = dfixed_const(1);
933 wm->consumption_rate.full = dfixed_div(a, consumption_time);
934
935
936 /* Determine line time
937 * LineTime = total time for one line of displayhtotal
938 * LineTime = total number of horizontal pixels
939 * pclk = pixel clock period(ns)
940 */
941 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
942 line_time.full = dfixed_mul(a, pclk);
943
944 /* Determine active time
945 * ActiveTime = time of active region of display within one line,
946 * hactive = total number of horizontal active pixels
947 * htotal = total number of horizontal pixels
948 */
949 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
950 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
951 wm->active_time.full = dfixed_mul(line_time, b);
952 wm->active_time.full = dfixed_div(wm->active_time, a);
953
954 /* Determine chunk time
955 * ChunkTime = the time it takes the DCP to send one chunk of data
956 * to the LB which consists of pipeline delay and inter chunk gap
957 * sclk = system clock(Mhz)
958 */
959 a.full = dfixed_const(600 * 1000);
960 chunk_time.full = dfixed_div(a, rdev->pm.sclk);
961 read_delay_latency.full = dfixed_const(1000);
962
963 /* Determine the worst case latency
964 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
965 * WorstCaseLatency = worst case time from urgent to when the MC starts
966 * to return data
967 * READ_DELAY_IDLE_MAX = constant of 1us
968 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
969 * which consists of pipeline delay and inter chunk gap
970 */
971 if (dfixed_trunc(wm->num_line_pair) > 1) {
972 a.full = dfixed_const(3);
973 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
974 wm->worst_case_latency.full += read_delay_latency.full;
975 } else {
976 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
977 }
978
979 /* Determine the tolerable latency
980 * TolerableLatency = Any given request has only 1 line time
981 * for the data to be returned
982 * LBRequestFifoDepth = Number of chunk requests the LB can
983 * put into the request FIFO for a display
984 * LineTime = total time for one line of display
985 * ChunkTime = the time it takes the DCP to send one chunk
986 * of data to the LB which consists of
987 * pipeline delay and inter chunk gap
988 */
989 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
990 tolerable_latency.full = line_time.full;
991 } else {
992 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
993 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
994 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
995 tolerable_latency.full = line_time.full - tolerable_latency.full;
996 }
997 /* We assume worst case 32bits (4 bytes) */
998 wm->dbpp.full = dfixed_const(2 * 16);
999
1000 /* Determine the maximum priority mark
1001 * width = viewport width in pixels
1002 */
1003 a.full = dfixed_const(16);
1004 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1005 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1006 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1007
1008 /* Determine estimated width */
1009 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1010 estimated_width.full = dfixed_div(estimated_width, consumption_time);
1011 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1012 wm->priority_mark.full = wm->priority_mark_max.full;
1013 } else {
1014 a.full = dfixed_const(16);
1015 wm->priority_mark.full = dfixed_div(estimated_width, a);
1016 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1017 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1018 }
1019 }
1020
1021 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1022 {
1023 struct drm_display_mode *mode0 = NULL;
1024 struct drm_display_mode *mode1 = NULL;
1025 struct rv515_watermark wm0;
1026 struct rv515_watermark wm1;
1027 u32 tmp;
1028 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1029 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1030 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1031 fixed20_12 a, b;
1032
1033 if (rdev->mode_info.crtcs[0]->base.enabled)
1034 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1035 if (rdev->mode_info.crtcs[1]->base.enabled)
1036 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1037 rs690_line_buffer_adjust(rdev, mode0, mode1);
1038
1039 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1040 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1041
1042 tmp = wm0.lb_request_fifo_depth;
1043 tmp |= wm1.lb_request_fifo_depth << 16;
1044 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1045
1046 if (mode0 && mode1) {
1047 if (dfixed_trunc(wm0.dbpp) > 64)
1048 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1049 else
1050 a.full = wm0.num_line_pair.full;
1051 if (dfixed_trunc(wm1.dbpp) > 64)
1052 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1053 else
1054 b.full = wm1.num_line_pair.full;
1055 a.full += b.full;
1056 fill_rate.full = dfixed_div(wm0.sclk, a);
1057 if (wm0.consumption_rate.full > fill_rate.full) {
1058 b.full = wm0.consumption_rate.full - fill_rate.full;
1059 b.full = dfixed_mul(b, wm0.active_time);
1060 a.full = dfixed_const(16);
1061 b.full = dfixed_div(b, a);
1062 a.full = dfixed_mul(wm0.worst_case_latency,
1063 wm0.consumption_rate);
1064 priority_mark02.full = a.full + b.full;
1065 } else {
1066 a.full = dfixed_mul(wm0.worst_case_latency,
1067 wm0.consumption_rate);
1068 b.full = dfixed_const(16 * 1000);
1069 priority_mark02.full = dfixed_div(a, b);
1070 }
1071 if (wm1.consumption_rate.full > fill_rate.full) {
1072 b.full = wm1.consumption_rate.full - fill_rate.full;
1073 b.full = dfixed_mul(b, wm1.active_time);
1074 a.full = dfixed_const(16);
1075 b.full = dfixed_div(b, a);
1076 a.full = dfixed_mul(wm1.worst_case_latency,
1077 wm1.consumption_rate);
1078 priority_mark12.full = a.full + b.full;
1079 } else {
1080 a.full = dfixed_mul(wm1.worst_case_latency,
1081 wm1.consumption_rate);
1082 b.full = dfixed_const(16 * 1000);
1083 priority_mark12.full = dfixed_div(a, b);
1084 }
1085 if (wm0.priority_mark.full > priority_mark02.full)
1086 priority_mark02.full = wm0.priority_mark.full;
1087 if (dfixed_trunc(priority_mark02) < 0)
1088 priority_mark02.full = 0;
1089 if (wm0.priority_mark_max.full > priority_mark02.full)
1090 priority_mark02.full = wm0.priority_mark_max.full;
1091 if (wm1.priority_mark.full > priority_mark12.full)
1092 priority_mark12.full = wm1.priority_mark.full;
1093 if (dfixed_trunc(priority_mark12) < 0)
1094 priority_mark12.full = 0;
1095 if (wm1.priority_mark_max.full > priority_mark12.full)
1096 priority_mark12.full = wm1.priority_mark_max.full;
1097 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1098 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1099 if (rdev->disp_priority == 2) {
1100 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1101 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1102 }
1103 } else if (mode0) {
1104 if (dfixed_trunc(wm0.dbpp) > 64)
1105 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1106 else
1107 a.full = wm0.num_line_pair.full;
1108 fill_rate.full = dfixed_div(wm0.sclk, a);
1109 if (wm0.consumption_rate.full > fill_rate.full) {
1110 b.full = wm0.consumption_rate.full - fill_rate.full;
1111 b.full = dfixed_mul(b, wm0.active_time);
1112 a.full = dfixed_const(16);
1113 b.full = dfixed_div(b, a);
1114 a.full = dfixed_mul(wm0.worst_case_latency,
1115 wm0.consumption_rate);
1116 priority_mark02.full = a.full + b.full;
1117 } else {
1118 a.full = dfixed_mul(wm0.worst_case_latency,
1119 wm0.consumption_rate);
1120 b.full = dfixed_const(16);
1121 priority_mark02.full = dfixed_div(a, b);
1122 }
1123 if (wm0.priority_mark.full > priority_mark02.full)
1124 priority_mark02.full = wm0.priority_mark.full;
1125 if (dfixed_trunc(priority_mark02) < 0)
1126 priority_mark02.full = 0;
1127 if (wm0.priority_mark_max.full > priority_mark02.full)
1128 priority_mark02.full = wm0.priority_mark_max.full;
1129 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1130 if (rdev->disp_priority == 2)
1131 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1132 } else if (mode1) {
1133 if (dfixed_trunc(wm1.dbpp) > 64)
1134 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1135 else
1136 a.full = wm1.num_line_pair.full;
1137 fill_rate.full = dfixed_div(wm1.sclk, a);
1138 if (wm1.consumption_rate.full > fill_rate.full) {
1139 b.full = wm1.consumption_rate.full - fill_rate.full;
1140 b.full = dfixed_mul(b, wm1.active_time);
1141 a.full = dfixed_const(16);
1142 b.full = dfixed_div(b, a);
1143 a.full = dfixed_mul(wm1.worst_case_latency,
1144 wm1.consumption_rate);
1145 priority_mark12.full = a.full + b.full;
1146 } else {
1147 a.full = dfixed_mul(wm1.worst_case_latency,
1148 wm1.consumption_rate);
1149 b.full = dfixed_const(16 * 1000);
1150 priority_mark12.full = dfixed_div(a, b);
1151 }
1152 if (wm1.priority_mark.full > priority_mark12.full)
1153 priority_mark12.full = wm1.priority_mark.full;
1154 if (dfixed_trunc(priority_mark12) < 0)
1155 priority_mark12.full = 0;
1156 if (wm1.priority_mark_max.full > priority_mark12.full)
1157 priority_mark12.full = wm1.priority_mark_max.full;
1158 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1159 if (rdev->disp_priority == 2)
1160 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1161 }
1162
1163 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1164 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1165 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1166 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1167 }
1168
1169 void rv515_bandwidth_update(struct radeon_device *rdev)
1170 {
1171 uint32_t tmp;
1172 struct drm_display_mode *mode0 = NULL;
1173 struct drm_display_mode *mode1 = NULL;
1174
1175 radeon_update_display_priority(rdev);
1176
1177 if (rdev->mode_info.crtcs[0]->base.enabled)
1178 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1179 if (rdev->mode_info.crtcs[1]->base.enabled)
1180 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1181 /*
1182 * Set display0/1 priority up in the memory controller for
1183 * modes if the user specifies HIGH for displaypriority
1184 * option.
1185 */
1186 if ((rdev->disp_priority == 2) &&
1187 (rdev->family == CHIP_RV515)) {
1188 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1189 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1190 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1191 if (mode1)
1192 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1193 if (mode0)
1194 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1195 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1196 }
1197 rv515_bandwidth_avivo_update(rdev);
1198 }
kernel source for telekom puls (alcatel/mediatek)