drivers/gpu/drm/radeon/radeon_mode.h

   1 /*
   2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   3  *                VA Linux Systems Inc., Fremont, California.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Original Authors:
  25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26  *
  27  * Kernel port Author: Dave Airlie
  28  */
  29
  30 #ifndef RADEON_MODE_H
  31 #define RADEON_MODE_H
  32
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drm_dp_helper.h>
  36 #include <drm/drm_fixed.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <linux/i2c.h>
  39 #include <linux/i2c-algo-bit.h>
  40
  41 struct radeon_bo;
  42 struct radeon_device;
  43
  44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  48
  49 enum radeon_rmx_type {
  50         RMX_OFF,
  51         RMX_FULL,
  52         RMX_CENTER,
  53         RMX_ASPECT
  54 };
  55
  56 enum radeon_tv_std {
  57         TV_STD_NTSC,
  58         TV_STD_PAL,
  59         TV_STD_PAL_M,
  60         TV_STD_PAL_60,
  61         TV_STD_NTSC_J,
  62         TV_STD_SCART_PAL,
  63         TV_STD_SECAM,
  64         TV_STD_PAL_CN,
  65         TV_STD_PAL_N,
  66 };
  67
  68 enum radeon_underscan_type {
  69         UNDERSCAN_OFF,
  70         UNDERSCAN_ON,
  71         UNDERSCAN_AUTO,
  72 };
  73
  74 enum radeon_hpd_id {
  75         RADEON_HPD_1 = 0,
  76         RADEON_HPD_2,
  77         RADEON_HPD_3,
  78         RADEON_HPD_4,
  79         RADEON_HPD_5,
  80         RADEON_HPD_6,
  81         RADEON_HPD_NONE = 0xff,
  82 };
  83
  84 #define RADEON_MAX_I2C_BUS 16
  85
  86 /* radeon gpio-based i2c
  87  * 1. "mask" reg and bits
  88  *    grabs the gpio pins for software use
  89  *    0=not held  1=held
  90  * 2. "a" reg and bits
  91  *    output pin value
  92  *    0=low 1=high
  93  * 3. "en" reg and bits
  94  *    sets the pin direction
  95  *    0=input 1=output
  96  * 4. "y" reg and bits
  97  *    input pin value
  98  *    0=low 1=high
  99  */
 100 struct radeon_i2c_bus_rec {
 101         bool valid;
 102         /* id used by atom */
 103         uint8_t i2c_id;
 104         /* id used by atom */
 105         enum radeon_hpd_id hpd;
 106         /* can be used with hw i2c engine */
 107         bool hw_capable;
 108         /* uses multi-media i2c engine */
 109         bool mm_i2c;
 110         /* regs and bits */
 111         uint32_t mask_clk_reg;
 112         uint32_t mask_data_reg;
 113         uint32_t a_clk_reg;
 114         uint32_t a_data_reg;
 115         uint32_t en_clk_reg;
 116         uint32_t en_data_reg;
 117         uint32_t y_clk_reg;
 118         uint32_t y_data_reg;
 119         uint32_t mask_clk_mask;
 120         uint32_t mask_data_mask;
 121         uint32_t a_clk_mask;
 122         uint32_t a_data_mask;
 123         uint32_t en_clk_mask;
 124         uint32_t en_data_mask;
 125         uint32_t y_clk_mask;
 126         uint32_t y_data_mask;
 127 };
 128
 129 struct radeon_tmds_pll {
 130     uint32_t freq;
 131     uint32_t value;
 132 };
 133
 134 #define RADEON_MAX_BIOS_CONNECTOR 16
 135
 136 /* pll flags */
 137 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
 138 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
 139 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
 140 #define RADEON_PLL_LEGACY               (1 << 3)
 141 #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
 143 #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
 145 #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 147 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 149 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
 150 #define RADEON_PLL_IS_LCD               (1 << 13)
 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
 152
 153 struct radeon_pll {
 154         /* reference frequency */
 155         uint32_t reference_freq;
 156
 157         /* fixed dividers */
 158         uint32_t reference_div;
 159         uint32_t post_div;
 160
 161         /* pll in/out limits */
 162         uint32_t pll_in_min;
 163         uint32_t pll_in_max;
 164         uint32_t pll_out_min;
 165         uint32_t pll_out_max;
 166         uint32_t lcd_pll_out_min;
 167         uint32_t lcd_pll_out_max;
 168         uint32_t best_vco;
 169
 170         /* divider limits */
 171         uint32_t min_ref_div;
 172         uint32_t max_ref_div;
 173         uint32_t min_post_div;
 174         uint32_t max_post_div;
 175         uint32_t min_feedback_div;
 176         uint32_t max_feedback_div;
 177         uint32_t min_frac_feedback_div;
 178         uint32_t max_frac_feedback_div;
 179
 180         /* flags for the current clock */
 181         uint32_t flags;
 182
 183         /* pll id */
 184         uint32_t id;
 185 };
 186
 187 struct radeon_i2c_chan {
 188         struct i2c_adapter adapter;
 189         struct drm_device *dev;
 190         union {
 191                 struct i2c_algo_bit_data bit;
 192                 struct i2c_algo_dp_aux_data dp;
 193         } algo;
 194         struct radeon_i2c_bus_rec rec;
 195 };
 196
 197 /* mostly for macs, but really any system without connector tables */
 198 enum radeon_connector_table {
 199         CT_NONE = 0,
 200         CT_GENERIC,
 201         CT_IBOOK,
 202         CT_POWERBOOK_EXTERNAL,
 203         CT_POWERBOOK_INTERNAL,
 204         CT_POWERBOOK_VGA,
 205         CT_MINI_EXTERNAL,
 206         CT_MINI_INTERNAL,
 207         CT_IMAC_G5_ISIGHT,
 208         CT_EMAC,
 209         CT_RN50_POWER,
 210         CT_MAC_X800,
 211         CT_MAC_G5_9600,
 212         CT_SAM440EP,
 213         CT_MAC_G4_SILVER
 214 };
 215
 216 enum radeon_dvo_chip {
 217         DVO_SIL164,
 218         DVO_SIL1178,
 219 };
 220
 221 struct radeon_fbdev;
 222
 223 struct radeon_afmt {
 224         bool enabled;
 225         int offset;
 226         bool last_buffer_filled_status;
 227         int id;
 228 };
 229
 230 struct radeon_mode_info {
 231         struct atom_context *atom_context;
 232         struct card_info *atom_card_info;
 233         enum radeon_connector_table connector_table;
 234         bool mode_config_initialized;
 235         struct radeon_crtc *crtcs[6];
 236         struct radeon_afmt *afmt[6];
 237         /* DVI-I properties */
 238         struct drm_property *coherent_mode_property;
 239         /* DAC enable load detect */
 240         struct drm_property *load_detect_property;
 241         /* TV standard */
 242         struct drm_property *tv_std_property;
 243         /* legacy TMDS PLL detect */
 244         struct drm_property *tmds_pll_property;
 245         /* underscan */
 246         struct drm_property *underscan_property;
 247         struct drm_property *underscan_hborder_property;
 248         struct drm_property *underscan_vborder_property;
 249         /* hardcoded DFP edid from BIOS */
 250         struct edid *bios_hardcoded_edid;
 251         int bios_hardcoded_edid_size;
 252
 253         /* pointer to fbdev info structure */
 254         struct radeon_fbdev *rfbdev;
 255         /* firmware flags */
 256         u16 firmware_flags;
 257         /* pointer to backlight encoder */
 258         struct radeon_encoder *bl_encoder;
 259 };
 260
 261 #define RADEON_MAX_BL_LEVEL 0xFF
 262
 263 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 264
 265 struct radeon_backlight_privdata {
 266         struct radeon_encoder *encoder;
 267         uint8_t negative;
 268 };
 269
 270 #endif
 271
 272 #define MAX_H_CODE_TIMING_LEN 32
 273 #define MAX_V_CODE_TIMING_LEN 32
 274
 275 /* need to store these as reading
 276    back code tables is excessive */
 277 struct radeon_tv_regs {
 278         uint32_t tv_uv_adr;
 279         uint32_t timing_cntl;
 280         uint32_t hrestart;
 281         uint32_t vrestart;
 282         uint32_t frestart;
 283         uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
 284         uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
 285 };
 286
 287 struct radeon_atom_ss {
 288         uint16_t percentage;
 289         uint8_t type;
 290         uint16_t step;
 291         uint8_t delay;
 292         uint8_t range;
 293         uint8_t refdiv;
 294         /* asic_ss */
 295         uint16_t rate;
 296         uint16_t amount;
 297 };
 298
 299 struct radeon_crtc {
 300         struct drm_crtc base;
 301         int crtc_id;
 302         u16 lut_r[256], lut_g[256], lut_b[256];
 303         bool enabled;
 304         bool can_tile;
 305         bool in_mode_set;
 306         uint32_t crtc_offset;
 307         struct drm_gem_object *cursor_bo;
 308         uint64_t cursor_addr;
 309         int cursor_width;
 310         int cursor_height;
 311         uint32_t legacy_display_base_addr;
 312         uint32_t legacy_cursor_offset;
 313         enum radeon_rmx_type rmx_type;
 314         u8 h_border;
 315         u8 v_border;
 316         fixed20_12 vsc;
 317         fixed20_12 hsc;
 318         struct drm_display_mode native_mode;
 319         int pll_id;
 320         /* page flipping */
 321         struct radeon_unpin_work *unpin_work;
 322         int deferred_flip_completion;
 323         /* pll sharing */
 324         struct radeon_atom_ss ss;
 325         bool ss_enabled;
 326         u32 adjusted_clock;
 327         int bpc;
 328         u32 pll_reference_div;
 329         u32 pll_post_div;
 330         u32 pll_flags;
 331         struct drm_encoder *encoder;
 332         struct drm_connector *connector;
 333 };
 334
 335 struct radeon_encoder_primary_dac {
 336         /* legacy primary dac */
 337         uint32_t ps2_pdac_adj;
 338 };
 339
 340 struct radeon_encoder_lvds {
 341         /* legacy lvds */
 342         uint16_t panel_vcc_delay;
 343         uint8_t  panel_pwr_delay;
 344         uint8_t  panel_digon_delay;
 345         uint8_t  panel_blon_delay;
 346         uint16_t panel_ref_divider;
 347         uint8_t  panel_post_divider;
 348         uint16_t panel_fb_divider;
 349         bool     use_bios_dividers;
 350         uint32_t lvds_gen_cntl;
 351         /* panel mode */
 352         struct drm_display_mode native_mode;
 353         struct backlight_device *bl_dev;
 354         int      dpms_mode;
 355         uint8_t  backlight_level;
 356 };
 357
 358 struct radeon_encoder_tv_dac {
 359         /* legacy tv dac */
 360         uint32_t ps2_tvdac_adj;
 361         uint32_t ntsc_tvdac_adj;
 362         uint32_t pal_tvdac_adj;
 363
 364         int               h_pos;
 365         int               v_pos;
 366         int               h_size;
 367         int               supported_tv_stds;
 368         bool              tv_on;
 369         enum radeon_tv_std tv_std;
 370         struct radeon_tv_regs tv;
 371 };
 372
 373 struct radeon_encoder_int_tmds {
 374         /* legacy int tmds */
 375         struct radeon_tmds_pll tmds_pll[4];
 376 };
 377
 378 struct radeon_encoder_ext_tmds {
 379         /* tmds over dvo */
 380         struct radeon_i2c_chan *i2c_bus;
 381         uint8_t slave_addr;
 382         enum radeon_dvo_chip dvo_chip;
 383 };
 384
 385 /* spread spectrum */
 386 struct radeon_encoder_atom_dig {
 387         bool linkb;
 388         /* atom dig */
 389         bool coherent_mode;
 390         int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
 391         /* atom lvds/edp */
 392         uint32_t lcd_misc;
 393         uint16_t panel_pwr_delay;
 394         uint32_t lcd_ss_id;
 395         /* panel mode */
 396         struct drm_display_mode native_mode;
 397         struct backlight_device *bl_dev;
 398         int dpms_mode;
 399         uint8_t backlight_level;
 400         int panel_mode;
 401         struct radeon_afmt *afmt;
 402 };
 403
 404 struct radeon_encoder_atom_dac {
 405         enum radeon_tv_std tv_std;
 406 };
 407
 408 struct radeon_encoder {
 409         struct drm_encoder base;
 410         uint32_t encoder_enum;
 411         uint32_t encoder_id;
 412         uint32_t devices;
 413         uint32_t active_device;
 414         uint32_t flags;
 415         uint32_t pixel_clock;
 416         enum radeon_rmx_type rmx_type;
 417         enum radeon_underscan_type underscan_type;
 418         uint32_t underscan_hborder;
 419         uint32_t underscan_vborder;
 420         struct drm_display_mode native_mode;
 421         void *enc_priv;
 422         int audio_polling_active;
 423         bool is_ext_encoder;
 424         u16 caps;
 425 };
 426
 427 struct radeon_connector_atom_dig {
 428         uint32_t igp_lane_info;
 429         /* displayport */
 430         struct radeon_i2c_chan *dp_i2c_bus;
 431         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 432         u8 dp_sink_type;
 433         int dp_clock;
 434         int dp_lane_count;
 435         bool edp_on;
 436 };
 437
 438 struct radeon_gpio_rec {
 439         bool valid;
 440         u8 id;
 441         u32 reg;
 442         u32 mask;
 443 };
 444
 445 struct radeon_hpd {
 446         enum radeon_hpd_id hpd;
 447         u8 plugged_state;
 448         struct radeon_gpio_rec gpio;
 449 };
 450
 451 struct radeon_router {
 452         u32 router_id;
 453         struct radeon_i2c_bus_rec i2c_info;
 454         u8 i2c_addr;
 455         /* i2c mux */
 456         bool ddc_valid;
 457         u8 ddc_mux_type;
 458         u8 ddc_mux_control_pin;
 459         u8 ddc_mux_state;
 460         /* clock/data mux */
 461         bool cd_valid;
 462         u8 cd_mux_type;
 463         u8 cd_mux_control_pin;
 464         u8 cd_mux_state;
 465 };
 466
 467 struct radeon_connector {
 468         struct drm_connector base;
 469         uint32_t connector_id;
 470         uint32_t devices;
 471         struct radeon_i2c_chan *ddc_bus;
 472         /* some systems have an hdmi and vga port with a shared ddc line */
 473         bool shared_ddc;
 474         bool use_digital;
 475         /* we need to mind the EDID between detect
 476            and get modes due to analog/digital/tvencoder */
 477         struct edid *edid;
 478         void *con_priv;
 479         bool dac_load_detect;
 480         bool detected_by_load; /* if the connection status was determined by load */
 481         uint16_t connector_object_id;
 482         struct radeon_hpd hpd;
 483         struct radeon_router router;
 484         struct radeon_i2c_chan *router_bus;
 485 };
 486
 487 struct radeon_framebuffer {
 488         struct drm_framebuffer base;
 489         struct drm_gem_object *obj;
 490 };
 491
 492 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
 493                                 ((em) == ATOM_ENCODER_MODE_DP_MST))
 494
 495 struct atom_clock_dividers {
 496         u32 post_div;
 497         union {
 498                 struct {
 499 #ifdef __BIG_ENDIAN
 500                         u32 reserved : 6;
 501                         u32 whole_fb_div : 12;
 502                         u32 frac_fb_div : 14;
 503 #else
 504                         u32 frac_fb_div : 14;
 505                         u32 whole_fb_div : 12;
 506                         u32 reserved : 6;
 507 #endif
 508                 };
 509                 u32 fb_div;
 510         };
 511         u32 ref_div;
 512         bool enable_post_div;
 513         bool enable_dithen;
 514         u32 vco_mode;
 515         u32 real_clock;
 516 };
 517
 518 extern enum radeon_tv_std
 519 radeon_combios_get_tv_info(struct radeon_device *rdev);
 520 extern enum radeon_tv_std
 521 radeon_atombios_get_tv_info(struct radeon_device *rdev);
 522
 523 extern struct drm_connector *
 524 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
 525 extern struct drm_connector *
 526 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
 527 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
 528                                     u32 pixel_clock);
 529
 530 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
 531 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
 532 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
 533 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
 534 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
 535
 536 extern void radeon_connector_hotplug(struct drm_connector *connector);
 537 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 538                                        struct drm_display_mode *mode);
 539 extern void radeon_dp_set_link_config(struct drm_connector *connector,
 540                                       const struct drm_display_mode *mode);
 541 extern void radeon_dp_link_train(struct drm_encoder *encoder,
 542                                  struct drm_connector *connector);
 543 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
 544 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
 545 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
 546 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 547                                     struct drm_connector *connector);
 548 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
 549 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
 550 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
 551 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
 552                                            int action, uint8_t lane_num,
 553                                            uint8_t lane_set);
 554 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
 555 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
 556 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 557                                 u8 write_byte, u8 *read_byte);
 558
 559 extern void radeon_i2c_init(struct radeon_device *rdev);
 560 extern void radeon_i2c_fini(struct radeon_device *rdev);
 561 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
 562 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
 563 extern void radeon_i2c_add(struct radeon_device *rdev,
 564                            struct radeon_i2c_bus_rec *rec,
 565                            const char *name);
 566 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
 567                                                  struct radeon_i2c_bus_rec *i2c_bus);
 568 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
 569                                                     struct radeon_i2c_bus_rec *rec,
 570                                                     const char *name);
 571 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 572                                                  struct radeon_i2c_bus_rec *rec,
 573                                                  const char *name);
 574 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
 575 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
 576                                 u8 slave_addr,
 577                                 u8 addr,
 578                                 u8 *val);
 579 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
 580                                 u8 slave_addr,
 581                                 u8 addr,
 582                                 u8 val);
 583 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
 584 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
 585 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
 586 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
 587
 588 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
 589
 590 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
 591                                              struct radeon_atom_ss *ss,
 592                                              int id);
 593 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
 594                                              struct radeon_atom_ss *ss,
 595                                              int id, u32 clock);
 596
 597 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
 598                                       uint64_t freq,
 599                                       uint32_t *dot_clock_p,
 600                                       uint32_t *fb_div_p,
 601                                       uint32_t *frac_fb_div_p,
 602                                       uint32_t *ref_div_p,
 603                                       uint32_t *post_div_p);
 604
 605 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
 606                                      u32 freq,
 607                                      u32 *dot_clock_p,
 608                                      u32 *fb_div_p,
 609                                      u32 *frac_fb_div_p,
 610                                      u32 *ref_div_p,
 611                                      u32 *post_div_p);
 612
 613 extern void radeon_setup_encoder_clones(struct drm_device *dev);
 614
 615 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
 616 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 617 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 618 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
 619 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
 620 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
 621 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
 622 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
 623 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
 624 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
 625
 626 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
 627 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 628                                    struct drm_framebuffer *old_fb);
 629 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
 630                                          struct drm_framebuffer *fb,
 631                                          int x, int y,
 632                                          enum mode_set_atomic state);
 633 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
 634                                    struct drm_display_mode *mode,
 635                                    struct drm_display_mode *adjusted_mode,
 636                                    int x, int y,
 637                                    struct drm_framebuffer *old_fb);
 638 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
 639
 640 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 641                                  struct drm_framebuffer *old_fb);
 642 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 643                                        struct drm_framebuffer *fb,
 644                                        int x, int y,
 645                                        enum mode_set_atomic state);
 646 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 647                                    struct drm_framebuffer *fb,
 648                                    int x, int y, int atomic);
 649 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
 650                                   struct drm_file *file_priv,
 651                                   uint32_t handle,
 652                                   uint32_t width,
 653                                   uint32_t height);
 654 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 655                                    int x, int y);
 656
 657 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
 658                                       int *vpos, int *hpos);
 659
 660 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
 661 extern struct edid *
 662 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
 663 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
 664 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
 665 extern struct radeon_encoder_atom_dig *
 666 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
 667 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 668                                           struct radeon_encoder_int_tmds *tmds);
 669 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
 670                                                      struct radeon_encoder_int_tmds *tmds);
 671 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
 672                                                    struct radeon_encoder_int_tmds *tmds);
 673 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
 674                                                          struct radeon_encoder_ext_tmds *tmds);
 675 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
 676                                                        struct radeon_encoder_ext_tmds *tmds);
 677 extern struct radeon_encoder_primary_dac *
 678 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
 679 extern struct radeon_encoder_tv_dac *
 680 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
 681 extern struct radeon_encoder_lvds *
 682 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
 683 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
 684 extern struct radeon_encoder_tv_dac *
 685 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
 686 extern struct radeon_encoder_primary_dac *
 687 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
 688 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
 689 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
 690 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
 691 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
 692 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
 693 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
 694 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
 695 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
 696 extern void
 697 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 698 extern void
 699 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 700 extern void
 701 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 702 extern void
 703 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 704 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 705                                      u16 blue, int regno);
 706 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 707                                      u16 *blue, int regno);
 708 int radeon_framebuffer_init(struct drm_device *dev,
 709                              struct radeon_framebuffer *rfb,
 710                              struct drm_mode_fb_cmd2 *mode_cmd,
 711                              struct drm_gem_object *obj);
 712
 713 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 714 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
 715 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
 716 void radeon_atombios_init_crtc(struct drm_device *dev,
 717                                struct radeon_crtc *radeon_crtc);
 718 void radeon_legacy_init_crtc(struct drm_device *dev,
 719                              struct radeon_crtc *radeon_crtc);
 720
 721 void radeon_get_clock_info(struct drm_device *dev);
 722
 723 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
 724 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
 725
 726 void radeon_enc_destroy(struct drm_encoder *encoder);
 727 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 728 void radeon_combios_asic_init(struct drm_device *dev);
 729 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 730                                         const struct drm_display_mode *mode,
 731                                         struct drm_display_mode *adjusted_mode);
 732 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 733                              struct drm_display_mode *adjusted_mode);
 734 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
 735
 736 /* legacy tv */
 737 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
 738                                       uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
 739                                       uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
 740 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
 741                                   uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
 742                                   uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
 743 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
 744                                   uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
 745                                   uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
 746 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
 747                                struct drm_display_mode *mode,
 748                                struct drm_display_mode *adjusted_mode);
 749
 750 /* fbdev layer */
 751 int radeon_fbdev_init(struct radeon_device *rdev);
 752 void radeon_fbdev_fini(struct radeon_device *rdev);
 753 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
 754 int radeon_fbdev_total_size(struct radeon_device *rdev);
 755 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
 756
 757 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
 758
 759 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
 760
 761 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
 762 #endif