2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "drm_sarea.h"
31 #include "radeon_drm.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
36 int radeon_driver_unload_kms(struct drm_device
*dev
)
38 struct radeon_device
*rdev
= dev
->dev_private
;
42 radeon_modeset_fini(rdev
);
43 radeon_device_fini(rdev
);
45 dev
->dev_private
= NULL
;
49 int radeon_driver_load_kms(struct drm_device
*dev
, unsigned long flags
)
51 struct radeon_device
*rdev
;
54 rdev
= kzalloc(sizeof(struct radeon_device
), GFP_KERNEL
);
58 dev
->dev_private
= (void *)rdev
;
61 if (drm_pci_device_is_agp(dev
)) {
62 flags
|= RADEON_IS_AGP
;
63 } else if (pci_is_pcie(dev
->pdev
)) {
64 flags
|= RADEON_IS_PCIE
;
66 flags
|= RADEON_IS_PCI
;
69 /* radeon_device_init should report only fatal error
70 * like memory allocation failure or iomapping failure,
71 * or memory manager initialization failure, it must
72 * properly initialize the GPU MC controller and permit
75 r
= radeon_device_init(rdev
, dev
, dev
->pdev
, flags
);
77 dev_err(&dev
->pdev
->dev
, "Fatal error during GPU init\n");
81 /* Call ACPI methods */
82 acpi_status
= radeon_acpi_init(rdev
);
84 dev_dbg(&dev
->pdev
->dev
, "Error during ACPI methods call\n");
86 /* Again modeset_init should fail only on fatal error
87 * otherwise it should provide enough functionalities
90 r
= radeon_modeset_init(rdev
);
92 dev_err(&dev
->pdev
->dev
, "Fatal error during modeset init\n");
95 radeon_driver_unload_kms(dev
);
99 static void radeon_set_filp_rights(struct drm_device
*dev
,
100 struct drm_file
**owner
,
101 struct drm_file
*applier
,
104 mutex_lock(&dev
->struct_mutex
);
109 } else if (*value
== 0) {
111 if (*owner
== applier
)
114 *value
= *owner
== applier
? 1 : 0;
115 mutex_unlock(&dev
->struct_mutex
);
119 * Userspace get information ioctl
121 int radeon_info_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
123 struct radeon_device
*rdev
= dev
->dev_private
;
124 struct drm_radeon_info
*info
;
125 struct radeon_mode_info
*minfo
= &rdev
->mode_info
;
128 struct drm_crtc
*crtc
;
132 value_ptr
= (uint32_t *)((unsigned long)info
->value
);
133 if (DRM_COPY_FROM_USER(&value
, value_ptr
, sizeof(value
)))
136 switch (info
->request
) {
137 case RADEON_INFO_DEVICE_ID
:
138 value
= dev
->pci_device
;
140 case RADEON_INFO_NUM_GB_PIPES
:
141 value
= rdev
->num_gb_pipes
;
143 case RADEON_INFO_NUM_Z_PIPES
:
144 value
= rdev
->num_z_pipes
;
146 case RADEON_INFO_ACCEL_WORKING
:
147 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
148 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
))
151 value
= rdev
->accel_working
;
153 case RADEON_INFO_CRTC_FROM_ID
:
154 for (i
= 0, found
= 0; i
< rdev
->num_crtc
; i
++) {
155 crtc
= (struct drm_crtc
*)minfo
->crtcs
[i
];
156 if (crtc
&& crtc
->base
.id
== value
) {
157 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
158 value
= radeon_crtc
->crtc_id
;
164 DRM_DEBUG_KMS("unknown crtc id %d\n", value
);
168 case RADEON_INFO_ACCEL_WORKING2
:
169 value
= rdev
->accel_working
;
171 case RADEON_INFO_TILING_CONFIG
:
172 if (rdev
->family
>= CHIP_TAHITI
)
173 value
= rdev
->config
.si
.tile_config
;
174 else if (rdev
->family
>= CHIP_CAYMAN
)
175 value
= rdev
->config
.cayman
.tile_config
;
176 else if (rdev
->family
>= CHIP_CEDAR
)
177 value
= rdev
->config
.evergreen
.tile_config
;
178 else if (rdev
->family
>= CHIP_RV770
)
179 value
= rdev
->config
.rv770
.tile_config
;
180 else if (rdev
->family
>= CHIP_R600
)
181 value
= rdev
->config
.r600
.tile_config
;
183 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
187 case RADEON_INFO_WANT_HYPERZ
:
188 /* The "value" here is both an input and output parameter.
189 * If the input value is 1, filp requests hyper-z access.
190 * If the input value is 0, filp revokes its hyper-z access.
192 * When returning, the value is 1 if filp owns hyper-z access,
195 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value
);
198 radeon_set_filp_rights(dev
, &rdev
->hyperz_filp
, filp
, &value
);
200 case RADEON_INFO_WANT_CMASK
:
201 /* The same logic as Hyper-Z. */
203 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value
);
206 radeon_set_filp_rights(dev
, &rdev
->cmask_filp
, filp
, &value
);
208 case RADEON_INFO_CLOCK_CRYSTAL_FREQ
:
209 /* return clock value in KHz */
210 value
= rdev
->clock
.spll
.reference_freq
* 10;
212 case RADEON_INFO_NUM_BACKENDS
:
213 if (rdev
->family
>= CHIP_TAHITI
)
214 value
= rdev
->config
.si
.max_backends_per_se
*
215 rdev
->config
.si
.max_shader_engines
;
216 else if (rdev
->family
>= CHIP_CAYMAN
)
217 value
= rdev
->config
.cayman
.max_backends_per_se
*
218 rdev
->config
.cayman
.max_shader_engines
;
219 else if (rdev
->family
>= CHIP_CEDAR
)
220 value
= rdev
->config
.evergreen
.max_backends
;
221 else if (rdev
->family
>= CHIP_RV770
)
222 value
= rdev
->config
.rv770
.max_backends
;
223 else if (rdev
->family
>= CHIP_R600
)
224 value
= rdev
->config
.r600
.max_backends
;
229 case RADEON_INFO_NUM_TILE_PIPES
:
230 if (rdev
->family
>= CHIP_TAHITI
)
231 value
= rdev
->config
.si
.max_tile_pipes
;
232 else if (rdev
->family
>= CHIP_CAYMAN
)
233 value
= rdev
->config
.cayman
.max_tile_pipes
;
234 else if (rdev
->family
>= CHIP_CEDAR
)
235 value
= rdev
->config
.evergreen
.max_tile_pipes
;
236 else if (rdev
->family
>= CHIP_RV770
)
237 value
= rdev
->config
.rv770
.max_tile_pipes
;
238 else if (rdev
->family
>= CHIP_R600
)
239 value
= rdev
->config
.r600
.max_tile_pipes
;
244 case RADEON_INFO_FUSION_GART_WORKING
:
247 case RADEON_INFO_BACKEND_MAP
:
248 if (rdev
->family
>= CHIP_TAHITI
)
249 value
= rdev
->config
.si
.backend_map
;
250 else if (rdev
->family
>= CHIP_CAYMAN
)
251 value
= rdev
->config
.cayman
.backend_map
;
252 else if (rdev
->family
>= CHIP_CEDAR
)
253 value
= rdev
->config
.evergreen
.backend_map
;
254 else if (rdev
->family
>= CHIP_RV770
)
255 value
= rdev
->config
.rv770
.backend_map
;
256 else if (rdev
->family
>= CHIP_R600
)
257 value
= rdev
->config
.r600
.backend_map
;
262 case RADEON_INFO_VA_START
:
263 /* this is where we report if vm is supported or not */
264 if (rdev
->family
< CHIP_CAYMAN
)
266 value
= RADEON_VA_RESERVED_SIZE
;
268 case RADEON_INFO_IB_VM_MAX_SIZE
:
269 /* this is where we report if vm is supported or not */
270 if (rdev
->family
< CHIP_CAYMAN
)
272 value
= RADEON_IB_VM_MAX_SIZE
;
274 case RADEON_INFO_MAX_PIPES
:
275 if (rdev
->family
>= CHIP_TAHITI
)
276 value
= rdev
->config
.si
.max_pipes_per_simd
;
277 else if (rdev
->family
>= CHIP_CAYMAN
)
278 value
= rdev
->config
.cayman
.max_pipes_per_simd
;
279 else if (rdev
->family
>= CHIP_CEDAR
)
280 value
= rdev
->config
.evergreen
.max_pipes
;
281 else if (rdev
->family
>= CHIP_RV770
)
282 value
= rdev
->config
.rv770
.max_pipes
;
283 else if (rdev
->family
>= CHIP_R600
)
284 value
= rdev
->config
.r600
.max_pipes
;
290 DRM_DEBUG_KMS("Invalid request %d\n", info
->request
);
293 if (DRM_COPY_TO_USER(value_ptr
, &value
, sizeof(uint32_t))) {
294 DRM_ERROR("copy_to_user\n");
302 * Outdated mess for old drm with Xorg being in charge (void function now).
304 int radeon_driver_firstopen_kms(struct drm_device
*dev
)
309 void radeon_driver_lastclose_kms(struct drm_device
*dev
)
311 vga_switcheroo_process_delayed_switch();
314 int radeon_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
)
316 struct radeon_device
*rdev
= dev
->dev_private
;
318 file_priv
->driver_priv
= NULL
;
320 /* new gpu have virtual address space support */
321 if (rdev
->family
>= CHIP_CAYMAN
) {
322 struct radeon_fpriv
*fpriv
;
325 fpriv
= kzalloc(sizeof(*fpriv
), GFP_KERNEL
);
326 if (unlikely(!fpriv
)) {
330 r
= radeon_vm_init(rdev
, &fpriv
->vm
);
332 radeon_vm_fini(rdev
, &fpriv
->vm
);
337 file_priv
->driver_priv
= fpriv
;
342 void radeon_driver_postclose_kms(struct drm_device
*dev
,
343 struct drm_file
*file_priv
)
345 struct radeon_device
*rdev
= dev
->dev_private
;
347 /* new gpu have virtual address space support */
348 if (rdev
->family
>= CHIP_CAYMAN
&& file_priv
->driver_priv
) {
349 struct radeon_fpriv
*fpriv
= file_priv
->driver_priv
;
351 radeon_vm_fini(rdev
, &fpriv
->vm
);
353 file_priv
->driver_priv
= NULL
;
357 void radeon_driver_preclose_kms(struct drm_device
*dev
,
358 struct drm_file
*file_priv
)
360 struct radeon_device
*rdev
= dev
->dev_private
;
361 if (rdev
->hyperz_filp
== file_priv
)
362 rdev
->hyperz_filp
= NULL
;
363 if (rdev
->cmask_filp
== file_priv
)
364 rdev
->cmask_filp
= NULL
;
368 * VBlank related functions.
370 u32
radeon_get_vblank_counter_kms(struct drm_device
*dev
, int crtc
)
372 struct radeon_device
*rdev
= dev
->dev_private
;
374 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
375 DRM_ERROR("Invalid crtc %d\n", crtc
);
379 return radeon_get_vblank_counter(rdev
, crtc
);
382 int radeon_enable_vblank_kms(struct drm_device
*dev
, int crtc
)
384 struct radeon_device
*rdev
= dev
->dev_private
;
386 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
387 DRM_ERROR("Invalid crtc %d\n", crtc
);
391 rdev
->irq
.crtc_vblank_int
[crtc
] = true;
393 return radeon_irq_set(rdev
);
396 void radeon_disable_vblank_kms(struct drm_device
*dev
, int crtc
)
398 struct radeon_device
*rdev
= dev
->dev_private
;
400 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
401 DRM_ERROR("Invalid crtc %d\n", crtc
);
405 rdev
->irq
.crtc_vblank_int
[crtc
] = false;
407 radeon_irq_set(rdev
);
410 int radeon_get_vblank_timestamp_kms(struct drm_device
*dev
, int crtc
,
412 struct timeval
*vblank_time
,
415 struct drm_crtc
*drmcrtc
;
416 struct radeon_device
*rdev
= dev
->dev_private
;
418 if (crtc
< 0 || crtc
>= dev
->num_crtcs
) {
419 DRM_ERROR("Invalid crtc %d\n", crtc
);
423 /* Get associated drm_crtc: */
424 drmcrtc
= &rdev
->mode_info
.crtcs
[crtc
]->base
;
426 /* Helper routine in DRM core does all the work: */
427 return drm_calc_vbltimestamp_from_scanoutpos(dev
, crtc
, max_error
,
435 int radeon_dma_ioctl_kms(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file_priv
)
438 /* Not valid in KMS. */
442 #define KMS_INVALID_IOCTL(name) \
443 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
445 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
450 * All these ioctls are invalid in kms world.
452 KMS_INVALID_IOCTL(radeon_cp_init_kms
)
453 KMS_INVALID_IOCTL(radeon_cp_start_kms
)
454 KMS_INVALID_IOCTL(radeon_cp_stop_kms
)
455 KMS_INVALID_IOCTL(radeon_cp_reset_kms
)
456 KMS_INVALID_IOCTL(radeon_cp_idle_kms
)
457 KMS_INVALID_IOCTL(radeon_cp_resume_kms
)
458 KMS_INVALID_IOCTL(radeon_engine_reset_kms
)
459 KMS_INVALID_IOCTL(radeon_fullscreen_kms
)
460 KMS_INVALID_IOCTL(radeon_cp_swap_kms
)
461 KMS_INVALID_IOCTL(radeon_cp_clear_kms
)
462 KMS_INVALID_IOCTL(radeon_cp_vertex_kms
)
463 KMS_INVALID_IOCTL(radeon_cp_indices_kms
)
464 KMS_INVALID_IOCTL(radeon_cp_texture_kms
)
465 KMS_INVALID_IOCTL(radeon_cp_stipple_kms
)
466 KMS_INVALID_IOCTL(radeon_cp_indirect_kms
)
467 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms
)
468 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms
)
469 KMS_INVALID_IOCTL(radeon_cp_getparam_kms
)
470 KMS_INVALID_IOCTL(radeon_cp_flip_kms
)
471 KMS_INVALID_IOCTL(radeon_mem_alloc_kms
)
472 KMS_INVALID_IOCTL(radeon_mem_free_kms
)
473 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms
)
474 KMS_INVALID_IOCTL(radeon_irq_emit_kms
)
475 KMS_INVALID_IOCTL(radeon_irq_wait_kms
)
476 KMS_INVALID_IOCTL(radeon_cp_setparam_kms
)
477 KMS_INVALID_IOCTL(radeon_surface_alloc_kms
)
478 KMS_INVALID_IOCTL(radeon_surface_free_kms
)
481 struct drm_ioctl_desc radeon_ioctls_kms
[] = {
482 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT
, radeon_cp_init_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
483 DRM_IOCTL_DEF_DRV(RADEON_CP_START
, radeon_cp_start_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
484 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP
, radeon_cp_stop_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
485 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET
, radeon_cp_reset_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
486 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE
, radeon_cp_idle_kms
, DRM_AUTH
),
487 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME
, radeon_cp_resume_kms
, DRM_AUTH
),
488 DRM_IOCTL_DEF_DRV(RADEON_RESET
, radeon_engine_reset_kms
, DRM_AUTH
),
489 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN
, radeon_fullscreen_kms
, DRM_AUTH
),
490 DRM_IOCTL_DEF_DRV(RADEON_SWAP
, radeon_cp_swap_kms
, DRM_AUTH
),
491 DRM_IOCTL_DEF_DRV(RADEON_CLEAR
, radeon_cp_clear_kms
, DRM_AUTH
),
492 DRM_IOCTL_DEF_DRV(RADEON_VERTEX
, radeon_cp_vertex_kms
, DRM_AUTH
),
493 DRM_IOCTL_DEF_DRV(RADEON_INDICES
, radeon_cp_indices_kms
, DRM_AUTH
),
494 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE
, radeon_cp_texture_kms
, DRM_AUTH
),
495 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE
, radeon_cp_stipple_kms
, DRM_AUTH
),
496 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT
, radeon_cp_indirect_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
497 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2
, radeon_cp_vertex2_kms
, DRM_AUTH
),
498 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF
, radeon_cp_cmdbuf_kms
, DRM_AUTH
),
499 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM
, radeon_cp_getparam_kms
, DRM_AUTH
),
500 DRM_IOCTL_DEF_DRV(RADEON_FLIP
, radeon_cp_flip_kms
, DRM_AUTH
),
501 DRM_IOCTL_DEF_DRV(RADEON_ALLOC
, radeon_mem_alloc_kms
, DRM_AUTH
),
502 DRM_IOCTL_DEF_DRV(RADEON_FREE
, radeon_mem_free_kms
, DRM_AUTH
),
503 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP
, radeon_mem_init_heap_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
504 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT
, radeon_irq_emit_kms
, DRM_AUTH
),
505 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT
, radeon_irq_wait_kms
, DRM_AUTH
),
506 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM
, radeon_cp_setparam_kms
, DRM_AUTH
),
507 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC
, radeon_surface_alloc_kms
, DRM_AUTH
),
508 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE
, radeon_surface_free_kms
, DRM_AUTH
),
510 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO
, radeon_gem_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
511 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE
, radeon_gem_create_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
512 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP
, radeon_gem_mmap_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
513 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN
, radeon_gem_set_domain_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
514 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD
, radeon_gem_pread_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
515 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE
, radeon_gem_pwrite_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
516 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE
, radeon_gem_wait_idle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
517 DRM_IOCTL_DEF_DRV(RADEON_CS
, radeon_cs_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
518 DRM_IOCTL_DEF_DRV(RADEON_INFO
, radeon_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
519 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING
, radeon_gem_set_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
520 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING
, radeon_gem_get_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
521 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY
, radeon_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
522 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA
, radeon_gem_va_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
524 int radeon_max_kms_ioctl
= DRM_ARRAY_SIZE(radeon_ioctls_kms
);