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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_i2c.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <linux/export.h>
27
28 #include <drm/drmP.h>
29 #include <drm/drm_edid.h>
30 #include <drm/radeon_drm.h>
31 #include "radeon.h"
32 #include "atom.h"
33
34 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
35 struct i2c_msg *msgs, int num);
36 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
37
38 /**
39 * radeon_ddc_probe
40 *
41 */
42 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
43 {
44 u8 out = 0x0;
45 u8 buf[8];
46 int ret;
47 struct i2c_msg msgs[] = {
48 {
49 .addr = DDC_ADDR,
50 .flags = 0,
51 .len = 1,
52 .buf = &out,
53 },
54 {
55 .addr = DDC_ADDR,
56 .flags = I2C_M_RD,
57 .len = 8,
58 .buf = buf,
59 }
60 };
61
62 /* on hw with routers, select right port */
63 if (radeon_connector->router.ddc_valid)
64 radeon_router_select_ddc_port(radeon_connector);
65
66 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
67 if (ret != 2)
68 /* Couldn't find an accessible DDC on this connector */
69 return false;
70 /* Probe also for valid EDID header
71 * EDID header starts with:
72 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
73 * Only the first 6 bytes must be valid as
74 * drm_edid_block_valid() can fix the last 2 bytes */
75 if (drm_edid_header_is_valid(buf) < 6) {
76 /* Couldn't find an accessible EDID on this
77 * connector */
78 return false;
79 }
80 return true;
81 }
82
83 /* bit banging i2c */
84
85 static int pre_xfer(struct i2c_adapter *i2c_adap)
86 {
87 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
88 struct radeon_device *rdev = i2c->dev->dev_private;
89 struct radeon_i2c_bus_rec *rec = &i2c->rec;
90 uint32_t temp;
91
92 /* RV410 appears to have a bug where the hw i2c in reset
93 * holds the i2c port in a bad state - switch hw i2c away before
94 * doing DDC - do this for all r200s/r300s/r400s for safety sake
95 */
96 if (rec->hw_capable) {
97 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
98 u32 reg;
99
100 if (rdev->family >= CHIP_RV350)
101 reg = RADEON_GPIO_MONID;
102 else if ((rdev->family == CHIP_R300) ||
103 (rdev->family == CHIP_R350))
104 reg = RADEON_GPIO_DVI_DDC;
105 else
106 reg = RADEON_GPIO_CRT2_DDC;
107
108 mutex_lock(&rdev->dc_hw_i2c_mutex);
109 if (rec->a_clk_reg == reg) {
110 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
111 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
112 } else {
113 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
114 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
115 }
116 mutex_unlock(&rdev->dc_hw_i2c_mutex);
117 }
118 }
119
120 /* switch the pads to ddc mode */
121 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
122 temp = RREG32(rec->mask_clk_reg);
123 temp &= ~(1 << 16);
124 WREG32(rec->mask_clk_reg, temp);
125 }
126
127 /* clear the output pin values */
128 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
129 WREG32(rec->a_clk_reg, temp);
130
131 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
132 WREG32(rec->a_data_reg, temp);
133
134 /* set the pins to input */
135 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
136 WREG32(rec->en_clk_reg, temp);
137
138 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
139 WREG32(rec->en_data_reg, temp);
140
141 /* mask the gpio pins for software use */
142 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
143 WREG32(rec->mask_clk_reg, temp);
144 temp = RREG32(rec->mask_clk_reg);
145
146 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
147 WREG32(rec->mask_data_reg, temp);
148 temp = RREG32(rec->mask_data_reg);
149
150 return 0;
151 }
152
153 static void post_xfer(struct i2c_adapter *i2c_adap)
154 {
155 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
156 struct radeon_device *rdev = i2c->dev->dev_private;
157 struct radeon_i2c_bus_rec *rec = &i2c->rec;
158 uint32_t temp;
159
160 /* unmask the gpio pins for software use */
161 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
162 WREG32(rec->mask_clk_reg, temp);
163 temp = RREG32(rec->mask_clk_reg);
164
165 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
166 WREG32(rec->mask_data_reg, temp);
167 temp = RREG32(rec->mask_data_reg);
168 }
169
170 static int get_clock(void *i2c_priv)
171 {
172 struct radeon_i2c_chan *i2c = i2c_priv;
173 struct radeon_device *rdev = i2c->dev->dev_private;
174 struct radeon_i2c_bus_rec *rec = &i2c->rec;
175 uint32_t val;
176
177 /* read the value off the pin */
178 val = RREG32(rec->y_clk_reg);
179 val &= rec->y_clk_mask;
180
181 return (val != 0);
182 }
183
184
185 static int get_data(void *i2c_priv)
186 {
187 struct radeon_i2c_chan *i2c = i2c_priv;
188 struct radeon_device *rdev = i2c->dev->dev_private;
189 struct radeon_i2c_bus_rec *rec = &i2c->rec;
190 uint32_t val;
191
192 /* read the value off the pin */
193 val = RREG32(rec->y_data_reg);
194 val &= rec->y_data_mask;
195
196 return (val != 0);
197 }
198
199 static void set_clock(void *i2c_priv, int clock)
200 {
201 struct radeon_i2c_chan *i2c = i2c_priv;
202 struct radeon_device *rdev = i2c->dev->dev_private;
203 struct radeon_i2c_bus_rec *rec = &i2c->rec;
204 uint32_t val;
205
206 /* set pin direction */
207 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
208 val |= clock ? 0 : rec->en_clk_mask;
209 WREG32(rec->en_clk_reg, val);
210 }
211
212 static void set_data(void *i2c_priv, int data)
213 {
214 struct radeon_i2c_chan *i2c = i2c_priv;
215 struct radeon_device *rdev = i2c->dev->dev_private;
216 struct radeon_i2c_bus_rec *rec = &i2c->rec;
217 uint32_t val;
218
219 /* set pin direction */
220 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
221 val |= data ? 0 : rec->en_data_mask;
222 WREG32(rec->en_data_reg, val);
223 }
224
225 /* hw i2c */
226
227 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
228 {
229 u32 sclk = rdev->pm.current_sclk;
230 u32 prescale = 0;
231 u32 nm;
232 u8 n, m, loop;
233 int i2c_clock;
234
235 switch (rdev->family) {
236 case CHIP_R100:
237 case CHIP_RV100:
238 case CHIP_RS100:
239 case CHIP_RV200:
240 case CHIP_RS200:
241 case CHIP_R200:
242 case CHIP_RV250:
243 case CHIP_RS300:
244 case CHIP_RV280:
245 case CHIP_R300:
246 case CHIP_R350:
247 case CHIP_RV350:
248 i2c_clock = 60;
249 nm = (sclk * 10) / (i2c_clock * 4);
250 for (loop = 1; loop < 255; loop++) {
251 if ((nm / loop) < loop)
252 break;
253 }
254 n = loop - 1;
255 m = loop - 2;
256 prescale = m | (n << 8);
257 break;
258 case CHIP_RV380:
259 case CHIP_RS400:
260 case CHIP_RS480:
261 case CHIP_R420:
262 case CHIP_R423:
263 case CHIP_RV410:
264 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
265 break;
266 case CHIP_RS600:
267 case CHIP_RS690:
268 case CHIP_RS740:
269 /* todo */
270 break;
271 case CHIP_RV515:
272 case CHIP_R520:
273 case CHIP_RV530:
274 case CHIP_RV560:
275 case CHIP_RV570:
276 case CHIP_R580:
277 i2c_clock = 50;
278 if (rdev->family == CHIP_R520)
279 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
280 else
281 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
282 break;
283 case CHIP_R600:
284 case CHIP_RV610:
285 case CHIP_RV630:
286 case CHIP_RV670:
287 /* todo */
288 break;
289 case CHIP_RV620:
290 case CHIP_RV635:
291 case CHIP_RS780:
292 case CHIP_RS880:
293 case CHIP_RV770:
294 case CHIP_RV730:
295 case CHIP_RV710:
296 case CHIP_RV740:
297 /* todo */
298 break;
299 case CHIP_CEDAR:
300 case CHIP_REDWOOD:
301 case CHIP_JUNIPER:
302 case CHIP_CYPRESS:
303 case CHIP_HEMLOCK:
304 /* todo */
305 break;
306 default:
307 DRM_ERROR("i2c: unhandled radeon chip\n");
308 break;
309 }
310 return prescale;
311 }
312
313
314 /* hw i2c engine for r1xx-4xx hardware
315 * hw can buffer up to 15 bytes
316 */
317 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
318 struct i2c_msg *msgs, int num)
319 {
320 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
321 struct radeon_device *rdev = i2c->dev->dev_private;
322 struct radeon_i2c_bus_rec *rec = &i2c->rec;
323 struct i2c_msg *p;
324 int i, j, k, ret = num;
325 u32 prescale;
326 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
327 u32 tmp, reg;
328
329 mutex_lock(&rdev->dc_hw_i2c_mutex);
330 /* take the pm lock since we need a constant sclk */
331 mutex_lock(&rdev->pm.mutex);
332
333 prescale = radeon_get_i2c_prescale(rdev);
334
335 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
336 RADEON_I2C_DRIVE_EN |
337 RADEON_I2C_START |
338 RADEON_I2C_STOP |
339 RADEON_I2C_GO);
340
341 if (rdev->is_atom_bios) {
342 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
343 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
344 }
345
346 if (rec->mm_i2c) {
347 i2c_cntl_0 = RADEON_I2C_CNTL_0;
348 i2c_cntl_1 = RADEON_I2C_CNTL_1;
349 i2c_data = RADEON_I2C_DATA;
350 } else {
351 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
352 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
353 i2c_data = RADEON_DVI_I2C_DATA;
354
355 switch (rdev->family) {
356 case CHIP_R100:
357 case CHIP_RV100:
358 case CHIP_RS100:
359 case CHIP_RV200:
360 case CHIP_RS200:
361 case CHIP_RS300:
362 switch (rec->mask_clk_reg) {
363 case RADEON_GPIO_DVI_DDC:
364 /* no gpio select bit */
365 break;
366 default:
367 DRM_ERROR("gpio not supported with hw i2c\n");
368 ret = -EINVAL;
369 goto done;
370 }
371 break;
372 case CHIP_R200:
373 /* only bit 4 on r200 */
374 switch (rec->mask_clk_reg) {
375 case RADEON_GPIO_DVI_DDC:
376 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
377 break;
378 case RADEON_GPIO_MONID:
379 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
380 break;
381 default:
382 DRM_ERROR("gpio not supported with hw i2c\n");
383 ret = -EINVAL;
384 goto done;
385 }
386 break;
387 case CHIP_RV250:
388 case CHIP_RV280:
389 /* bits 3 and 4 */
390 switch (rec->mask_clk_reg) {
391 case RADEON_GPIO_DVI_DDC:
392 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
393 break;
394 case RADEON_GPIO_VGA_DDC:
395 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
396 break;
397 case RADEON_GPIO_CRT2_DDC:
398 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
399 break;
400 default:
401 DRM_ERROR("gpio not supported with hw i2c\n");
402 ret = -EINVAL;
403 goto done;
404 }
405 break;
406 case CHIP_R300:
407 case CHIP_R350:
408 /* only bit 4 on r300/r350 */
409 switch (rec->mask_clk_reg) {
410 case RADEON_GPIO_VGA_DDC:
411 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
412 break;
413 case RADEON_GPIO_DVI_DDC:
414 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
415 break;
416 default:
417 DRM_ERROR("gpio not supported with hw i2c\n");
418 ret = -EINVAL;
419 goto done;
420 }
421 break;
422 case CHIP_RV350:
423 case CHIP_RV380:
424 case CHIP_R420:
425 case CHIP_R423:
426 case CHIP_RV410:
427 case CHIP_RS400:
428 case CHIP_RS480:
429 /* bits 3 and 4 */
430 switch (rec->mask_clk_reg) {
431 case RADEON_GPIO_VGA_DDC:
432 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
433 break;
434 case RADEON_GPIO_DVI_DDC:
435 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
436 break;
437 case RADEON_GPIO_MONID:
438 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
439 break;
440 default:
441 DRM_ERROR("gpio not supported with hw i2c\n");
442 ret = -EINVAL;
443 goto done;
444 }
445 break;
446 default:
447 DRM_ERROR("unsupported asic\n");
448 ret = -EINVAL;
449 goto done;
450 break;
451 }
452 }
453
454 /* check for bus probe */
455 p = &msgs[0];
456 if ((num == 1) && (p->len == 0)) {
457 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
458 RADEON_I2C_NACK |
459 RADEON_I2C_HALT |
460 RADEON_I2C_SOFT_RST));
461 WREG32(i2c_data, (p->addr << 1) & 0xff);
462 WREG32(i2c_data, 0);
463 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
464 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
465 RADEON_I2C_EN |
466 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
467 WREG32(i2c_cntl_0, reg);
468 for (k = 0; k < 32; k++) {
469 udelay(10);
470 tmp = RREG32(i2c_cntl_0);
471 if (tmp & RADEON_I2C_GO)
472 continue;
473 tmp = RREG32(i2c_cntl_0);
474 if (tmp & RADEON_I2C_DONE)
475 break;
476 else {
477 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
478 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
479 ret = -EIO;
480 goto done;
481 }
482 }
483 goto done;
484 }
485
486 for (i = 0; i < num; i++) {
487 p = &msgs[i];
488 for (j = 0; j < p->len; j++) {
489 if (p->flags & I2C_M_RD) {
490 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
491 RADEON_I2C_NACK |
492 RADEON_I2C_HALT |
493 RADEON_I2C_SOFT_RST));
494 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
495 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
496 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
497 RADEON_I2C_EN |
498 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
499 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
500 for (k = 0; k < 32; k++) {
501 udelay(10);
502 tmp = RREG32(i2c_cntl_0);
503 if (tmp & RADEON_I2C_GO)
504 continue;
505 tmp = RREG32(i2c_cntl_0);
506 if (tmp & RADEON_I2C_DONE)
507 break;
508 else {
509 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
510 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
511 ret = -EIO;
512 goto done;
513 }
514 }
515 p->buf[j] = RREG32(i2c_data) & 0xff;
516 } else {
517 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
518 RADEON_I2C_NACK |
519 RADEON_I2C_HALT |
520 RADEON_I2C_SOFT_RST));
521 WREG32(i2c_data, (p->addr << 1) & 0xff);
522 WREG32(i2c_data, p->buf[j]);
523 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
524 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
525 RADEON_I2C_EN |
526 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
527 WREG32(i2c_cntl_0, reg);
528 for (k = 0; k < 32; k++) {
529 udelay(10);
530 tmp = RREG32(i2c_cntl_0);
531 if (tmp & RADEON_I2C_GO)
532 continue;
533 tmp = RREG32(i2c_cntl_0);
534 if (tmp & RADEON_I2C_DONE)
535 break;
536 else {
537 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
538 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
539 ret = -EIO;
540 goto done;
541 }
542 }
543 }
544 }
545 }
546
547 done:
548 WREG32(i2c_cntl_0, 0);
549 WREG32(i2c_cntl_1, 0);
550 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
551 RADEON_I2C_NACK |
552 RADEON_I2C_HALT |
553 RADEON_I2C_SOFT_RST));
554
555 if (rdev->is_atom_bios) {
556 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
557 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
558 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
559 }
560
561 mutex_unlock(&rdev->pm.mutex);
562 mutex_unlock(&rdev->dc_hw_i2c_mutex);
563
564 return ret;
565 }
566
567 /* hw i2c engine for r5xx hardware
568 * hw can buffer up to 15 bytes
569 */
570 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
571 struct i2c_msg *msgs, int num)
572 {
573 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
574 struct radeon_device *rdev = i2c->dev->dev_private;
575 struct radeon_i2c_bus_rec *rec = &i2c->rec;
576 struct i2c_msg *p;
577 int i, j, remaining, current_count, buffer_offset, ret = num;
578 u32 prescale;
579 u32 tmp, reg;
580 u32 saved1, saved2;
581
582 mutex_lock(&rdev->dc_hw_i2c_mutex);
583 /* take the pm lock since we need a constant sclk */
584 mutex_lock(&rdev->pm.mutex);
585
586 prescale = radeon_get_i2c_prescale(rdev);
587
588 /* clear gpio mask bits */
589 tmp = RREG32(rec->mask_clk_reg);
590 tmp &= ~rec->mask_clk_mask;
591 WREG32(rec->mask_clk_reg, tmp);
592 tmp = RREG32(rec->mask_clk_reg);
593
594 tmp = RREG32(rec->mask_data_reg);
595 tmp &= ~rec->mask_data_mask;
596 WREG32(rec->mask_data_reg, tmp);
597 tmp = RREG32(rec->mask_data_reg);
598
599 /* clear pin values */
600 tmp = RREG32(rec->a_clk_reg);
601 tmp &= ~rec->a_clk_mask;
602 WREG32(rec->a_clk_reg, tmp);
603 tmp = RREG32(rec->a_clk_reg);
604
605 tmp = RREG32(rec->a_data_reg);
606 tmp &= ~rec->a_data_mask;
607 WREG32(rec->a_data_reg, tmp);
608 tmp = RREG32(rec->a_data_reg);
609
610 /* set the pins to input */
611 tmp = RREG32(rec->en_clk_reg);
612 tmp &= ~rec->en_clk_mask;
613 WREG32(rec->en_clk_reg, tmp);
614 tmp = RREG32(rec->en_clk_reg);
615
616 tmp = RREG32(rec->en_data_reg);
617 tmp &= ~rec->en_data_mask;
618 WREG32(rec->en_data_reg, tmp);
619 tmp = RREG32(rec->en_data_reg);
620
621 /* */
622 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
623 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
624 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
625 saved2 = RREG32(0x494);
626 WREG32(0x494, saved2 | 0x1);
627
628 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
629 for (i = 0; i < 50; i++) {
630 udelay(1);
631 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
632 break;
633 }
634 if (i == 50) {
635 DRM_ERROR("failed to get i2c bus\n");
636 ret = -EBUSY;
637 goto done;
638 }
639
640 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
641 switch (rec->mask_clk_reg) {
642 case AVIVO_DC_GPIO_DDC1_MASK:
643 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
644 break;
645 case AVIVO_DC_GPIO_DDC2_MASK:
646 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
647 break;
648 case AVIVO_DC_GPIO_DDC3_MASK:
649 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
650 break;
651 default:
652 DRM_ERROR("gpio not supported with hw i2c\n");
653 ret = -EINVAL;
654 goto done;
655 }
656
657 /* check for bus probe */
658 p = &msgs[0];
659 if ((num == 1) && (p->len == 0)) {
660 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
661 AVIVO_DC_I2C_NACK |
662 AVIVO_DC_I2C_HALT));
663 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
664 udelay(1);
665 WREG32(AVIVO_DC_I2C_RESET, 0);
666
667 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
668 WREG32(AVIVO_DC_I2C_DATA, 0);
669
670 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
671 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
672 AVIVO_DC_I2C_DATA_COUNT(1) |
673 (prescale << 16)));
674 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
675 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
676 for (j = 0; j < 200; j++) {
677 udelay(50);
678 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
679 if (tmp & AVIVO_DC_I2C_GO)
680 continue;
681 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
682 if (tmp & AVIVO_DC_I2C_DONE)
683 break;
684 else {
685 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
686 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
687 ret = -EIO;
688 goto done;
689 }
690 }
691 goto done;
692 }
693
694 for (i = 0; i < num; i++) {
695 p = &msgs[i];
696 remaining = p->len;
697 buffer_offset = 0;
698 if (p->flags & I2C_M_RD) {
699 while (remaining) {
700 if (remaining > 15)
701 current_count = 15;
702 else
703 current_count = remaining;
704 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
705 AVIVO_DC_I2C_NACK |
706 AVIVO_DC_I2C_HALT));
707 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
708 udelay(1);
709 WREG32(AVIVO_DC_I2C_RESET, 0);
710
711 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
712 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
713 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
714 AVIVO_DC_I2C_DATA_COUNT(current_count) |
715 (prescale << 16)));
716 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
717 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
718 for (j = 0; j < 200; j++) {
719 udelay(50);
720 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
721 if (tmp & AVIVO_DC_I2C_GO)
722 continue;
723 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
724 if (tmp & AVIVO_DC_I2C_DONE)
725 break;
726 else {
727 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
728 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
729 ret = -EIO;
730 goto done;
731 }
732 }
733 for (j = 0; j < current_count; j++)
734 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
735 remaining -= current_count;
736 buffer_offset += current_count;
737 }
738 } else {
739 while (remaining) {
740 if (remaining > 15)
741 current_count = 15;
742 else
743 current_count = remaining;
744 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
745 AVIVO_DC_I2C_NACK |
746 AVIVO_DC_I2C_HALT));
747 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
748 udelay(1);
749 WREG32(AVIVO_DC_I2C_RESET, 0);
750
751 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
752 for (j = 0; j < current_count; j++)
753 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
754
755 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
756 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
757 AVIVO_DC_I2C_DATA_COUNT(current_count) |
758 (prescale << 16)));
759 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
760 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
761 for (j = 0; j < 200; j++) {
762 udelay(50);
763 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
764 if (tmp & AVIVO_DC_I2C_GO)
765 continue;
766 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
767 if (tmp & AVIVO_DC_I2C_DONE)
768 break;
769 else {
770 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
771 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
772 ret = -EIO;
773 goto done;
774 }
775 }
776 remaining -= current_count;
777 buffer_offset += current_count;
778 }
779 }
780 }
781
782 done:
783 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
784 AVIVO_DC_I2C_NACK |
785 AVIVO_DC_I2C_HALT));
786 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
787 udelay(1);
788 WREG32(AVIVO_DC_I2C_RESET, 0);
789
790 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
791 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
792 WREG32(0x494, saved2);
793 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
794 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
795 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
796
797 mutex_unlock(&rdev->pm.mutex);
798 mutex_unlock(&rdev->dc_hw_i2c_mutex);
799
800 return ret;
801 }
802
803 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
804 struct i2c_msg *msgs, int num)
805 {
806 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
807 struct radeon_device *rdev = i2c->dev->dev_private;
808 struct radeon_i2c_bus_rec *rec = &i2c->rec;
809 int ret = 0;
810
811 switch (rdev->family) {
812 case CHIP_R100:
813 case CHIP_RV100:
814 case CHIP_RS100:
815 case CHIP_RV200:
816 case CHIP_RS200:
817 case CHIP_R200:
818 case CHIP_RV250:
819 case CHIP_RS300:
820 case CHIP_RV280:
821 case CHIP_R300:
822 case CHIP_R350:
823 case CHIP_RV350:
824 case CHIP_RV380:
825 case CHIP_R420:
826 case CHIP_R423:
827 case CHIP_RV410:
828 case CHIP_RS400:
829 case CHIP_RS480:
830 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
831 break;
832 case CHIP_RS600:
833 case CHIP_RS690:
834 case CHIP_RS740:
835 /* XXX fill in hw i2c implementation */
836 break;
837 case CHIP_RV515:
838 case CHIP_R520:
839 case CHIP_RV530:
840 case CHIP_RV560:
841 case CHIP_RV570:
842 case CHIP_R580:
843 if (rec->mm_i2c)
844 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
845 else
846 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
847 break;
848 case CHIP_R600:
849 case CHIP_RV610:
850 case CHIP_RV630:
851 case CHIP_RV670:
852 /* XXX fill in hw i2c implementation */
853 break;
854 case CHIP_RV620:
855 case CHIP_RV635:
856 case CHIP_RS780:
857 case CHIP_RS880:
858 case CHIP_RV770:
859 case CHIP_RV730:
860 case CHIP_RV710:
861 case CHIP_RV740:
862 /* XXX fill in hw i2c implementation */
863 break;
864 case CHIP_CEDAR:
865 case CHIP_REDWOOD:
866 case CHIP_JUNIPER:
867 case CHIP_CYPRESS:
868 case CHIP_HEMLOCK:
869 /* XXX fill in hw i2c implementation */
870 break;
871 default:
872 DRM_ERROR("i2c: unhandled radeon chip\n");
873 ret = -EIO;
874 break;
875 }
876
877 return ret;
878 }
879
880 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
881 {
882 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
883 }
884
885 static const struct i2c_algorithm radeon_i2c_algo = {
886 .master_xfer = radeon_hw_i2c_xfer,
887 .functionality = radeon_hw_i2c_func,
888 };
889
890 static const struct i2c_algorithm radeon_atom_i2c_algo = {
891 .master_xfer = radeon_atom_hw_i2c_xfer,
892 .functionality = radeon_atom_hw_i2c_func,
893 };
894
895 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
896 struct radeon_i2c_bus_rec *rec,
897 const char *name)
898 {
899 struct radeon_device *rdev = dev->dev_private;
900 struct radeon_i2c_chan *i2c;
901 int ret;
902
903 /* don't add the mm_i2c bus unless hw_i2c is enabled */
904 if (rec->mm_i2c && (radeon_hw_i2c == 0))
905 return NULL;
906
907 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
908 if (i2c == NULL)
909 return NULL;
910
911 i2c->rec = *rec;
912 i2c->adapter.owner = THIS_MODULE;
913 i2c->adapter.class = I2C_CLASS_DDC;
914 i2c->adapter.dev.parent = &dev->pdev->dev;
915 i2c->dev = dev;
916 i2c_set_adapdata(&i2c->adapter, i2c);
917 if (rec->mm_i2c ||
918 (rec->hw_capable &&
919 radeon_hw_i2c &&
920 ((rdev->family <= CHIP_RS480) ||
921 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
922 /* set the radeon hw i2c adapter */
923 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
924 "Radeon i2c hw bus %s", name);
925 i2c->adapter.algo = &radeon_i2c_algo;
926 ret = i2c_add_adapter(&i2c->adapter);
927 if (ret) {
928 DRM_ERROR("Failed to register hw i2c %s\n", name);
929 goto out_free;
930 }
931 } else if (rec->hw_capable &&
932 radeon_hw_i2c &&
933 ASIC_IS_DCE3(rdev)) {
934 /* hw i2c using atom */
935 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
936 "Radeon i2c hw bus %s", name);
937 i2c->adapter.algo = &radeon_atom_i2c_algo;
938 ret = i2c_add_adapter(&i2c->adapter);
939 if (ret) {
940 DRM_ERROR("Failed to register hw i2c %s\n", name);
941 goto out_free;
942 }
943 } else {
944 /* set the radeon bit adapter */
945 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
946 "Radeon i2c bit bus %s", name);
947 i2c->adapter.algo_data = &i2c->algo.bit;
948 i2c->algo.bit.pre_xfer = pre_xfer;
949 i2c->algo.bit.post_xfer = post_xfer;
950 i2c->algo.bit.setsda = set_data;
951 i2c->algo.bit.setscl = set_clock;
952 i2c->algo.bit.getsda = get_data;
953 i2c->algo.bit.getscl = get_clock;
954 i2c->algo.bit.udelay = 10;
955 i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */
956 i2c->algo.bit.data = i2c;
957 ret = i2c_bit_add_bus(&i2c->adapter);
958 if (ret) {
959 DRM_ERROR("Failed to register bit i2c %s\n", name);
960 goto out_free;
961 }
962 }
963
964 return i2c;
965 out_free:
966 kfree(i2c);
967 return NULL;
968
969 }
970
971 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
972 struct radeon_i2c_bus_rec *rec,
973 const char *name)
974 {
975 struct radeon_i2c_chan *i2c;
976 int ret;
977
978 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
979 if (i2c == NULL)
980 return NULL;
981
982 i2c->rec = *rec;
983 i2c->adapter.owner = THIS_MODULE;
984 i2c->adapter.class = I2C_CLASS_DDC;
985 i2c->adapter.dev.parent = &dev->pdev->dev;
986 i2c->dev = dev;
987 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
988 "Radeon aux bus %s", name);
989 i2c_set_adapdata(&i2c->adapter, i2c);
990 i2c->adapter.algo_data = &i2c->algo.dp;
991 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
992 i2c->algo.dp.address = 0;
993 ret = i2c_dp_aux_add_bus(&i2c->adapter);
994 if (ret) {
995 DRM_INFO("Failed to register i2c %s\n", name);
996 goto out_free;
997 }
998
999 return i2c;
1000 out_free:
1001 kfree(i2c);
1002 return NULL;
1003
1004 }
1005
1006 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1007 {
1008 if (!i2c)
1009 return;
1010 i2c_del_adapter(&i2c->adapter);
1011 kfree(i2c);
1012 }
1013
1014 /* Add the default buses */
1015 void radeon_i2c_init(struct radeon_device *rdev)
1016 {
1017 if (rdev->is_atom_bios)
1018 radeon_atombios_i2c_init(rdev);
1019 else
1020 radeon_combios_i2c_init(rdev);
1021 }
1022
1023 /* remove all the buses */
1024 void radeon_i2c_fini(struct radeon_device *rdev)
1025 {
1026 int i;
1027
1028 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1029 if (rdev->i2c_bus[i]) {
1030 radeon_i2c_destroy(rdev->i2c_bus[i]);
1031 rdev->i2c_bus[i] = NULL;
1032 }
1033 }
1034 }
1035
1036 /* Add additional buses */
1037 void radeon_i2c_add(struct radeon_device *rdev,
1038 struct radeon_i2c_bus_rec *rec,
1039 const char *name)
1040 {
1041 struct drm_device *dev = rdev->ddev;
1042 int i;
1043
1044 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1045 if (!rdev->i2c_bus[i]) {
1046 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1047 return;
1048 }
1049 }
1050 }
1051
1052 /* looks up bus based on id */
1053 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1054 struct radeon_i2c_bus_rec *i2c_bus)
1055 {
1056 int i;
1057
1058 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1059 if (rdev->i2c_bus[i] &&
1060 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1061 return rdev->i2c_bus[i];
1062 }
1063 }
1064 return NULL;
1065 }
1066
1067 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1068 {
1069 return NULL;
1070 }
1071
1072 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1073 u8 slave_addr,
1074 u8 addr,
1075 u8 *val)
1076 {
1077 u8 out_buf[2];
1078 u8 in_buf[2];
1079 struct i2c_msg msgs[] = {
1080 {
1081 .addr = slave_addr,
1082 .flags = 0,
1083 .len = 1,
1084 .buf = out_buf,
1085 },
1086 {
1087 .addr = slave_addr,
1088 .flags = I2C_M_RD,
1089 .len = 1,
1090 .buf = in_buf,
1091 }
1092 };
1093
1094 out_buf[0] = addr;
1095 out_buf[1] = 0;
1096
1097 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1098 *val = in_buf[0];
1099 DRM_DEBUG("val = 0x%02x\n", *val);
1100 } else {
1101 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1102 addr, *val);
1103 }
1104 }
1105
1106 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1107 u8 slave_addr,
1108 u8 addr,
1109 u8 val)
1110 {
1111 uint8_t out_buf[2];
1112 struct i2c_msg msg = {
1113 .addr = slave_addr,
1114 .flags = 0,
1115 .len = 2,
1116 .buf = out_buf,
1117 };
1118
1119 out_buf[0] = addr;
1120 out_buf[1] = val;
1121
1122 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1123 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1124 addr, val);
1125 }
1126
1127 /* ddc router switching */
1128 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1129 {
1130 u8 val;
1131
1132 if (!radeon_connector->router.ddc_valid)
1133 return;
1134
1135 if (!radeon_connector->router_bus)
1136 return;
1137
1138 radeon_i2c_get_byte(radeon_connector->router_bus,
1139 radeon_connector->router.i2c_addr,
1140 0x3, &val);
1141 val &= ~radeon_connector->router.ddc_mux_control_pin;
1142 radeon_i2c_put_byte(radeon_connector->router_bus,
1143 radeon_connector->router.i2c_addr,
1144 0x3, val);
1145 radeon_i2c_get_byte(radeon_connector->router_bus,
1146 radeon_connector->router.i2c_addr,
1147 0x1, &val);
1148 val &= ~radeon_connector->router.ddc_mux_control_pin;
1149 val |= radeon_connector->router.ddc_mux_state;
1150 radeon_i2c_put_byte(radeon_connector->router_bus,
1151 radeon_connector->router.i2c_addr,
1152 0x1, val);
1153 }
1154
1155 /* clock/data router switching */
1156 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1157 {
1158 u8 val;
1159
1160 if (!radeon_connector->router.cd_valid)
1161 return;
1162
1163 if (!radeon_connector->router_bus)
1164 return;
1165
1166 radeon_i2c_get_byte(radeon_connector->router_bus,
1167 radeon_connector->router.i2c_addr,
1168 0x3, &val);
1169 val &= ~radeon_connector->router.cd_mux_control_pin;
1170 radeon_i2c_put_byte(radeon_connector->router_bus,
1171 radeon_connector->router.i2c_addr,
1172 0x3, val);
1173 radeon_i2c_get_byte(radeon_connector->router_bus,
1174 radeon_connector->router.i2c_addr,
1175 0x1, &val);
1176 val &= ~radeon_connector->router.cd_mux_control_pin;
1177 val |= radeon_connector->router.cd_mux_state;
1178 radeon_i2c_put_byte(radeon_connector->router_bus,
1179 radeon_connector->router.i2c_addr,
1180 0x1, val);
1181 }
1182
kernel source for telekom puls (alcatel/mediatek)