2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector
*connector
);
38 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 struct drm_device
*dev
= crtc
->dev
;
42 struct radeon_device
*rdev
= dev
->dev_private
;
45 DRM_DEBUG("%d\n", radeon_crtc
->crtc_id
);
46 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
57 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
61 for (i
= 0; i
< 256; i
++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR
,
63 (radeon_crtc
->lut_r
[i
] << 20) |
64 (radeon_crtc
->lut_g
[i
] << 10) |
65 (radeon_crtc
->lut_b
[i
] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
);
71 static void evergreen_crtc_load_lut(struct drm_crtc
*crtc
)
73 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
74 struct drm_device
*dev
= crtc
->dev
;
75 struct radeon_device
*rdev
= dev
->dev_private
;
78 DRM_DEBUG("%d\n", radeon_crtc
->crtc_id
);
79 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
93 for (i
= 0; i
< 256; i
++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
95 (radeon_crtc
->lut_r
[i
] << 20) |
96 (radeon_crtc
->lut_g
[i
] << 10) |
97 (radeon_crtc
->lut_b
[i
] << 0));
101 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
103 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
104 struct drm_device
*dev
= crtc
->dev
;
105 struct radeon_device
*rdev
= dev
->dev_private
;
109 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
110 if (radeon_crtc
->crtc_id
== 0)
111 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
113 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
114 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
116 WREG8(RADEON_PALETTE_INDEX
, 0);
117 for (i
= 0; i
< 256; i
++) {
118 WREG32(RADEON_PALETTE_30_DATA
,
119 (radeon_crtc
->lut_r
[i
] << 20) |
120 (radeon_crtc
->lut_g
[i
] << 10) |
121 (radeon_crtc
->lut_b
[i
] << 0));
125 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
127 struct drm_device
*dev
= crtc
->dev
;
128 struct radeon_device
*rdev
= dev
->dev_private
;
133 if (ASIC_IS_DCE4(rdev
))
134 evergreen_crtc_load_lut(crtc
);
135 else if (ASIC_IS_AVIVO(rdev
))
136 avivo_crtc_load_lut(crtc
);
138 legacy_crtc_load_lut(crtc
);
141 /** Sets the color ramps on behalf of fbcon */
142 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
145 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
147 radeon_crtc
->lut_r
[regno
] = red
>> 6;
148 radeon_crtc
->lut_g
[regno
] = green
>> 6;
149 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
152 /** Gets the color ramps on behalf of fbcon */
153 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
154 u16
*blue
, int regno
)
156 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
158 *red
= radeon_crtc
->lut_r
[regno
] << 6;
159 *green
= radeon_crtc
->lut_g
[regno
] << 6;
160 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
163 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
164 u16
*blue
, uint32_t size
)
166 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
173 /* userspace palettes are always correct as is */
174 for (i
= 0; i
< 256; i
++) {
175 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
176 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
177 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
179 radeon_crtc_load_lut(crtc
);
182 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
184 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
186 drm_crtc_cleanup(crtc
);
190 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
191 .cursor_set
= radeon_crtc_cursor_set
,
192 .cursor_move
= radeon_crtc_cursor_move
,
193 .gamma_set
= radeon_crtc_gamma_set
,
194 .set_config
= drm_crtc_helper_set_config
,
195 .destroy
= radeon_crtc_destroy
,
198 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
200 struct radeon_device
*rdev
= dev
->dev_private
;
201 struct radeon_crtc
*radeon_crtc
;
204 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
205 if (radeon_crtc
== NULL
)
208 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
210 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
211 radeon_crtc
->crtc_id
= index
;
212 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
215 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
216 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
217 radeon_crtc
->mode_set
.num_connectors
= 0;
220 for (i
= 0; i
< 256; i
++) {
221 radeon_crtc
->lut_r
[i
] = i
<< 2;
222 radeon_crtc
->lut_g
[i
] = i
<< 2;
223 radeon_crtc
->lut_b
[i
] = i
<< 2;
226 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
227 radeon_atombios_init_crtc(dev
, radeon_crtc
);
229 radeon_legacy_init_crtc(dev
, radeon_crtc
);
232 static const char *encoder_names
[34] = {
252 "INTERNAL_KLDSCP_TMDS1",
253 "INTERNAL_KLDSCP_DVO1",
254 "INTERNAL_KLDSCP_DAC1",
255 "INTERNAL_KLDSCP_DAC2",
264 "INTERNAL_KLDSCP_LVTMA",
269 static const char *connector_names
[15] = {
287 static const char *hpd_names
[6] = {
296 static void radeon_print_display_setup(struct drm_device
*dev
)
298 struct drm_connector
*connector
;
299 struct radeon_connector
*radeon_connector
;
300 struct drm_encoder
*encoder
;
301 struct radeon_encoder
*radeon_encoder
;
305 DRM_INFO("Radeon Display Connectors\n");
306 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
307 radeon_connector
= to_radeon_connector(connector
);
308 DRM_INFO("Connector %d:\n", i
);
309 DRM_INFO(" %s\n", connector_names
[connector
->connector_type
]);
310 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
311 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
312 if (radeon_connector
->ddc_bus
) {
313 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
314 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
315 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
316 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
317 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
318 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
319 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
320 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
321 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
323 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
324 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
325 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
326 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
327 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
328 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
329 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
331 DRM_INFO(" Encoders:\n");
332 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
333 radeon_encoder
= to_radeon_encoder(encoder
);
334 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
336 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
337 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
338 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
339 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
340 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
341 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
342 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
343 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
344 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
345 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
346 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
347 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
348 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
349 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
350 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
351 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
352 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
353 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
354 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
355 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
362 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
364 struct radeon_device
*rdev
= dev
->dev_private
;
365 struct drm_connector
*drm_connector
;
369 if (rdev
->is_atom_bios
) {
370 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
372 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
374 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
376 ret
= radeon_get_legacy_connector_info_from_table(dev
);
379 if (!ASIC_IS_AVIVO(rdev
))
380 ret
= radeon_get_legacy_connector_info_from_table(dev
);
383 radeon_setup_encoder_clones(dev
);
384 radeon_print_display_setup(dev
);
385 list_for_each_entry(drm_connector
, &dev
->mode_config
.connector_list
, head
)
386 radeon_ddc_dump(drm_connector
);
392 int radeon_ddc_get_modes(struct radeon_connector
*radeon_connector
)
394 struct drm_device
*dev
= radeon_connector
->base
.dev
;
395 struct radeon_device
*rdev
= dev
->dev_private
;
398 if ((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_DisplayPort
) ||
399 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
400 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
401 if ((dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
||
402 dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
) && dig
->dp_i2c_bus
)
403 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &dig
->dp_i2c_bus
->adapter
);
405 if (!radeon_connector
->ddc_bus
)
407 if (!radeon_connector
->edid
) {
408 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &radeon_connector
->ddc_bus
->adapter
);
410 /* some servers provide a hardcoded edid in rom for KVMs */
411 if (!radeon_connector
->edid
)
412 radeon_connector
->edid
= radeon_combios_get_hardcoded_edid(rdev
);
413 if (radeon_connector
->edid
) {
414 drm_mode_connector_update_edid_property(&radeon_connector
->base
, radeon_connector
->edid
);
415 ret
= drm_add_edid_modes(&radeon_connector
->base
, radeon_connector
->edid
);
418 drm_mode_connector_update_edid_property(&radeon_connector
->base
, NULL
);
422 static int radeon_ddc_dump(struct drm_connector
*connector
)
425 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
428 if (!radeon_connector
->ddc_bus
)
430 edid
= drm_get_edid(connector
, &radeon_connector
->ddc_bus
->adapter
);
437 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
447 static void radeon_compute_pll_legacy(struct radeon_pll
*pll
,
449 uint32_t *dot_clock_p
,
451 uint32_t *frac_fb_div_p
,
453 uint32_t *post_div_p
)
455 uint32_t min_ref_div
= pll
->min_ref_div
;
456 uint32_t max_ref_div
= pll
->max_ref_div
;
457 uint32_t min_post_div
= pll
->min_post_div
;
458 uint32_t max_post_div
= pll
->max_post_div
;
459 uint32_t min_fractional_feed_div
= 0;
460 uint32_t max_fractional_feed_div
= 0;
461 uint32_t best_vco
= pll
->best_vco
;
462 uint32_t best_post_div
= 1;
463 uint32_t best_ref_div
= 1;
464 uint32_t best_feedback_div
= 1;
465 uint32_t best_frac_feedback_div
= 0;
466 uint32_t best_freq
= -1;
467 uint32_t best_error
= 0xffffffff;
468 uint32_t best_vco_diff
= 1;
470 u32 pll_out_min
, pll_out_max
;
472 DRM_DEBUG("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
475 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
476 pll_out_min
= pll
->lcd_pll_out_min
;
477 pll_out_max
= pll
->lcd_pll_out_max
;
479 pll_out_min
= pll
->pll_out_min
;
480 pll_out_max
= pll
->pll_out_max
;
483 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
484 min_ref_div
= max_ref_div
= pll
->reference_div
;
486 while (min_ref_div
< max_ref_div
-1) {
487 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
488 uint32_t pll_in
= pll
->reference_freq
/ mid
;
489 if (pll_in
< pll
->pll_in_min
)
491 else if (pll_in
> pll
->pll_in_max
)
498 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
499 min_post_div
= max_post_div
= pll
->post_div
;
501 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
502 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
503 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
506 for (post_div
= min_post_div
; post_div
<= max_post_div
; ++post_div
) {
509 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
512 /* legacy radeons only have a few post_divs */
513 if (pll
->flags
& RADEON_PLL_LEGACY
) {
514 if ((post_div
== 5) ||
525 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
526 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
527 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
528 uint32_t min_feed_div
= pll
->min_feedback_div
;
529 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
531 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
534 while (min_feed_div
< max_feed_div
) {
536 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
537 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
538 uint32_t frac_feedback_div
;
541 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
543 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
544 vco
= radeon_div(tmp
, ref_div
);
546 if (vco
< pll_out_min
) {
547 min_feed_div
= feedback_div
+ 1;
549 } else if (vco
> pll_out_max
) {
550 max_feed_div
= feedback_div
;
554 while (min_frac_feed_div
< max_frac_feed_div
) {
555 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
556 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
557 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
558 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
560 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
561 error
= freq
- current_freq
;
562 error
= error
< 0 ? 0xffffffff : error
;
564 error
= abs(current_freq
- freq
);
565 vco_diff
= abs(vco
- best_vco
);
567 if ((best_vco
== 0 && error
< best_error
) ||
569 (error
< best_error
- 100 ||
570 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
571 best_post_div
= post_div
;
572 best_ref_div
= ref_div
;
573 best_feedback_div
= feedback_div
;
574 best_frac_feedback_div
= frac_feedback_div
;
575 best_freq
= current_freq
;
577 best_vco_diff
= vco_diff
;
578 } else if (current_freq
== freq
) {
579 if (best_freq
== -1) {
580 best_post_div
= post_div
;
581 best_ref_div
= ref_div
;
582 best_feedback_div
= feedback_div
;
583 best_frac_feedback_div
= frac_feedback_div
;
584 best_freq
= current_freq
;
586 best_vco_diff
= vco_diff
;
587 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
588 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
589 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
590 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
591 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
592 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
593 best_post_div
= post_div
;
594 best_ref_div
= ref_div
;
595 best_feedback_div
= feedback_div
;
596 best_frac_feedback_div
= frac_feedback_div
;
597 best_freq
= current_freq
;
599 best_vco_diff
= vco_diff
;
602 if (current_freq
< freq
)
603 min_frac_feed_div
= frac_feedback_div
+ 1;
605 max_frac_feed_div
= frac_feedback_div
;
607 if (current_freq
< freq
)
608 min_feed_div
= feedback_div
+ 1;
610 max_feed_div
= feedback_div
;
615 *dot_clock_p
= best_freq
/ 10000;
616 *fb_div_p
= best_feedback_div
;
617 *frac_fb_div_p
= best_frac_feedback_div
;
618 *ref_div_p
= best_ref_div
;
619 *post_div_p
= best_post_div
;
623 calc_fb_div(struct radeon_pll
*pll
,
628 uint32_t *fb_div_frac
)
630 fixed20_12 feedback_divider
, a
, b
;
633 vco_freq
= freq
* post_div
;
634 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
635 a
.full
= dfixed_const(pll
->reference_freq
);
636 feedback_divider
.full
= dfixed_const(vco_freq
);
637 feedback_divider
.full
= dfixed_div(feedback_divider
, a
);
638 a
.full
= dfixed_const(ref_div
);
639 feedback_divider
.full
= dfixed_mul(feedback_divider
, a
);
641 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
642 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
643 a
.full
= dfixed_const(10);
644 feedback_divider
.full
= dfixed_mul(feedback_divider
, a
);
645 feedback_divider
.full
+= dfixed_const_half(0);
646 feedback_divider
.full
= dfixed_floor(feedback_divider
);
647 feedback_divider
.full
= dfixed_div(feedback_divider
, a
);
649 /* *fb_div = floor(feedback_divider); */
650 a
.full
= dfixed_floor(feedback_divider
);
651 *fb_div
= dfixed_trunc(a
);
652 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
653 a
.full
= dfixed_const(10);
654 b
.full
= dfixed_mul(feedback_divider
, a
);
656 feedback_divider
.full
= dfixed_floor(feedback_divider
);
657 feedback_divider
.full
= dfixed_mul(feedback_divider
, a
);
658 feedback_divider
.full
= b
.full
- feedback_divider
.full
;
659 *fb_div_frac
= dfixed_trunc(feedback_divider
);
661 /* *fb_div = floor(feedback_divider + 0.5); */
662 feedback_divider
.full
+= dfixed_const_half(0);
663 feedback_divider
.full
= dfixed_floor(feedback_divider
);
665 *fb_div
= dfixed_trunc(feedback_divider
);
669 if (((*fb_div
) < pll
->min_feedback_div
) || ((*fb_div
) > pll
->max_feedback_div
))
676 calc_fb_ref_div(struct radeon_pll
*pll
,
680 uint32_t *fb_div_frac
,
683 fixed20_12 ffreq
, max_error
, error
, pll_out
, a
;
685 u32 pll_out_min
, pll_out_max
;
687 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
688 pll_out_min
= pll
->lcd_pll_out_min
;
689 pll_out_max
= pll
->lcd_pll_out_max
;
691 pll_out_min
= pll
->pll_out_min
;
692 pll_out_max
= pll
->pll_out_max
;
695 ffreq
.full
= dfixed_const(freq
);
696 /* max_error = ffreq * 0.0025; */
697 a
.full
= dfixed_const(400);
698 max_error
.full
= dfixed_div(ffreq
, a
);
700 for ((*ref_div
) = pll
->min_ref_div
; (*ref_div
) < pll
->max_ref_div
; ++(*ref_div
)) {
701 if (calc_fb_div(pll
, freq
, post_div
, (*ref_div
), fb_div
, fb_div_frac
)) {
702 vco
= pll
->reference_freq
* (((*fb_div
) * 10) + (*fb_div_frac
));
703 vco
= vco
/ ((*ref_div
) * 10);
705 if ((vco
< pll_out_min
) || (vco
> pll_out_max
))
708 /* pll_out = vco / post_div; */
709 a
.full
= dfixed_const(post_div
);
710 pll_out
.full
= dfixed_const(vco
);
711 pll_out
.full
= dfixed_div(pll_out
, a
);
713 if (pll_out
.full
>= ffreq
.full
) {
714 error
.full
= pll_out
.full
- ffreq
.full
;
715 if (error
.full
<= max_error
.full
)
723 static void radeon_compute_pll_new(struct radeon_pll
*pll
,
725 uint32_t *dot_clock_p
,
727 uint32_t *frac_fb_div_p
,
729 uint32_t *post_div_p
)
731 u32 fb_div
= 0, fb_div_frac
= 0, post_div
= 0, ref_div
= 0;
732 u32 best_freq
= 0, vco_frequency
;
733 u32 pll_out_min
, pll_out_max
;
735 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
736 pll_out_min
= pll
->lcd_pll_out_min
;
737 pll_out_max
= pll
->lcd_pll_out_max
;
739 pll_out_min
= pll
->pll_out_min
;
740 pll_out_max
= pll
->pll_out_max
;
743 /* freq = freq / 10; */
746 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
) {
747 post_div
= pll
->post_div
;
748 if ((post_div
< pll
->min_post_div
) || (post_div
> pll
->max_post_div
))
751 vco_frequency
= freq
* post_div
;
752 if ((vco_frequency
< pll_out_min
) || (vco_frequency
> pll_out_max
))
755 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
) {
756 ref_div
= pll
->reference_div
;
757 if ((ref_div
< pll
->min_ref_div
) || (ref_div
> pll
->max_ref_div
))
759 if (!calc_fb_div(pll
, freq
, post_div
, ref_div
, &fb_div
, &fb_div_frac
))
763 for (post_div
= pll
->max_post_div
; post_div
>= pll
->min_post_div
; --post_div
) {
764 if (pll
->flags
& RADEON_PLL_LEGACY
) {
765 if ((post_div
== 5) ||
773 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
776 vco_frequency
= freq
* post_div
;
777 if ((vco_frequency
< pll_out_min
) || (vco_frequency
> pll_out_max
))
779 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
) {
780 ref_div
= pll
->reference_div
;
781 if ((ref_div
< pll
->min_ref_div
) || (ref_div
> pll
->max_ref_div
))
783 if (calc_fb_div(pll
, freq
, post_div
, ref_div
, &fb_div
, &fb_div_frac
))
786 if (calc_fb_ref_div(pll
, freq
, post_div
, &fb_div
, &fb_div_frac
, &ref_div
))
792 best_freq
= pll
->reference_freq
* 10 * fb_div
;
793 best_freq
+= pll
->reference_freq
* fb_div_frac
;
794 best_freq
= best_freq
/ (ref_div
* post_div
);
798 DRM_ERROR("Couldn't find valid PLL dividers\n");
800 *dot_clock_p
= best_freq
/ 10;
802 *frac_fb_div_p
= fb_div_frac
;
803 *ref_div_p
= ref_div
;
804 *post_div_p
= post_div
;
806 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p
, *fb_div_p
, *frac_fb_div_p
, *ref_div_p
, *post_div_p
);
809 void radeon_compute_pll(struct radeon_pll
*pll
,
811 uint32_t *dot_clock_p
,
813 uint32_t *frac_fb_div_p
,
815 uint32_t *post_div_p
)
819 radeon_compute_pll_new(pll
, freq
, dot_clock_p
, fb_div_p
,
820 frac_fb_div_p
, ref_div_p
, post_div_p
);
822 case PLL_ALGO_LEGACY
:
824 radeon_compute_pll_legacy(pll
, freq
, dot_clock_p
, fb_div_p
,
825 frac_fb_div_p
, ref_div_p
, post_div_p
);
830 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
832 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
835 drm_gem_object_unreference_unlocked(radeon_fb
->obj
);
836 drm_framebuffer_cleanup(fb
);
840 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
841 struct drm_file
*file_priv
,
842 unsigned int *handle
)
844 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
846 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
849 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
850 .destroy
= radeon_user_framebuffer_destroy
,
851 .create_handle
= radeon_user_framebuffer_create_handle
,
855 radeon_framebuffer_init(struct drm_device
*dev
,
856 struct radeon_framebuffer
*rfb
,
857 struct drm_mode_fb_cmd
*mode_cmd
,
858 struct drm_gem_object
*obj
)
861 drm_framebuffer_init(dev
, &rfb
->base
, &radeon_fb_funcs
);
862 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
865 static struct drm_framebuffer
*
866 radeon_user_framebuffer_create(struct drm_device
*dev
,
867 struct drm_file
*file_priv
,
868 struct drm_mode_fb_cmd
*mode_cmd
)
870 struct drm_gem_object
*obj
;
871 struct radeon_framebuffer
*radeon_fb
;
873 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handle
);
875 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
876 "can't create framebuffer\n", mode_cmd
->handle
);
880 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
881 if (radeon_fb
== NULL
) {
885 radeon_framebuffer_init(dev
, radeon_fb
, mode_cmd
, obj
);
887 return &radeon_fb
->base
;
890 static void radeon_output_poll_changed(struct drm_device
*dev
)
892 struct radeon_device
*rdev
= dev
->dev_private
;
893 radeon_fb_output_poll_changed(rdev
);
896 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
897 .fb_create
= radeon_user_framebuffer_create
,
898 .output_poll_changed
= radeon_output_poll_changed
901 struct drm_prop_enum_list
{
906 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
911 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
912 { { TV_STD_NTSC
, "ntsc" },
913 { TV_STD_PAL
, "pal" },
914 { TV_STD_PAL_M
, "pal-m" },
915 { TV_STD_PAL_60
, "pal-60" },
916 { TV_STD_NTSC_J
, "ntsc-j" },
917 { TV_STD_SCART_PAL
, "scart-pal" },
918 { TV_STD_PAL_CN
, "pal-cn" },
919 { TV_STD_SECAM
, "secam" },
922 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
926 if (rdev
->is_atom_bios
) {
927 rdev
->mode_info
.coherent_mode_property
=
928 drm_property_create(rdev
->ddev
,
931 if (!rdev
->mode_info
.coherent_mode_property
)
934 rdev
->mode_info
.coherent_mode_property
->values
[0] = 0;
935 rdev
->mode_info
.coherent_mode_property
->values
[1] = 1;
938 if (!ASIC_IS_AVIVO(rdev
)) {
939 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
940 rdev
->mode_info
.tmds_pll_property
=
941 drm_property_create(rdev
->ddev
,
944 for (i
= 0; i
< sz
; i
++) {
945 drm_property_add_enum(rdev
->mode_info
.tmds_pll_property
,
947 radeon_tmds_pll_enum_list
[i
].type
,
948 radeon_tmds_pll_enum_list
[i
].name
);
952 rdev
->mode_info
.load_detect_property
=
953 drm_property_create(rdev
->ddev
,
955 "load detection", 2);
956 if (!rdev
->mode_info
.load_detect_property
)
958 rdev
->mode_info
.load_detect_property
->values
[0] = 0;
959 rdev
->mode_info
.load_detect_property
->values
[1] = 1;
961 drm_mode_create_scaling_mode_property(rdev
->ddev
);
963 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
964 rdev
->mode_info
.tv_std_property
=
965 drm_property_create(rdev
->ddev
,
968 for (i
= 0; i
< sz
; i
++) {
969 drm_property_add_enum(rdev
->mode_info
.tv_std_property
,
971 radeon_tv_std_enum_list
[i
].type
,
972 radeon_tv_std_enum_list
[i
].name
);
978 void radeon_update_display_priority(struct radeon_device
*rdev
)
980 /* adjustment options for the display watermarks */
981 if ((radeon_disp_priority
== 0) || (radeon_disp_priority
> 2)) {
982 /* set display priority to high for r3xx, rv515 chips
983 * this avoids flickering due to underflow to the
984 * display controllers during heavy acceleration.
985 * Don't force high on rs4xx igp chips as it seems to
986 * affect the sound card. See kernel bug 15982.
988 if ((ASIC_IS_R300(rdev
) || (rdev
->family
== CHIP_RV515
)) &&
989 !(rdev
->flags
& RADEON_IS_IGP
))
990 rdev
->disp_priority
= 2;
992 rdev
->disp_priority
= 0;
994 rdev
->disp_priority
= radeon_disp_priority
;
998 int radeon_modeset_init(struct radeon_device
*rdev
)
1003 drm_mode_config_init(rdev
->ddev
);
1004 rdev
->mode_info
.mode_config_initialized
= true;
1006 rdev
->ddev
->mode_config
.funcs
= (void *)&radeon_mode_funcs
;
1008 if (ASIC_IS_AVIVO(rdev
)) {
1009 rdev
->ddev
->mode_config
.max_width
= 8192;
1010 rdev
->ddev
->mode_config
.max_height
= 8192;
1012 rdev
->ddev
->mode_config
.max_width
= 4096;
1013 rdev
->ddev
->mode_config
.max_height
= 4096;
1016 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
1018 ret
= radeon_modeset_create_props(rdev
);
1023 /* check combios for a valid hardcoded EDID - Sun servers */
1024 if (!rdev
->is_atom_bios
) {
1025 /* check for hardcoded EDID in BIOS */
1026 radeon_combios_check_hardcoded_edid(rdev
);
1029 /* allocate crtcs */
1030 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1031 radeon_crtc_init(rdev
->ddev
, i
);
1034 /* okay we should have all the bios connectors */
1035 ret
= radeon_setup_enc_conn(rdev
->ddev
);
1039 /* initialize hpd */
1040 radeon_hpd_init(rdev
);
1042 /* Initialize power management */
1043 radeon_pm_init(rdev
);
1045 radeon_fbdev_init(rdev
);
1046 drm_kms_helper_poll_init(rdev
->ddev
);
1051 void radeon_modeset_fini(struct radeon_device
*rdev
)
1053 radeon_fbdev_fini(rdev
);
1054 kfree(rdev
->mode_info
.bios_hardcoded_edid
);
1055 radeon_pm_fini(rdev
);
1057 if (rdev
->mode_info
.mode_config_initialized
) {
1058 drm_kms_helper_poll_fini(rdev
->ddev
);
1059 radeon_hpd_fini(rdev
);
1060 drm_mode_config_cleanup(rdev
->ddev
);
1061 rdev
->mode_info
.mode_config_initialized
= false;
1065 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
1066 struct drm_display_mode
*mode
,
1067 struct drm_display_mode
*adjusted_mode
)
1069 struct drm_device
*dev
= crtc
->dev
;
1070 struct drm_encoder
*encoder
;
1071 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1072 struct radeon_encoder
*radeon_encoder
;
1075 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1076 radeon_encoder
= to_radeon_encoder(encoder
);
1077 if (encoder
->crtc
!= crtc
)
1081 if (radeon_encoder
->rmx_type
== RMX_OFF
)
1082 radeon_crtc
->rmx_type
= RMX_OFF
;
1083 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
1084 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
1085 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
1087 radeon_crtc
->rmx_type
= RMX_OFF
;
1088 /* copy native mode */
1089 memcpy(&radeon_crtc
->native_mode
,
1090 &radeon_encoder
->native_mode
,
1091 sizeof(struct drm_display_mode
));
1094 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
1095 /* WARNING: Right now this can't happen but
1096 * in the future we need to check that scaling
1097 * are consistent accross different encoder
1098 * (ie all encoder can work with the same
1101 DRM_ERROR("Scaling not consistent accross encoder.\n");
1106 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
1108 a
.full
= dfixed_const(crtc
->mode
.vdisplay
);
1109 b
.full
= dfixed_const(radeon_crtc
->native_mode
.hdisplay
);
1110 radeon_crtc
->vsc
.full
= dfixed_div(a
, b
);
1111 a
.full
= dfixed_const(crtc
->mode
.hdisplay
);
1112 b
.full
= dfixed_const(radeon_crtc
->native_mode
.vdisplay
);
1113 radeon_crtc
->hsc
.full
= dfixed_div(a
, b
);
1115 radeon_crtc
->vsc
.full
= dfixed_const(1);
1116 radeon_crtc
->hsc
.full
= dfixed_const(1);